cs/ee 3700 : fundamentals of digital system design chris j. myers lecture 9: asynchronous sequential...
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CS/EE 3700 : Fundamentals of Digital System Design
Chris J. Myers
Lecture 9: Asynchronous Sequential Circuits
Chapter 9
Asynchronous Circuits
• Asynchronous sequential circuits do not use a clock or flip-flops for state variables.
• Changes in state occur in response to changes on the inputs.
• This chapter describes single input change (SIC) fundamental-mode async. circuits.
• Only one input allowed to change at a time.• Time between input changes must be sufficient for
the circuit to stabilize.
Figure 9.1 Analysis of the SR latch
R
S Q Y y
Present Next state
state SR = 00 01 10 11
y Y Y Y Y
0 0 0 1 0
1 1 0 1 0
(b) State-assigned table
(b) Circuit with modeled gate delay
Figure 9.2 FSM model for the SR latch
Present Next state Outputstate SR = 00 01 10 11 Q
A A A B A 0
B B A B A 1
(a) State table
(b) State diagram
1000
110100
10
A 0 B 1
1101
SR
Figure 9.3 Mealy representation of the SR latch
Present Nextstate Output, Q
state SR = 00 01 10 11 00 01 10 11
A A A B A 0 0 0
B B A B A 1 1
(a) State table
(b) State diagram
10/100/1
11/001/000/0
10/ –
A B
01 –11 –
SR/Q
–
–
–
Terminology
• state table = flow table
• state-assigned table = transition table or excitation table.
Figure 8.90 The general model for a sequential circuit
Combinational circuit
Y k
Y 1
y k
y 1
w 1
w n
z 1
z m
Outputs
Next-statevariables
Present-state variables
Inputs
Figure 9.4 The gated D latch
D
C
Q Y y
(a) Circuit
Present Nextstate
state CD = 00 01 10 11y Y Y Y Y Q
0 0 0 0 1 0
1 1 1 0 1 1
(b) Excitationtable
Figure 9.4 The gated D latch
Present Nextstate state CD = 00 01 10 11 Q
A A A A B 0
B B B A B 1
(c) Flowtable
(d) State diagram
x10x
x00x
11
A 0 B 1
10
CD
Figure 9.5 Circuit for the master-slave D flip-flop
D
Clk
Q
Q
D
C
Q y s y m
Master Slave
Q
D
Clk
Q
Q
Figure 9.6 Excitation and flow tables for Example 9.2
Present Next state
state CD = 00 01 10 11 Output
y m y s Y m Y s Q
00 0 0 0 0 0 0 10 0
01 00 00 0 1 11 1
10 11 11 00 1 0 0
11 1 1 1 1 01 1 1 1
(a) Excitationtable
Present Next state Outputstate CD = 00 01 10 11 Q
S1 S 1 S 1 S 1 S3 0
S2 S1 S1 S 2 S4 1
S3 S4 S4 S1 S 3 0
S4 S 4 S 4 S2 S 4 1
(b) Flow table
Figure 9.6 Excitation and flow tables for Example 9.2
Present Next state Outputstate CD = 00 01 10 11 Q
S1 S 1 S 1 S 1 S3 0
S2 S1 S1 S 2 S4 1
S3 S4 S4 S1 S 3 0
S4 S 4 S 4 S2 S 4 1
(b) Flow table
Present Next state Outputstate CD = 00 01 10 11 Q
S1 S 1 S 1 S 1 S3 0
S2 S1 S 2 S4 1
S3 S4 S1 S 3 0
S4 S 4 S 4 S2 S 4 1
(c) FlowTable with unspecifiedentries
–
–
Figure 9.7 State diagram for the master-slave D flip-flopC
x10x10
11
S2 1 S4 1 10
11x00x
11
S1 0 S3 0 10
0x0x
CD
Figure 9.8 Circuit for Example 9.3
z y 1
y 2
Y 1
Y 2
w 1
w 2
Figure 9.9 Excitation and flow tables
Present Next state
state w 2 w 1 = 00 01 10 11 Output
y 2 y 1 Y 2 Y 1 Y 2 Y 1 Y 2 Y 1 Y 2 Y 1 z
00 0 0 01 10 11 0
01 11 0 1 11 11 0
10 00 1 0 1 0 1 0 1
11 1 1 10 10 10 0
(a) Excitation table
Present Next state Outputstate w 2 w 1 = 00 01 10 11 z
A A B C D 0
B D B D D 0
C A C C C 1
D D C C C 0
(b) Flow table
Figure 9.10 Modified flow table for Example 9.3
Present Next state Outputstate w 2 w 1 = 00 01 10 11 z
A A B C 0
B D B D 0
C A C C C 1
D D C C C 0
––
Figure 9.11 State table for Example 9.3
01
x11x
10
w2w1
A/0
C/1
B/0
D/0 00
00
00 0011
x11x
01
Figure 9.12 Flow table for a simple vending machine
Present Next state Outputstate w 2 w 1 = 00 01 10 11 z
A A B C 0
B D B 0
C A C C 1
D D C C 0
w 2 dime w 1 nickel
–––––
Steps in the Analysis Process
• Cut feedback paths and insert delay element.– Input to delay element is next-state, and output is the
present-state.– Cut set may not be unique.
• Derive next-state and output expressions from the circuit.
• Derive the excitation table.• Derive a flow table.• Derive a state diagram, if desired.
Synthesis of Asynchronous Circuits
• Devise a state diagram.
• Derive the flow table.
• Minimize number of states.
• Perform race-free state assignment.
• Derive excitation table.
• Obtain next-state and output expressions.
• Construct a hazard-free circuit.
Figure 9.13 Parity-generating asynchronous FSM
(a) State diagram
Present Next state OutputState w = 0 w = 1 z
A A B 0
B C B 1
C C D 1
D A D 0
(b) Flow table
1
1
0
A/0
D/0
B/1
C/1 0
0
0
1
1
Figure 9.14 State assignment
Present Next state
state w = 0 w = 1 Output
y 2 y 1 Y 2 Y 1 z
00 0 0 01 0
01 10 0 1 1
10 1 0 11 1
11 00 1 1 0
(a) Poor state assignment
Present Next state
state w = 0 w = 1 Output
y 2 y 1 Y 2 Y 1 z
00 0 0 01 0
01 11 0 1 1
11 1 1 10 1
10 00 1 0 0
(b) Good state assignment
Figure 9.14 State assignment
Figure 9.15 Circuit that implements an FSM
y 1
y 2
w
z
Figure 9.16 Synchronous solution for Example 9.4
w
z D Q
Q
Figure 9.17 State diagram for a modulo-4 counter
1
1
0
A 0
H 0
B 1
G 3
0
0
1
1 C 1
F 3
D 2
E 2
1
0 1
0
0
1
1
0
0
Figure 9.18 Flow and excitation tables for a modulo-4 counter
Present Nextstate Outputstate w = 0 w = 1 z
A A B 0
B C B 1
C C D 1
D E D 2
E E F 2
F G F 3
G G H 3
H A H 0
(a) Flowtable
Figure 9.18 Flow and excitation tables for a modulo-4 counter
Present Next state
state w = 0 w = 1 Output Mod-8 output
y 3 y 2 y 1 Y 3 Y 2 Y 1 z 2 z 1 z 3 z 2 z 1
000 0 00 001 00 000
001 011 0 01 01 001
011 0 11 010 01 010
010 110 0 10 10 011
110 1 10 111 10 100
111 101 1 11 11 101
101 1 01 100 11 110
100 000 1 00 00 111
(b) Excitation table (c) Output for countingthe edges
Figure 9.19 Arbitration example
Arbiter
Request1
Grant1
Request2
Grant2
Device 1
Device 2
Sharedresource
(a) Arbitration structure
Request (r)
Grant (g)
(b) Handshake signaling
Figure 9.20 State diagram for the arbiter
01A 0 0 B 01
C 10
0011
00
00
10
01
10
0111
1011
r 2 r 1
Figure 9.21 Implementation of the arbiter
Present Nextstate Outputstate r 2 r 1 = 00 01 10 11 g
2 g 1
A A B C B 00
B A B C B 01
C A B C C 10
(a) Flowtable
Present Nextstate
state r 2 r 1 = 00 01 10 11 Output
y 2 y 1 Y 2 Y 1 g 2 g 1
A 00 0 0 01 10 01 00
B 01 00 0 1 10 0 1 01
C 10 00 01 1 0 1 0 10
D 11 01 10 dd
(b) Excitationtable
Figure 9.22 The arbiter circuit
y 2
g 1
g 2
r 1
r 2
THIS CIRCUIT IS WRONG!
Figure 9.23 An alternative for avoiding a critical race
Present Next state Outputstate r 2 r 1 = 00 01 10 11
g 2 g 1
A A B C B 00
B A B A B 01
C A A C C 10
(a) Modified flow table
Present Next state
state r 2 r 1 = 00 01 10 11Output
y 2 y 1 Y 2 Y 1 g 2 g 1
00 0 0 01 10 01 00
01 00 0 1 00 0 1 01
10 00 00 1 0 1 0 10
(b) Modified excitation table
Figure 9.24 Mealy model for the arbiter FSM
1x 1000 00
x1 0100 00
10 0 –
B C
01 0–
Present Next state Output g 2 g 1
state r 2 r 1 = 00 01 10 11 00 01 10 11
B B B C B 00 01 –0 01
C C B C C 00 0– 10 10
(a) Flow diagram
Figure 9.25 Mealy model implementation of the arbiter FSM
Present Next state Output
state r 2 r 1 = 00 01 10 11 00 01 10 11
y Y g 2 g 1
0 0 0 1 0 00 01 d 0 01
1 1 0 1 1 00 0 d 10 10
(b) Excitation table
State Reduction
• Usually start with primitive flow table (i.e., only a single stable state per row).
• Asynchronous FSMs likely have many unspecified (don’t care) entries.
• Two-step state reduction process:– Apply partitioning procedure in which don’t
care entries must match.– Merge rows exploiting don’t cares.
Figure 9.26 Derivation of an FSM for the simple vending machine
A 0
B 0 C 1
D 0
E 1 F 1
0 0
0
0 0
0
D
N
N
N
N
D
D
0
D
(a) Initial statediagram
Figure 9.26 Derivation of an FSM for the simple vending machine
Present Nextstate OutputState DN = 00 01 10 11 z
A A B C 0
B D B 0
C A C 1
D D E F 0
E A E 1
F A F 1
(b) Initial flowtable
–
–
–
–
–
–
–
–
–
–
Figure 9.27 First-step reduction of the vending machine FSM
Present Next state Outputstate DN = 00 01 10 11 z
A A B C 0
B D B 0
C A C 1
D D E C 0
E A E 1
–––––––
–
Figure 9.12 Flow table for a simple vending machine
Present Next state Outputstate w 2 w 1 = 00 01 10 11 z
A A B C 0
B D B 0
C A C C 1
D D C C 0
w 2 dime w 1 nickel
–––––
Merging Procedure
• May be many possibilities for row mergers.• Two states Si and Sj are compatible if there
are no state conflicts for any input.– both Si and Sj have same successor, or– both Si and Sj are stable, or– the successor of Si or Sj or both is unspecified.
• Si and Sj must also have same output when specified.
Figure 9.28 A primitive flow table
Present Next state Outputstate w 2 w 1 = 00 01 10 11 z
A A H B 0
B F B C 0
C H C 1
D A D E 1
E D G E 1
F F D 0
G F G 0
H H E 0
––
––
––
–
–
–
–
– –
Figure 9.29 Merger diagram (which preserves the Moore model)
E G
B
F
C
H
A D
Figure 9.30 Reduced Moore-type flow table
Present Next state Outputstate w 2 w 1 = 00 01 10 11 z
A A A B D 0
B B D B C 0
C A C 1
D A D B D 1
– –
Figure 9.31 Complete merger diagram
G
A
F
C
H
B
D
E
State Reduction Procedure
1. Use partitioning procedure to eliminate equivalent states in primitive flow table.
2. Construct merger diagram.
3. Choose subsets of equivalent states including each state in only one subset.
4. Derive reduced flow table.
5. Repeat 2 to 4 until no reduction.
Figure 9.32 Flow table for Example 9.8
Present Next state Outputstate w 2 w 1 = 00 01 10 11 z
A A F C 0
B A B H 1
C G C D 0
D F D 1
E G E D 1
F F K 0
G G B J 0
H L E H 1
J G J 0
K B E K 1
L A L K 1
–
–
–
–
–
–
–
–
–
–
–
––
–
Figure 9.33 Reduction obtained by using the partitioning procedure
Present Next state Outputstate w 2 w 1 = 00 01 10 11 z
A A F C 0
B A B H 1
C G C D 0
D F D 1
E G E D 1
F F H 0
G G B J 0
H B E H 1
J G J 0
–
–
–
–
–
–
–
–
–
––
–
Figure 9.34 Merger diagram
G F
A
J
C
E
D
H
B
Figure 9.35 Reduction obtained from the merger diagram
Present Next state Outputstate w 2 w 1 = 00 01 10 11 z
A A A C B 0
B A B D B 1
C G C D 0
D G A D D 1
G G B G 0
–
–
Figure 9.36 Merger diagram
C B D G A
Figure 9.37 Reduced flow table for Example 9.8
Present Next state Outputstate w 2 w 1 = 00 01 10 11 z
A A A C B 0
B A B D B 1
C C B C D 0
D C A D D 1
Figure 9.38 Flow table for Example 9.9
Present Next state Outputstate w 2 w 1 = 00 01 10 11 z
A A G E 0
B K B D 0
C F C H 1
D C E D 0
E A E D 1
F F C J 0
G K G D 1
H E H 1
J F J D 0
K K C B 0
––
––
––
–––
–
–
Figure 9.39 Reduction resulting from the partitioning procedure
Present Next state Outputstate w 2 w 1 = 00 01 10 11 z
A A G E 0
B F B D 0
C F C H 1
D C E D 0
E A E D 1
F F C B 0
G F G D 1
H E H 1
––
––
––
–––
Figure 9.40 Merger diagrams
D B C A
E F H G
(a) Preserving the Moore model
G H C A
B D F E
(b) Complete merger diagram
Figure 9.41 An FSM specified in the form of a Mealy model
Present Next state Output z
state w 2 w 1 = 00 01 10 11 00 01 10 11
A A G E 0
B F B D 0 0 0
C F C H 1 1
D C E D 0
E A E D 1
F F C B 0 0
G F G D 1
H E H 1 1
––
––
––
––– ––
––
––
––
–
––––
–
–––
– –
Figure 9.42 Reduced flow table for Example 9.9
Present Next state Output z
state w 2 w 1 = 00 01 10 11 00 01 10 11
A A B D A 0 1 1
B C B B D 0 1 0 0
C C C B A 0 1 0 1
D A C D D 1 0 – –
–
Figure 9.43 Flow table for Example 9.9
Present Next state Outputstate w 2 w 1 = 00 01 10 11 z
A A B C 0
B F B H 0
C F C H 0
D D G C 1
E A E H 0
F F E C 0
G D G H 0
H G C H 1
––
––
––
––
Figure 9.44 Reduction after the partitioning procedure
Present Next state Outputstate w 2 w 1 = 00 01 10 11 z
A A B C 0
B A B H 0
C A C H 0
D D G C 1
G D G H 0
H G C H 1
––
––
––
Figure 9.45 Merger diagram
H
B
C
G
D
A
Figure 9.46 Reduced flow table for Example 9.10
Present Next state Output z
state w 2 w 1 = 00 01 10 11 00 01 10 11
A A A A D 0 0 0
D D D A D 1 0 1
––
State Assignment
• Impossible to ensure that a change of two or more state variables occur at the same time.
• To achieve reliable operation, should make state variables change one at a time.
• Hamming distance is number of bits different in two bit strings.
• Ideal state assignment has Hamming distance of 1 for all state transitions.
Figure 9.47 Transitions
(a) Corresponding to Figure 9.14a
(b) Corresponding to Figure 9.14 b
C 10= D 11=
A 00= B 01=
w 0= w 0=
w 1=
w 1=
D 10= C 11=
A 00= B 01=
w 0= w 0=
w 1=
w 1=
Present Nextstate
state w = 0 w = 1 Output
y 2 y 1 Y 2 Y 1 z
00 0 0 01 0
01 11 0 1 1
11 1 1 10 1
10 00 1 0 0
Present Nextstate
state w = 0 w = 1 Output
y 2 y 1 Y 2 Y 1 z
00 0 0 01 0
01 10 0 1 1
10 1 0 11 1
11 00 1 1 0
Figure 9.48 Transitions for the arbiter
Present Nextstate Outputstate r 2 r 1 = 00 01 10 11 g 2 g 1 A A B C B 00
B A B C B 01
C A B C C 10
Present Nextstate
state r 2 r 1 = 00 01 10 11 Output
y 2 y 1 Y 2 Y 1 g 2 g 1
A 00 0 0 01 10 01 00
B 01 00 0 1 10 0 1 01
C 10 00 01 1 0 1 0 10
D 11 01 10 dd
(a) Transitions in Figure 9.21 a
(b) Using the extra state D
C 10=
A 00= B 01=
0010
01
01
C 10= D 11=
A 00= B 01=
00 10
10
01
11
01
01
11
10
10
00
00
Figure 9.49 Modified flow table
Present Next state Outputstate r 2 r 1 = 00 01 10 11 g 2 g 1
A A B C B 00
B A B D B 01
C A D C C 10
D B C 10– –
Transition Diagram
• Transition diagram illustrates all transitions in a flow table.
• Good state assignment means no diagonals in the transition diagram.
• Must embed the transition diagram onto ak-dimensional cube.
• n state variables can be embedded onto an n-dimensional cube.
Figure 9.50 Relabeled flow table
Present Next state Outputstate r 2 r 1 = 00 01 10 11 g 2 g 1
A 1 2 4 3 00
B 1 2 4 3 01
C 1 2 4 5 10
Figure 9.51 Transition diagrams
(c) Selected transition diagram
(a) Transitions in Figure 9.50 (b) Complete transition diagram
C 10=
A 00= B 01=1 2 3
1 4 2 4
C 10=
A 00= B 01=1 2 34
1 4 2 2 4 1
C 10=
A 00= B 01=1 2 34
1 4 2
Deriving Transition Diagrams
• Derive relabeled flow table.– Transitions through unstable states that lead to
stable state are given the same number.
• Represent each row of flow table by vertex.• Join Vi and Vj by edge if they have same
number in any column.• For any column in which Vi and Vj have
same number, label edge with that number.
Figure 9.52 Flow tables
Present Next state Outputstate w 2 w 1 = 00 01 10 11 z 2 z 1
A A B C A 00
B B B D C 01
C A C D C 10
D B D A 11
(a) Flow table
Present Next state Outputstate w 2 w 1 = 00 01 10 11 z 2 z 1
A 1 4 7 2 00
B 3 4 7 6 01
C 1 5 7 6 10
D 3 7 2 11
(b) Relabeled flow table
–
–
Figure 9.53 Transition diagrams
B
(a) First transition diagram (b) Second transition diagram
D 10=
A 00= 4 7 ,
2 7 , 6 7 ,
(c) Augmented transition diagram
C 11=
1 7 ,
3 7 ,
7 D 10=
A 00= C 01= 1 7 ,
2 7 , 6 7 ,
B 11=
4 7 ,
7
3 7 ,
D 10=
A 00= C 01= 1 7 ,
2 7 4 , , 6 7 ,
B 11= 3 7 4 , ,
B 01=
Figure 9.54 Realization of an FSM
Present Next state Output z 2 z 1
state w 2 w 1 = 00 01 10 11 00 01 10 11
A A D D A 00 00 11 00
B B B D C 01 01 11 01
C A C B C –0 10 1– 10
D B B D A –1 0– 11 00
(a) Modified flow table
Present Next state Output
state w 2 w 1 = 00 01 10 11 00 01 10 11y 2 y 1 Y 2 Y 1 z 2 z 1
A 00 0 0 10 10 0 0 00 00 11 00
B 11 1 1 1 1 10 01 01 01 11 01
C 01 00 0 1 11 0 1 10 10
D 10 11 11 1 0 00 11 00
(b) Excitation table
–0 1–
–1 0–
Figure 9.55 FSM for Example 9.14
Present Nextstate Outputstate w 2 w 1 = 00 01 10 11 z 2 z 1
A A A C B 00
B A B D B 01
C C B C D 10
D C A D D 11
(a) Flow table
Present Nextstate Outputstate w 2 w 1 = 00 01 10 11 z 2 z 1
A 1 2 6 4 00
B 1 3 7 4 01
C 5 3 6 8 10
D 5 2 7 8 11
(b) Relabeled flow table
Figure 9.56 Transition diagrams
(a) Transition diagram (b) Augmented transition diagram
A
D C 5 8 ,
2 3
(c) Embedded transition diagram
B
7 6
1 4 , A
D C 5 8 ,
2
3
B
7 6
1 4 ,
5 8 ,
3
7
G
E
D
A B
E
F C
G
7
5 8 ,
1 4 , 3
3 2
7
y 2 y 3
y 1
F
6
5 8 ,
Figure 9.57 Modified tables for Example 9.14
Present Nextstate Outputstate w 2 w 1 = 00 01 10 11 z 2 z 1
A A A C B 00
B A B E B 01
C C F C G 10
D G A D D 11
E D –1
F B 01
G C D 1–
(a) Modified flow table
–– –
– –
– –
–
Figure 9.57 Modified tables for Example 9.14
Present Next state
state w 2 w 1 = 00 01 10 11 Output
y 3 y 2 y 1 Y 3 Y 2 Y 1 z 2 z 1
A 000 0
00 0
00 100 001 00
B 001 000 0
01 011 0
01 01
C 100 1
00 101 1
00 110 10
D 010 110 000 0
10 0
10 11
E 011 010
F 101 001 01
G 110 100 010
(b) Excitation table
–– –
– –
– –
–
–1
1–
Figure 9.58 Embedded transition diagram if two nodes per row are used
B1
A1 A2
B2
D1C1
C2
1 4
5 8
2
5 8 1 4
7
y 2
y 3
y 1
D2
6
3
Figure 9.59 Modified flow and excitation tables for Example 9.15
Present Nextstate Outputstate w 2 w 1 = 00 01 10 11 z 2 z 1
A1 A
1 A
1 C1 B1 00
A2 A
2 A
2 A1 B2 00
B1 A1 B
1 B2 B
1 01
B2 A2 B
2 D2 B
2 01
C1 C
1 C2 C
1 D1 10
C2 C
2 B1 C
2 D2 11
D1 C1 A2 D
1 D
1 11
D2 C2 D1 D
2 D
2 11
(a) Modified flow table
Figure 9.59 Modified flow and excitation tables for Example 9.15
Present Next state
state w 2 w 1 = 00 01 10 11 Output
y 3 y 2 y 1 Y 3 Y 2 Y 1 z 2 z 1
A1 000 0
00 0
00 100 010 00
A2 001 0
01 0
01 000 011 00
B1 010 000 0
10 011 0
10 01
B2 011 001 0
11 111 0
11 01
C1 100 1
00 110 1
00 101 10
C2 110 1
10 010 1
10 111 10
D1 101 100 001 1
01 1
01 11
D2 111 110 101 1
11 1
11 11
(b) Excitation table
Figure 9.60 State assignment with one-hot encoding
State Present Next state Outputassignment State w 2 w 1 = 00 01 10 11 z 2 z 1
0001 A A A E F 00
0010 B F B G B 01
0100 C C H C I 10
1000 D I J D D 11
0101 E C –0
0011 F A B 0–
1010 G D –1
0110 H B 01
1100 I C D 1–
1001 J A 00
– –
– –
– –– –
– ––
–
–
–
– –
Hazards
• In asynchronous circuits, undesirable glitches must not occur.
• Glitches caused by structure of circuit and propagation delays are called hazards.
• Designer must eliminate all hazards from an asynchronous circuit.
Figure 9.61 Definition of hazards
1 1 0 0
1 0 0 1
(a) Static hazard
(b) Dynamic hazard
1
0
1
0
Figure 9.62 An example of a static hazard
x 1 x 2 x 3 00 01 11 10
1
0
1
(b) Karnaugh map
1
f
x 3
(a) Circuit with a hazard
1
1
x 1
x 2 p
q
x 3
x 1
x 2
f
(c) Hazard-free circuit
Remove Static 1-Hazards
• Hazard exists whenever 2 adjacent 1s in a K-map are not covered by a single product.
• To remove all static hazards, find a cover that includes each pair of adjacent 1s.
Figure 9.63 Two-level implementation of master-slave D flip-flop
00 01 11 10
1
1 1
00
01
11
10
(b) Karnaugh maps for Y m and Y s in Figure 9.6a
1 1
1
y m y s
CD
1
1
00 01 11 10
1
1 1
00
01
11
10
1 1 1
y m y s
CD
1 1
D
C
Y m
Y s
y m
y s
p
q
r
(a) Minimum-cost circuit
Q
Figure 9.63 Two-level implementation of master-slave D flip-flop
00 01 11 10
1
1 1
00
01
11
10
(b) Karnaugh maps for Y m and Y s in Figure 9.6a
1 1
1
y m y s
CD
1
1
00 01 11 10
1
1 1
00
01
11
10
1 1 1
y m y s
CD
1 1
D
C
Y m
Y s
y m
y s
(c) Hazard-free circuit
Q
Figure 9.64 Function for Example 9.17
x 1 x 2 x 3 x 4 00 01 11 10
1 1 1
00
01
11
10
1 1
1 1
d d
d
1
Figure 9.65 Static hazard in a POS circuit
x 1 x 2 x 3 00 01 11 10
1
0
1
(b) Karnaugh map
1
f
x 3
(a) Circuit with a hazard
0
0
x 2
x 1 p
q
0 0
1
1
x 3
x 2
x 1
f
(c) Hazard-free circuit
Figure 9.66 Circuit with a dynamic hazard
(a) Circuit
x 2
x 1
x 3
x 4
b
a
c d
f
x 2 x 3 x 4
x 1
b
a
c
d
f
One gate delay
(b) Timing diagram
Significance of Hazards
• A glitch in an asynchronous circuit can cause the circuit to enter an incorrect state and possibly become stable in that state.
• Next-state logic must be hazard-free.
• Synchronous circuits can have hazards as long as they are stable by the setup time of the flip-flops.
Vending Machine Controller
• It accepts nickels and dimes.
• A total of 15 cents to release candy.
• No change given if 20 cents is deposited.
• Coins deposited one at a time.
Figure 9.67 Initial state diagram for the vending-machine controller
A 0
B 0
0
D
N
N
N
D D
C 0
J 0
K 1 L 1 N
N
D
D 0
E 0 F 1
G 0
H 1 I 1
0
N
N
N
0
0
0 0 0 D
D
0
D
D
0
0
0
0
0
Figure 9.68 Initial flow table for the vending-machine controller
Present Next state Outputstate DN = 00 01 10 11 z
A A B C 0
B D B 0
C J C 0
D D E F 0
E G E 0
F A F 1
G G H I 0
H A H 1
I A I 1
J J K L 0
K A K 1
L A L 1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Figure 9.69 First step in state minimization
Present Next state Outputstate DN = 00 01 10 11 z
A A B C 0
B D B 0
C G C 0
D D E F 0
E G E 0
F A F 1
G G H F 0
H A H 1
–
–
–
–
–
–
–
–
–
–
–
–
–
Figure 9.70 Merger diagram
B
H
A
F
D
G
C
E
Figure 9.71 Reduced flow tables
Present Next state Outputstate DN = 00 01 10 11 z
A A B C 0
B D B 0
C G C C 0
D D C F 0
F A F F 1
G G F F 0
(a) Minimized flow table
Present Next state Outputstate DN = 00 01 10 11 z
A 1 2 4 0
B 5 2 0
C 8 3 4 0
D 5 3 7 0
F 1 6 7 1
G 8 6 7 0
(b) Relabeled flow table
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Figure 9.72 State diagram for the vending-machine controller
A 0
F 1
B 0
G 0
D 0
C 0
00 01 00
00 01
01 00
00
00 0110
0110
0110
DN
10 10
Figure 9.73 Determination of the state assignment
B
A F
D
G 100
110
7
4
1
6 7
111
2
3
C
4
001 000
101
5
011 010 8
B
A F
D
G
C
7
1
2
5
4
6 7
3
7 8
(a) Transition diagram
(b) Embedded on the cube
4
Figure 9.74 Excitation table
Present Next state
state DN = 00 01 10 11 Output
y 3 y 2 y 1 Y 3 Y 2 Y 1 z
A 000 0
00 010 100 0
B 010 011 0
10 0
C 111 101 1
11 1
11 0
D 011 0
11 111 001 0
F 001 000 0
01 0
01 1
G 101 1
01 001 001 0
100 110 0
110 111 0
– –
–
–
–
–
–
–
–
–
–
–
–
Figure 9.75 Karnaugh maps for the functions in Figure 9.74
00 01 11 10
d
1
00
01
11
10
1 1
d 1
1
y 1 y 2
DN
d
d
1
d
00 01 11 10
d
1 1
00
01
11
10
1 1
d 1
d
d
y 1 y 2
DN
d
d
d
d
1
1
y 3 1 = y 3 0 =
(a) Map for Y 1
Figure 9.75 Karnaugh maps for the functions in Figure 9.74
00 01 11 10
d
00
01
11
10
1 1
d
1
y 1 y 2
DN
d
1
1
d d
00 01 11 10
d
00
01
11
10
1
d
1 d
d
y 1 y 2
DN
d
d
d
d
1
1
y 3 0 = y 3 1 =
(b) Map for Y 2
Figure 9.75 Karnaugh maps for the functions in Figure 9.74
00 01 11 10
d
00
01
11
10
1
d
1
y 1 y 2
DN
d
d d
00 01 11 10
d
1
00
01
11
10
1 1
d
1 d
d
y 1 y 2
DN
d
d
d
d
1
1
y 3 1 = y 3 0 =
(c) Map for Y 3
Summary
• Analysis of asynchronous circuits.
• Synthesis of asynchronous circuits.– State reduction– State assignment– Hazard-free logic design