csen 402 - ch4 the processor_4509

8/8/2019 CSEN 402 - Ch4 the Processor_4509

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CSEN 402 Computer Organization & Design

Spring 2010

22 April, 2010

Cha ter 4 The Processor 1

Dr.MohamedF.Ahmed

Chapter4TheProcessor

CPUperformancefactors

4.1In

troduction

Instructioncount DeterminedbyISAandcompiler

CPIandCycletime DeterminedbyCPUhardware

WewillexaminetwoMIPSimplementations Asimplifiedversion

Amore

realistic

i elined

version

Simplesubset,showsmostaspects Memoryreference:lw,sw Arithmetic/logical:add,sub,and,or,slt Controltransfer:beq,j

Chapter 4 The Processor 2Thursday, April 22, 2010


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PC instructionmemory,fetchinstruction

Registernumbers registerfile,readregisters Dependingoninstructionclass

UseALUtocalculate

Arithmeticresult

Memoryaddressforload/store

Accessdatamemoryforload/store

PC targetaddressorPC+4




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Cant just join

w res oge er

Use multiplexers




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Informationencodedinbinary

4.2L

ogicD

esign

Co

Lowvoltage=0,Highvoltage=1

Onewireperbit

Multibitdataencodedonmultiwirebuses

Combinationalelement O erateondata

nv

en

tion

s

Outputisafunctionofinput

State(sequential)elements Storeinformation


ANDgate

A

Y+ Adder

A

BY

Multiplexer

=

Arithmetic/Logic Unit

Y = F(A, B)

Chapter 4 The Processor 3

I0

I1Y

M

u

x

S

A

B

YALU

F

Thursday, April 22, 2010


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Register:stores

data

in

acircuit

Usesac oc signa to eterminew entoup atethestoredvalue

Edgetriggered:updatewhenClk changesfrom0to1

Clk


Clk

D

Q


Combinationallogictransformsdataduring

Betweenclockedges

Inputfromstateelements,outputtostateelement

Longestdelaydeterminesclockperiod



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Data ath

4.3B

uildin

ga

Datap

ElementsthatprocessdataandaddressesintheCPU

Registers,ALUs,muxs,memories,

WewillbuildaMIPSdatapath incrementally

ath


Increment by

4 for next

instruction


-

register



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Readtwo

register

operands

Writeregisterresult


Readregisteroperands Calculateaddressusin 16bitoffset

UseALU,butsignextendoffset

Load:Readmemoryandupdateregister Store:Writeregistervaluetomemory



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Readre istero erands Compareoperands

UseALU,subtractandcheckZerooutput

Calculatetargetaddress

Signextenddisplacement

t e t2p aces wor sp acement

AddtoPC+4

Alreadycalculated

by

instruction

fetch


Just

re-routes

wires


Sign-bit wire

replicated



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Cha ter 4 The Processor

Firstcutdata athdoesaninstructioninoneclockcycle

Eachdatapath elementcanonlydoonefunctionatatime

Hence,weneedseparateinstructionanddata

Usemultiplexerswherealternatedata

sourcesare

used

for

different

instructions




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ALUusedfor

=

4.4A

Sim

pleIm

plem

Branch:F=subtract

Rtype:Fdependsonfunct field

en

tation

Sch

em

eALU control Function

0000 AND


0010 add

0110 subtract

0111 set-on-less-than

1100 NOR



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Controlsignals

derived

from

instruction

0 rs rt rd shamt funct

31:26 5:025:21 20:16 15:11 10:6

35 or 43 rs rt address

31:26 25:21 20:16 15:0

R-type

Load/

Store


31:26 25:21 20:16 15:0

ranc

opcode always

read

read,

except

for load

write for

R-type

and load

sign-extend

and add




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2 address

31:26 25:0

Jump

Jumpuseswordaddress UpdatePCwithconcatenationof

Top4bitsofoldPC

26bitjumpaddress

00

Needanextracontrolsignaldecodedfromopcode



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Lon estdela determinesclock eriod

Criticalpath:loadinstruction

Instructionmemory registerfileALU datamemory registerfile

Notfeasibletovaryperiodfordifferent

Violatesdesignprinciple

Makingthecommoncasefast

Wewillimproveperformancebypipelining



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Dr.MohamedF.Ahmed

Chapter4TheProcessor

csen 402 - ch4 the processor_4509

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