Current Mode Control - Functional Basics and

Classical Analysis

Fun

dam

enta

ls o

f PW

M D

c-to

-Dc

Pow

er P

ower

Con

vers

ion

2

22

Voltage Mode ControlC

urr

ent

Mo

de

Co

ntr

ol B

asic

s

PWM

Ov

conv

rampv

refV

SV

E/A1Z

2Z

Control law:

3

33

Current Mode ControlC

urr

ent

Mo

de

Co

ntr

ol B

asic

s

Control law:

PWM

Ov

conv

refV

SV

E/A1Z

2Z

Iv

Li

4

44

Propagation of Inductor Current DisturbanceC

urr

ent

Mo

de

Co

ntr

ol B

asic

s conv

Li

conv

Li

5

55

Compensation Ramp AdditionC

urr

ent

Mo

de

Co

ntr

ol B

asic

s

conv

Iv

PWM

Ov

conv

refV

SV

E/A1Z

2Z

CSN

Li

Iv

6

66

Peak Current Mode ControlC

urr

ent

Mo

de

Co

ntr

ol B

asic

s

rampv

Li

PWM

Ov

conv

refV

SV

E/A1Z

2Z

CSN

Li

Ivrampv

conv

7

77

Sub-harmonic Oscillation and Compensation RampC

urr

ent

Mo

de

Co

ntr

ol B

asic

s

0.0

0.5

1.0

1.50.0

2.0

4.0

6.0

0

5

10

15

20

v I , v

con [

V]

i L [

A]

VS [

V]

0

5

10

15

20

VS [

V]

0.0

0.5

1.0

1.5

0.0

2.0

4.0

6.0

v I +v ra

mp,

v con [

V]

i L [

A]

No compensation ramp With compensation ramp

8

88

Current Sensing NetworkC

urr

ent

Mo

de

Co

ntr

ol B

asic

s

PWM

fR

fCxR

1 : n

RR

RD

RC

HV

0

Si

S

zD

ramp

CSN Gain :

( )v t

9

99

Benefits and Issues of Current Mode ControlC

urr

ent

Mo

de

Co

ntr

ol B

asic

s

Benefits Current Mode Control

Improved dynamic performance: most pronounced benefits for boost and

buck/boost converters

Robustness of converter dynamics: good for both CCM and DCM operations

Simple compensation design: standard two-pole one-zero compensation

Issues of Current Mode Control

Dynamic modeling and analysis: multi-loop control system

Sampling effects: sampled-data system characteristics

10

1010

Average Mode Current Mode ControlA

vera

ge

Cu

rre

nt M

od

e C

ontr

ol

Li

conv

rampv

0 A

conv

refV

SV

CSN

Li

conv

rampv

Iv1IZ

PWME/A

E/A

2IZ

2Z

1Z

11

1111

Power Factor Corrected Ac-to-Dc Converter

convCSN

Li

rampv

Iv1IZ

PWME/A

2IZ

( )Sv t

Ave

rag

e C

urr

en

t Mo

de

Con

trol

12

1212

Charge ControlC

ha

rge

Co

ntro

l

IC ISPWM

Ov

conv

refV

SV

E/A1Z

2Z

CSN

Si

Iv

Si

conv

Iv

Control law:

13

1313

Peak Current-Mode Controlled PWM ConvertersC

lass

ica

l An

alys

is o

f Cur

ren

t Mod

e C

ontr

ol

2Z

1Z

PWME / A

aX i Z

p

Y

rampv

IvCSN

conv

, , :

, , :

, , :

a X p Y i Z

i X a Y p Z

a X i Y p Z

14

1414

Small-Signal ModelC

lass

ica

l An

alys

is o

f Cur

ren

t Mod

e C

ontr

ol

(s)vF

iR

mF

d

apV dD

1:D

ˆI dC

iv

conv

2

1

1:

( )( ) :

( )

:

i x

v

m

R Rn

Z sF s

Z s

F

15

1515

Modulator GainM

od

ula

tor

Ga

in

I i Lv R i

ns fs

esrampv

Modulator gain :

When compensation rampis not used ( 0)2 1

e

ms n f

S

FT S S

16

1616

Modulator GainM

od

ula

tor

Ga

in

I i Lv R i

ns fs

esrampv

nSS O

iV V

RL

Si

VR

LS

iVR

L

Oi

VR

LS O

iV V

RL

Oi

VR

LfS

Buck converter Boost converter Buck/boostconverter

17

1717

Block Diagram RepresentationB

lock

Dia

gram

Re

pre

sen

tatio

n

vsG

pZ

vdG

isG

qZ

idG

mF

iR

vF

d

Iv

conv

Li

ov

sv

oi

Fast Current Loop :

ˆˆ ˆ( ) ( ) ( )( )

ˆ ˆ ˆ ( )( )( )

Slow Voltage Loop :

ˆˆ ˆ( ) ( ) ( )( )

ˆ ˆ ˆ( ) ( )( )

L Ii

IL

o cv

o c

i s v s d sT s

v si sd s

v s v s d sT s

v s v sd s

18

1818

Power Stage Transfer FunctionsP

ow

er

Sta

ge T

ran

sfe

r F

unct

ions

2 21 /ˆ

( )ˆ 1 / /

esrovs vs

s o o

svG s K

v s Q s

2 2

ˆ 1 /( )

ˆ 1 / /

isLis is

s o o

siG s K

v s Q s

2 2

1 / 1 /ˆ( )

ˆ 1 / /

esr rhpovd vd

o o

s svG s K

d s Q s

2 2

ˆ 1 /( ) ˆ 1 / /

idLid id

o o

siG s K

d s Q s

2 2

1 / 1 /ˆ( )

ˆ 1 / /

z esrop p

o o o

s svZ s K

i s Q s

2 2

ˆ 1 / 1 /( )

ˆ 1 / /

z esrLq q

o o o

s siZ s K

i s Q s

vsG

pZ

vdG

isG

qZ

idG

mF

iR

vF

d

Iv

conv

Li

ov

sv

oi

19

1919

Dc Gains and Corner FrequenciesP

ow

er

Sta

ge T

ran

sfe

r F

unct

ions

vsK

vdK

pK

D

SV

lR

/D R

1/ (1 )D

2/ (1 )SV D

2/ (1 )lR D

21 / ((1 ) )D R

/ (1 )D D

2/ (1 )SV D

2/ (1 )lR D

2/ ((1 ) )D D RisK

idK

qK

esr

rhp

/SV R 32 / ((1 ) )SV D R 2(1 ) / ((1 ) )SV D D R

1 1 / (1 )D 1 / (1 )D

1/ ( )cCR 1/ ( )cCR 1/ ( )cCR

2(1 ) ( / )D R L 2(1 ) / ( / )D D R L

z /lR L /lR L /lR L

is 1/ ( )CR 1/ ( )CR 1/ ( )CR

id

o

Q

1/ ( )CR 2 / ( )CR (1 ) / ( )D CR

1/ LC (1 ) /D LC (1 ) /D LC

/R C L (1 ) /D R C L (1 ) /D R C L

Buck converter Boost converter Boost/boost

20

2020

Current LoopC

urr

ent

Loo

p

o

id

20log iK

0dBci

| |iT

2 2

2 2

1 1

( )

1 1

id idi id i m i

o oo o

s s

T s K R F Ks s s s

Q Q

vsG

pZ

vdG

isG

qZ

idG

mF

iR

vF

d

Iv

conv

Li

ov

sv

oi

21

2121

Voltage Loop

vsG

pZ

vdG

isG

qZ

idG

mF

iR

vF

d

Iv

conv

Li

ov

sv

oi

( ) ( ) ( )v vd v mT s G s F s F

Vo

ltage

Loo

p

22

2222

Mason’s Gain RuleM

aso

n’s

Ga

in R

ule

th

( ) : Tranfer function of interest

:1 (sum of gains of all individual loops)

+ (sum of gain products of all two non-touching loops)

: Gain of the k forward path

:1 (sum of gains of all individual loops not touched by

k

k

H s

M

the k forward path)

+ (sum of gain products of all two non-touching loops not touched

by the k forward path)

th

th

vsG

pZ

vdG

isG

qZ

idG

mF

iR

vF

d

Iv

conv

Li

ov

sv

oi

23

2323

Overall Loop GainL

oop

Ga

in A

naly

sis

vsG

pZ

vdG

isG

qZ

idG

mF

iR

vF

d

Li

A

ov

sv

oi

11

ˆ 1( )

ˆ

ny

k kx k

vT s M

v

24

2424

Outer Loop GainL

oop

Ga

in A

naly

sis

vsG

pZ

vdG

isG

qZ

idG

mF

iR

vF

d

Li

ov

sv

oi

B

2ˆ

( )ˆy

x

vT s

v

25

2525

Stability AnalysisS

tab

ility

An

alys

is

vsG

pZ

vdG

isG

qZ

idG

mF

iR

vF

d

Iv

conv

Li

ov

sv

oi

26

2626

Absolute StabilityS

tab

ility

An

alys

is

1 2

1ˆ ( )( )

ˆ ( ) 1

T and T carry the same information on the absolute stability

vs id i m is i m vdou

s id i m vd v m

G G R F G R F Gv sA s

v s G R F G F F

-2 -1 0 1 2-2

-1

0

1

2

1T

2T

-2 -1 0 1 2-2

-1

0

1

2

1T

2T

-2-1 0 1 2

0

1

2

-2

-1

1T

2T

27

2727

Relative StabilityS

tab

ility

An

alys

is

1( ) ( ) ( )i vT s T s T s ( )

( )1 ( )v

si

T sT s

T s

-2-1 0 1 2

0

1

2

-2

-1

1T

2T

28

2828

Instability with IntegratorV

olta

ge F

eed

back

Co

mp

en

satio

n

-1

-1+1

0dB

id

esr

o

cr

-3

-2

| |vT

| |iT

1| |T

1

( ) ( )

( ) ( ) ( )

( ) ( ) ( )

i id i mi

v vd v m

i v

T s G s R F

T s G s F s F

T s T s T s

29

2929

Instability with IntegratorV

olta

ge F

eed

back

Co

mp

en

satio

n 1| |T

| |iT | |vT

iT

vT

1T

0.1 1 10 100-300

-200

-100

0

100

Pha

se [

deg]

Frequency [kHz]

-20

0

20

40

60

80

Mag

nitu

de [

dB]

30

3030

Two-Pole One-Zero Compensation and Overall Loop GainV

olta

ge F

eed

back

Co

mp

en

satio

n

1

+1

o

id2

1

zc| |vT

| |iT

0dB

1| |T

cr

ci

pc esr

1( ) ( ) ( )

( ) at frequencies where | ( ) | ( )

( ) at frequencies where | ( ) | ( )

i v

i i v

v i v

T s T s T s

T s T j T j

T s T j T j

31

3131

Outer Loop GainO

ute

r L

oop

Ga

in

-1

o

id

-2

-1

0dB -2

zc-1

-2

-1

| |vT

| |iT

2| |T

32

3232

Current Loop Design EquationC

urr

ent

Loo

p D

esig

n

+1

| |iT

0dB

i20log K 1

2 2

2 2

1 1

( ) ( )

1 1

Design equation:

2 1

2

id idi id i m id i m i

o oo o

i id i m

ms n f e

s s

T s G s R F K R F Ks s s s

Q Q

K K R F

FT S S S

33

3333

Current Loop Design ProceduresC

urr

ent

Loo

p D

esig

n

2

2

max

1

( )

1

1) Select crossover frequency :

2) Evaluate the dcgain:

3) Select the CSN gain such that

where is the maximum input voltage for the PWM block

4) Evaluate the moduator gain:

5) Evaluate the co

idi id i m

o o

i

i

s

T s K R Fs s

Q

T

R

V

mpensation ramp slope:

34

3434

Voltage Loop Design EquationV

olta

ge L

oop

Des

ign

id

0dB

zc

-1

-2

-1

| |vT

| |iT

2| |T

cr

id20log K

2

2

2

2

2

1 1

( )

1

1

( )

1

( )( )

( )

Design equation

esr rhpv vd m

esr o

idi id i m

o o

v

i

s s

T s K Fs s

s

T s K R Fs s

Q

T sT s

T s

35

3535

Voltage Loop Design ProceduresV

olta

ge L

oop

Des

ign

2

2

1 1 1

( )

1 1

1) Set compensation pole :

2) Select the compensation zero:

3) Select corssover frequency:

4) Evaluate the integrator gain:

5) Check the pha

esr rhp zcv vd m v

o pc

2

s s s

T s K F Ks s s

sQ s

T

o ose margin of and adjust to secure a 45 ~70 phase margin

6) Evaluate the circuit parameters for the voltage feedback compensation2 vT K

36

3636

Circuit for Two-Pole One Zero CompensationV

olta

ge F

eed

back

Co

mp

en

satio

n

xRrefV

1R

2R 2C

3C

2

1

1( )

( )1

vzc

pc

sK

Z s

Z s ss

37

3737

Buck Converter ExampleB

uck

Con

vert

er

Exa

mp

le

PWM

conv

4refV V

E/A

rampvIv

20 s

1R

3C

2R 2C

CSN

eS

40 F 0.1 0.1

470 F1 16 V

38

3838

Current Loop DesignB

uck

Con

vert

er

Exa

mp

le

1) crossover frequency:

2) Dc gain of :

3) CSN gain:

4) Modulator gain:

5) Compensation ramp:

i

i

T

T

39

3939

Voltage Loop DesignB

uck

Con

vert

er

Exa

mp

le

6) Compensation pole:

7) Compensation zero:

8) crossover frequency:

9) Integrator gain:

10) Voltage feedback circuit:

2T

40

4040

Loop Gain CharacteristicsB

uck

Con

vert

er

Exa

mp

le

| |vT

| |iT

2| |T

0.1 1 10 100

-20

0

20

40

Mag

nitu

de [

dB]

Frequency [kHz]

| |vT

| |iT

1| |T

0.1 1 10 100

-20

0

20

40

Mag

nitu

de [

dB]

Frequency [kHz]

31

32

1

2

Design targets:

crossover frequency: 0.2 2 10 10 r/s

crossover frequency: 2 3.39 10 r/s

Design results:

crossover frequency:

crossover frequency:

ci s

cr esr

T

T

T

T

41

4141

Overall Loop Gain and Outer Loop GainB

uck

Con

vert

er

Exa

mp

le

1| |T2| |T

1T2T

0.1 1 10 100-200

-180

-160

-140

-120

-100

-80

-60

Pha

se [

deg]

Frequency [kHz]

-40

-20

0

20

40

60

Mag

nitu

de [

dB]

Overall loop gain:

Crossover frequency

Phase margin:

Outer loop gain:

Crossover frequency

Phase margin:

42

4242

Closed-Loop PerformanceB

uck

Con

vert

er

Exa

mp

le

0.1 1 10 100-40

-30

-20

-10

Mag

nitu

de [

dB]

Frequency [kHz]

0.1 1 10 100-80

-60

-40

-20

Mag

nitu

de [

dB]

Frequency [kHz]

Output impedance

Audio-susceptibility

2.0 2.5 3.0 3.5 4.0 4.5 5.03.5

4.0

4.5

Vol

tage

[V

]

Time [ms]

2.0 2.5 3.0 3.5 4.0 4.5 5.03.5

4.0

4.5

VO(t

) [V

]

Time [ms]

Step load response:

4A 8A 4AoI

Step input response:

16 8V 16VSV V