ddr penetrates mobile computing
DESCRIPTION
DDR Penetrates Mobile Computing. Bill Gervasi Technology Analyst Chairman, JEDEC Memory Parametrics Committee. Agenda. Why DDR for Mobile? Standard versus cached DRAMs DDR Configurations Introducing the DDR MicroDIMM Mobile System Design Guidelines. Reasons for DDR in Mobile. - PowerPoint PPT PresentationTRANSCRIPT
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San JoseSan Jose January 23-24, 2001 January 23-24, 2001 TaipeiTaipei February 14-15, 2001 February 14-15, 2001
DDR PenetratesDDR PenetratesMobile ComputingMobile Computing
Bill Gervasi
Technology Analyst
Chairman, JEDEC Memory
Parametrics Committee
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AgendaAgenda
• Why DDR for Mobile?
• Standard versus cached DRAMs
• DDR Configurations
• Introducing the DDR MicroDIMM
• Mobile System Design Guidelines
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Reasons for DDR in MobileReasons for DDR in Mobile
• Performance
• Power
• Form factors
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SDRAM EvolutionSDRAM Evolution
1000MB/s
2700MB/sMainstreamMemories
SDR
DDR333
Simple,incrementalsteps
DDR II4800MB/s
2100MB/s
DDR266
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Power: DDR vs SDRPower: DDR vs SDR
0
0.5
1
1.5
2
2.5
3
3.5
Throughput per Second per Unit Power
PC-100
1X
DDR-266
3.2X
PC-133
0.8X
DDR-333
2.6X est.
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DDR Power ManagementDDR Power Management Relative
PowerCPU ClockLatency**
Active on 100% 0 x 5 = 0
Inactive on 3 x 5 = 15
Active off 1 x 5 = 5
Inactive off 0.2% 4 x 5 = 20
Sleep 0.4% 200 x 5=1000
PowerState*
12%
4%
* Not industry standard terms – simplified for brevity** Assuming memory clock frequency = 1/5 CPU frequency
Op
enP
age
Clo
sed
Pag
e
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Implications: Mobile PowerImplications: Mobile Power
• Encourages closed page policy– Precharge banks as soon as data read– Takes latency hit to reactivate
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Closed Page Power ProfileClosed Page Power Profile
NOP ACT R R PRE NOP
NOP ACT W W PRE NOP
Command Activity
Power Profile
Power Profile
Command ActivityLower Power
Higher Power
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Cached DRAM Power ProfileCached DRAM Power Profile
NOP ACT R-PRE R R NOP
NOP ACT W W PRE NOP
Lower Power
Higher Power
Command Activity
Power Profile
Power Profile
Command Activity
Depending on cached DRAM architecture
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Standard vs CachedStandard vs Cached
• Cached DRAM architectures save power– Improved closed page performance– Latency reduction on page hits– Lower power profile
(See my other presentation at Platform 2001… “An Analysis of Virtual Channel and Enhanced Memories Technologies”)
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DDR ConfigurationsDDR Configurations
TSOP-II
SO-DIMM
DIMM
TQFP
NEW!MicroDIMM
NEW!FBGA
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Next: Small PackagesNext: Small PackagesFBGA (fine pitch BGA)
•Lower inductance•Lower capacitance•Smaller footprint•Tighter layouts enabled
Details:
Package size = 104 mm2 = 54% smaller
Inductance: 1.7nH lower
Inductance variation, pin to pin: 3X less
Capacitance: 0.5pF lower
Performance gain: 300ps of data valid time
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DDR Chip ConfigurationsDDR Chip Configurations• TQFP devices for point to point
– x32 … 64Mb, 128Mb coming– 100 pins, 16 x 22 mm footprint
• TSOP devices– x4, x8, x16 … 64Mb, 128Mb, 256Mb– 66 pins, 12 x 22 mm footprint
• FBGA selection in process– x4, x8, x16 … 128Mb, 256Mb, 512Mb/1Gb coming– 60 ball, 6.4 x 11 mm minimum footprint
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DDR Module ConfigurationsDDR Module Configurations• DDR SO-DIMM – done!
– Sockets, modules in production
• DDR MicroDIMM – in process– Task group active
• System application combinations– One module only– Soldered down + module– Two modules
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Next: DDR MicroDIMMNext: DDR MicroDIMM
• Half the size of the DDR SO-DIMM• Half the capacity if using TSOP
– or –• Same capacity if using FBGA• Target markets:
– PDAs– Internet appliances– Subnotebook computers
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SO- and Micro- DIMMsSO- and Micro- DIMMs
DDR SO-DIMM
TSOP:67.6 x 31.75 mm = 2146 mm2
4 or 8 devices
200 pins on 0.6 mm pin pitch(supports ECC)
---------------------
FBGA:Under consideration if needed
DDR MicroDIMM
TSOP:45.5 x 30 mm = 1365 mm2
4 devices
172 pins on 0.5 mm pin pitch(no ECC)
---------------------
FBGA:45.5 x 25 mm = 1137 mm2
4 or 8 devices
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Module StatusModule Status
• DDR SO-DIMM– DDR266 validated– DDR333 under analysis– Looking okay to 333 MHz with TSOP
• DDR MicroDIMM– TSOP easy, DDR266/333 speeds– FBGA package needed to fit 8 chips– Possible schedule
• Sample April 2001• Approved spec June 2001
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Module DensitiesModule Densities
SO-DIMM MicroDIMM
RawCard
64(Mb)
128(Mb)
256(Mb)
RawCard
64(Mb)
128 (Mb)
256 (Mb)
A: 8 TSOPs(MB) 64 128 256 A: 4 TSOPs
(MB) 32 64 128
B: 8 TSOPs(MB) 64 128 256 B: 4 FBGAs
(MB) 32 64 128
C: 4-5 TSOPs(MB) 32 64 128 C: 8 FBGAs
(MB) 64 128 256
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Small System ConfigurationsSmall System Configurations
• One data bus, one address bus
• Point to point, single socket– Series damped data, address, clock
• Two sockets– SSTL_2 terminated data– Series damped address, clock– Top/bottom or butterfly arrangement
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Top/Bottom Mobile ModulesTop/Bottom Mobile Modules
• Standard for many current full size notebooks• Hard to get at one of the modules• Thickest form factor
CPU
Socket Module
CPUModule SOCKET
Motherboard
Note: There may be patents regarding use of these layouts
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Butterfly Mobile ModulesButterfly Mobile Modules
• Perfect for thin/light notebooks & subnotes• Single access door to both modules• Also good for small form factor desktop PCs
CPU
Module Socket
CPUModule SOCKET
Motherboard
-- or --
Note: There may be patents regarding use of these layouts
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MicroDIMM DesignsMicroDIMM Designs
You know the DDR SO-DIMM, so…
…let’s focus on the MicroDIMM design
First, system configurations…
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Clock TopologyClock Topology
RAM
RAM
RAM
RAM
CK
CK
25
25
Conn
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Data Topology, 1 SlotData Topology, 1 Slot
RAM
RAM
DQ, DQS, DM
25Conn
22
2 bank
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Data Topology, 2 SlotData Topology, 2 SlotRAM
RAM
DQ, DQS, DM
25Conn
22
Conn
RAM
RAM22
25 VTT
2 bank
2 bank
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A/C Topology, 1 SlotA/C Topology, 1 SlotRAM
A, BA, WE,
RAS, CAS
10Conn
RAM
RAM
RAM
RAM
RAM
RAM
RAM
Two Bank
MicroDIMM
shown
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A/C Topology, 1 SlotA/C Topology, 1 Slot
10Conn
RAM RAM RAM RAM
11pF
One Bank
MicroDIMM
shown
A, BA, WE,
RAS, CAS
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A/C Topology, 2 SlotA/C Topology, 2 Slot
10Conn
Conn
RAM RAM RAM RAM
11pF
Two Bank
MicroDIMM
shown
One Bank
MicroDIMM
shown
A, BA, WE,
RAS, CAS
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
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CS & CKE TopologyCS & CKE Topology
CS, CKE
10Conn
RAM RAM RAM RAM
One or Two Bank
MicroDIMM
shown
11pF
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Increasing Focus on SystemsIncreasing Focus on Systems
• JEDEC packaging committee charter extended to include module sockets– Land pattern for pin pads– Mechanical support tab locations– Orientation holes– Shadow area of socket body– Module height & centerline
• Working system configuration first time!
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DDR MicroDIMM ClearancesDDR MicroDIMM Clearances
Standard socket, double sided memory module
Reverse socket, double sided memory module
Reverse socket, single sided memory module
Standard socket, single sided memory module
4.43mm max
0.65mm min
3.78mm max
5.40mm max
3.78mm max
discretes
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Socket Spec StatusSocket Spec Status
• Merging 144, 172 pin sockets into single parameterized MO-214 spec– Priming spring included
• Shoves module “to the left”
– Redimensioned by left edge, not center– Edge bevel defined
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ConclusionsConclusions
• DDR solutions for mobile growing
• Cached DRAM would be even better
• Point to point and DDR SO-DIMM done
• DDR333 development in progress
• FBGA packaged DDR coming
• DDR MicroDIMM development on track
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Memory of choice for the future
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Thank YouThank You