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DEEP-3 • Chris Shallcross Hakim Hazara Quang Ngo Sami Askar Stuart Kingston Trevor Lewis William Murray Decryption and Encryption of MP3

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Chris Shallcross Hakim Hazara Quang Ngo Sami Askar. Stuart Kingston Trevor Lewis William Murray. DEEP-3. Decryption and Encryption of MP3. Project Brief Aims and Goals Partitioning Design Route ASIP Design Route. Application Choice Project Management Early Feedback What Next - PowerPoint PPT Presentation

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Page 1: DEEP-3

DEEP-3

• Chris Shallcross

• Hakim Hazara

• Quang Ngo

• Sami Askar

• Stuart Kingston

• Trevor Lewis

• William Murray

Decryption and Encryption of MP3

Page 2: DEEP-3

Structure of Presentation

• Project Brief• Aims and Goals• Partitioning Design

Route• ASIP Design Route

• Application Choice• Project Management• Early Feedback• What Next• Conclusions

Page 3: DEEP-3

Project Brief

• Problem– How easy is it to harness the power of re-

configurable computing?– How easy is it for Software Engineers?

Page 4: DEEP-3

Introduction

• What is re-configurable computing?– “Computing platforms whose architecture can be modified by software to

suit the application in question. Such a system may take the form of a Field Programmable Gate Array (FPGA) combined with external memories and processors.”

• Why is it of such great interest?– Reduced development costs

– Reduced time to market

– Hot upgrades

– Improved performance (sometimes!)

Page 5: DEEP-3

Current Trends in Reconfigurable Computing

• Greater number of gates / higher clock frequencies increased performance

• Greater volumes reduced costs

• C-like hardware description languages development accessible to software engineers more effort can be allocated to other parts of the project

Page 6: DEEP-3

Project Aims

• To investigate hardware/software co-design methods– By considering two design routes using a non-trivial

application as a test-bench– By measuring amount of effort required for each design

route– Using direct and indirect measures e.g.

• Lines of code, number of gates used and execution time• Perceived complexity

– Comparing the performance of the prototypes with the software only version

Page 7: DEEP-3

Project Goals

• To produce and demonstrate two working prototypes

• To benchmark the prototypes against the software only solution

Page 8: DEEP-3

Hardware / Software Partitioning

Program

Start EndC Source Code Profile

Simulation

HandPartitioning

HardwareFunctions

SoftwareFunctions

Tuned Hardware/ Software

MixtureCO

MS

Page 9: DEEP-3

Partitioning Methodology (1)

• C Source developed using Rapid Application Development, then evolved to fixed point implementation– Common to both routes

• Profiling– Find “Hot spot” regions within the C source

Page 10: DEEP-3

Partitioning Methodology (2)

• Partitioning– Done manually as automated solutions are not very

good

– Apply partitioning rules

• C Handel C• Design inter/intra process communication, control

and synchronisation • Co-Simulation

– For Verification and Validation

Page 11: DEEP-3

Partitioning Design Route

• Advantages– Conceptually simpler to understand

– De Facto Standard therefore more applied examples

– Method can be used to produce low power, low cost or high performance

• Disadvantages– Done manually

– Repeated for every application

Page 12: DEEP-3

ASIP Design(1)

•C Source same as Partitioning method

•Profiling same as Partitioning method

–Also perform static analysis to discover instruction mix and number of registers required

Page 13: DEEP-3

ASIP Design (2)

• Instruction Set Architecture developed using coarse grain customisation

• GCC used as re-targetable compiler

• Simulate to validate making necessary changes

Page 14: DEEP-3

ASIP Methodology

• RISC (Load Store) Architecture– Based on MIPS– Efficient pipelining – Higher degree of parallelism – Performance advantage

• Harvard Architecture– Difficult so use Von Neumann in early stages

• VLIW– Improves performance– Perceived further work

Page 15: DEEP-3

ASIP Design Route

• Advantages– Most of the development effort is writing C– More efficient use of function units than GP– Shorter time to market than more customised

hardware design– Reusability

• Disadvantages– Extra complexity with compiler alterations

Page 16: DEEP-3

System Overview

Local Storage Distributor

MP3 Encoding

MP3 Decoding

EncryptedMP3

DecryptedMP3

Sound Sample

Decrypted DecompressedSound Sample

Output Source

Input Source

• Perceived as a non-trivial application

-Both computationally intensive on their own

-Different instruction mix (MP3 uses reals crypto uses integers)

Page 17: DEEP-3

Requirements

• Functional Requirements– Compress & Encrypt Sound– Decrypt, Decompress & Playback

• Non-Functional Requirements– Security

• Design Objectives– Multiple Input formats– Real Time– User Friendly

Page 18: DEEP-3

MP3

• International Standard– ISO/IEC 11172-3:1993

• Legal Issues– Patented technology– Can be licensed

• Based on Psycho-Acoustics model– How the human mind perceives sound

Page 19: DEEP-3

MP3 Encoding

• Data sent as audio frames• Difficult to generate a good perceptual model

– Very few good quality implementations

Page 20: DEEP-3

MP3 Decoding

• Easier than encoding

• Intended playback through speakers via FPGA

Page 21: DEEP-3

MP3 Codec Selection

• Considered many alternatives– LAME, BlandEnc, Xing, FhG

• Criteria used– VBR, Fixed Point, Open Source, Sound

Quality, Frequency of Public Domain Usage, Independent Tests

• LAME “best”– No Fixed Point

Page 22: DEEP-3

Cryptography

• Requirements– Open Standard, Industry Strength, Integrity

Check, Authentication

• Legal Issues– Patents, Key Strengths

• Algorithms– Public / Private Key, One-Way Hashes, Digital

Signatures

Page 23: DEEP-3

RSA Algorithm

• Security lies in intractability of factoring large integers

• Key distribution problem– Compare Padlock & Key

• Algorithm based on fast modular exponentiation.– Good test of FPGA performance

Page 24: DEEP-3

Conceptual Model

• Login– Related to encryption

Page 25: DEEP-3

Encoding & Encryption

Page 26: DEEP-3

Decryption & Playback

Page 27: DEEP-3

System Architecture

DMA

Host CPU(x86)

RC-1000 Board(FPGA – Memory)

Storage DeviceMemory (RAM)

Sound Card

Speakers Line In

CD-ROM

Microphone

PCI Bus

IDE Bus

Page 28: DEEP-3

FPGA Board Architecture

Page 29: DEEP-3

Time Management

Research

Implementation and test Plan

Implementation

Partitioning Route

ASIP Route

Test and Debug

Simulation

Review and documentation

Sign Off

10 Days

1 Day

30 Days

30 Days

10 Days

10 Days

5 Days

10/12/01 – 23/01/02

24/01/02 – 05/03/02 06/03/02 – 26/03/02 27/03/02 – 31/03/02

Page 30: DEEP-3

Risk Management – Identified Risks

• ASIP Design– No prior experience

– Conceptually More challenging

• Resources– Limited availability of FPGA

• Handel C– No prior experience before project

• Task Complexity

• Time Management– Slow Start

Page 31: DEEP-3

Risk Management – Managing Risks

• Spiral Model– Incremental with regular reviews

• Buddy Buddy System

• Dedicated Handel C “expert”

• Achievable goals

• Plenty of Research

Page 32: DEEP-3

Early Feedback

• Profiling results– Early identification of “hotspot” functions as

psycho acoustic analysis and Huffman coding

• Metrics– One week to grasp partitioning– Ten weeks to grasp ASIP design

• Handel C– Simple programs implemented

Page 33: DEEP-3

What Next?

• First Application Prototype– Software only

• Second Prototype– Fixed Point, software only

• Incrementally More Complex Handel C coding

• Further prototypes with the design processes

Page 34: DEEP-3

Summary

• Presented the project aims and vision• Presented two opposing development

methods• Presented an overview of the application to

be used• Identified risks and how to manage them • Presented initial results• Planned further work

Page 35: DEEP-3

Conclusion

• Project remains on schedule

• Good progress made

• Lots more to do