defect engineering in advanced devices on high-mobility...

Defect Engineering in Advanced Devices on High-Mobility

Substrates

C. Claeys1,2

1IMEC, Leuven, Belgium2E.E. Dept., KU Leuven, Leuven, Belgium

C. Claeys – IEEE DL, New Jersey, May 06 © imec 2006

Outline

IntroductionDefect Studies

Why importantChallenges

ITRS and ScalingProblemsSolutions

Dislocation GenerationHigh Mobility Substrates

Fabrication AspectsDefect IdentificationElectrical Performance (leakage, lifetime,

LF noise)

Conclusions


Introduction

Interest in defects due to their impact on: physical processes (e.g. diffusion)electrical device performance yield

Interest since the early days of semiconductors, but now there is physical insight

No longer trial and error but ENGINEERING

Origin of defects can beGrown-in (dislocations, vacancies, interstitials, swirls,

COPs……)Process-induced (dislocations, precipitates, metals,

twinning,…)

Scaling is putting stringent requirements on the resolution of the analytical techniques


Introduction

• DownscalingChannel doping levels: UTSOI

High-κ dielectrics

FUSI/Metal gates

carrier mobility control


Scaling Aspects: Mobility Control

Use of high-k dielectricsReduction of the low-field mobility due to remote phonon scattering

Use of metal gates or FUSIIncrease of the low-field mobility

R.Chau et al., IEEE Electron Device Lett., 25, (2004) 408


Scaling Aspects: Mobility Boosting

Use of high-k dielectrics + metal gate + strained Si

S. Datta et al, IEDM 2003, p. 653

35% increase for strained Si/SiGe

n-MOS


Strain Engineering

• Mobility improvement: Strain engineering

Strained Si on SiGe virtual substrates

Strain engineering: global or local

Ge or GeOI substrates


Strain Engineering Approaches

Channel Strain

Global Strain Local Strain

SiGe SRB sSOI

sGOI

SilicidesMetal Gate Stress

Liner

S/DRecessedThin Thick SRB sSDOI

STI

Uniaxial or Biaxial

CESL


Goal

LOW FIELD MOBILITY CONTROL ESSENTIAL FOR HIGH PERFORMANCE DEVICES

⇒ SUBSTRATE ENGINEERING: SOI, SiGe, Ge, GeOI, …..

⇒ STRAIN ENGINEERING65 nm CMOS platform available.

DEFECT ENGINEERING IN THESE MATERIALS


Stress & Dislocation Nucleation

Stress leads to the nucleation of dislocations when higher than the yield stress of the material

stress relaxation of precipitatesisolation induced stressinterfacial stress due to lattice mismatch


Stress and Defects

Electrical activity of the dislocations? Role of metallic impurities

• Stress can beneficially be used for getteringe.g. Fe getting by SiO2 precipitates

enhanced Cu precipitation due to strain relaxation

• Isolation-induced stress dislocations are the source of pipeline defects leading to an increase of the off-state leakage current


Stress-induced dislocations

J.W. Sleigh, C. Lin and G.J. Grula, IEEE Electron Device Lett., 20, (1999) 248


Strained Si

Device architecture:

Strained Si channel

Poly

Salicide

Source DrainRelaxed Si1-xGex

buffer layer

Strained Si

Relaxed SiGe


Strain S/D versus Channel


Strain and Spacer Overlap

P.R. Chidambaram et al., Digest 2004 Symp. on VLSI Technology, (2004) 48


Dislocation Nucleation

Misfit Dislocations (MDs) and Threading dislocations (TDs) may be generated in hetero-epitaxial systems.

Lattice mismatch: elastical relaxation by increasing the strainplastically by dislocation generation

Critical film thickness (Van der Merwe, JAP, 34, 117, 1963)

ν dislocation velocityf0 spacing mismatch Δa/aa =lattice spacing

Strain relaxed buffer layers:gradual Ge increase : thick layer composition (2-4 mm)thin layer approach (250-350 nm)

Strain relaxation can be facilitated by a C-rich layer

]102

1[ln0

2)1(4)21( +−

−−= ff

act π

ννπν


Strained Si on SRB Layers

Strained Si on SRBDislocation densityGraded channel approach (1-2 μm layers)Heat control in thick layers

IMEC approachThin (250-350 nm) approach with C-dopedlayer for strain relaxation

Can also be used in a SEG scheme(e.g. SEG for n-MOS & SiGe S/D for p-MOS)


Strain Relaxed Buffer Layers

Standard buffers

Thin SRB’s


Epilayer Structure

Misfit dislocations

Threading dislocations<= 3x106 cm-2

x x x x x x x x x x x x x x x x x x x

C layer: defect-rich

140 nm SiGe (22%)5 nm SiGe:C (22%)

70 nm SiGe (22%)

SiGe (20%), variable thickness

8 nm Strained Si

Total layer thickness: 250-350 nmAfter defect etching: Etch Pit Density <=3 106 cm-2


TEM Analysis


p+/n and n+/p Diode Structure

implanted n-well or p-wellDopant activation: by spike annealing (950-1050°C) Ni silicidation

Junction depth of ~50 nm


Chemical Defect Etching

Individual threading dislocations

Dislocation pile-upsMisfit DislocationsAt the Si/SRB interface


EMMI Analysis n+p junction

Si reference: Breakdown edges Thin SRB: MD bottom interface

Thick SRB: Uniform distributed spots

No electrical activity of threadingdislocations revealed


EMMI Analysis p+n junction

Si reference: Breakdown edges

Electrical activity of threadingdislocations and dislocation pile-ups revealed.

Thin SRB: distributed spots

Thick SRB: Distributed spots of TDs


Electrical Activity Defects - EBIC

W. Seifert, M. Kittler, J. Vanhellemont, E. Simoen and C. Claeys, Inst. Phys. Conf. Ser.,149, 319, 1996)


EBIC Strained Si/ Si0.8Ge0.2

H.C. Huang et al., Appl. Phys. Lett., 84, 3316, 2004

4 keV and 0.3 nA

a) 300 K and b) 65 K.

20 keV and 1 nA

a) 300 K and b) 65 K.


Diode Current Behavior

10-10

10-8

10-6

10-4

10-2

100

-1 0 1 2

Si refSSi, thinSSi, thick

I (A

/cm

2 )

V (V)

p+/n junctions

10-10

10-8

10-6

10-4

10-2

100

-2 -1 0 1

Si refSSi, thinSSi, thick

I (A

/cm

2 )

V (V)

n+/p junctions

G. Eneman et al., Proc. First CADRES Workshop, Catania 2004, J. Phys. C: Solid State Physics, vol 17, pp. S2192-2210 (2005).


Bulk Leakage Current Density versus TD Density

10 -6

10 -5

10 -4

10 -3

10 -2

105 10 6 107 108 109

VR=-1V

Rev

erse

Cur

rent

Den

sity

(A/c

m 2 )

Threading Dislocation Density (cm -2)

p+/n junctions

n+/p junctions

n+p: 10 pA/TD at Vr=-1 V and 25ºC

Different behavior p+n

Different electrical activity?

Dc at 270 nm


Activation Energy

Arrhenius plot of n+-p diode current density for thin and thick SRB’s, measured at a reverse voltage of 0.1V. Activation anneal was 1000°C.

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

20 30 40

SSi, thinSSi. thick

J (A

/cm

2 )

1/kT (eV-1)

~ exp(-0.590x)

~ exp(-0.996x)

V=0.1V reverseSSi-Thick (350 nm)

Bandgap Eact: diffusion

SSi-Thin (250 nm)Near midgap Eact : defects


Generation Lifetime versus TD Density

105

106

107

108

109

1010

1011

105 107 109

Experimental τ-1

Linear Fit

τ-1 (s

-1)

Threading Dislocation Density (cm-2)

TDDtnNn

gνστ =1

For nD ∼106 cm-1

σn: 9.6 10-13 cm2


Generation Lifetime

Effective generation lifetime at 0 V versus spike anneal temperature for p+-n junctions in a thick (350 nm) and a thin (250 nm) SRB

10-10

10-9

10-8

10-7

10-6

10-5

940 960 980 1000 1020 1040 1060

Eff

ectiv

e G

ener

atio

n L

ifetim

e (s

)

Spike Anneal Temperature ( oC)

thin SRB

thick SRB

Si references

p+/n junctions at 0 V


Discussion

Higher thermal budget: Reduce leakage currentDopant diffusion: lower EAnneal defects

SiGe with TDsTemperature increase: Wider WMore TDs in depletion region

TDDreverse NnWJ ⋅⋅~

W: depletion widthnD: number of traps per length dislocationNTD: threading dislocation density


Location C-rich Layer & Defect Density

Impact of the position of the C-rich layer and the defect density on the reverse current density of n+-p diodes

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

0 1 2

C at 100nmC at 200nmC at 270nmSi ref

J R (A

/cm

2 )

VR (V)

n+/p junctions

(a)10-9

10-7

10-5

10-3

10-1

101

0 1 2

~109 defects

~107 defects

~105 defectsSi ref

J R (A

/cm

2 )

VR (V)

n+/p junctions

(b)


Impact Type of Defect

• TDs increase the trap-assisted tunneling at RT, while above 100ºC the diffusion current dominates over the TD generation current.

• The C-rich layer defects introduce relaxation of the SiGe substrate. Moving the layer closer to the junction increase the generation current.

• Residual implantation damage makes the junction leakage current sensitive to the anneal temperature. For junction inside the SiGelayer this component is negligible compared to the leakage caused by other defects.


Low Frequency Noise

E. Simoen et al., ULSI Process integration IV, Quebec, May 2005

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-7 10-6 10-5 10-4

10 μmx5 μm n-MOSFET

Nor

mal

ised

noi

se s

pect

ral d

ensi

ty (1

/Hz)

Drain Current (A)

VDS

=0.1 Vthin SRB

no TD

TD

10-13

10-12

10-11

10-10

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

10 μmx1 μm n-MOSFETs

Inpu

t-ref

erre

d N

oise

Spe

ctra

l Den

sity

(V2 /H

z)

Gate Voltage Overdrive (V)

VDS

=0.1 Vf=10 Hz

SRB wafer

Si reference


Stress and Oxide Defects

A. Stesmans et al., APL 82 (2003) 3038


Process Induced Stressors

Tensile or compressive Geometry/design of devices has an impactStress parallel or perpendicular to the current flowUniaxial or biaxialVariety of stressors

SiGe recessed source/drainHybrid orientation techniques (HOT)Stress memorization effects (e.g. disposable stress liners)Contact etch stop layer (CESL)…………


Processing-Induced Stressors

A. Collaert et al., IEEE TED, 20 (2005) 820

10-11

10-9

10-7

10-5

0.001

200 250 300 350 400 450 500

referencetensilecompressive

I off [A

/μm

] @ V

gs=0

.2 V

Ion

[μA/μm] @ Vgs

=-0.8 V

Vds

=-1 V

10%

(b)

Ion –Ioff behavior of (a) nMOS devices and (b) pMOS devices; W = 35 nm; the strained layers obtained by SiN CESL have an intrinsic stress of 800 Mpa

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

200 300 400 500 600 700

referencetensilecompressive

I off [A

/μm

] @ V

gs=-

0.3

V

Ion

[μA/μm] @ Vgs

=0.7 V

Vds

=1 V

20%-30%

(a)


LF Noise and Stressors

10-1 10010-10

10-9

10-8

|VGS-VT| (V)

A S ID

/ I2 D

((µm

)2 /Hz)

Reference #1Reference #2SiGe #1SiGe #2Cap #1Cap #2SiGe+Cap #1SiGe+Cap #2

f = 10 Hz W = 10 µmL = 1 µm

G. Giusi, E. Simoen, G. Eneman, P. Verheyen, F. Crupi, K. De Meyer, C. Claeys and C. Ciofi, accepted for EDL, 2006 (in press)


Strain Engineering

Critical factors [Ge] and the layer thickness Ge can outdiffuse during processingThermal stability of the stress?Different behavior n- and p-channelsMobility enhancement is f(channel doping)Narrow width effects on strain behaviorDefect generationImpact strain on noise performance…………STRAIN ENGINEERING HAS SUCCESSFULLY

BEEN DEMONSTRATED BUT REMAINS COMPLEX


1947: 1st transistor:

J. Bardeen, W. Brattain,W. Shockley

Ge Device


Defects in Ge

Vanhellemont et al., in Defects and Diffusion in Semiconductors – An Annual Retrospective VII, Trans. Tech. Publ. Inc., 230, 149 (2004)

Defect in as-grown Ge (row of dislocations)

* High-res. Ge, H-atm.crystal growth

* 30°, 60° and 90° disl.* Disl. sink for [V]

No V2-H complexesTilted 35° away [001] pulling axis


Defects in GeOI

K.K. Bourdelle, APL, 86 (2005) 181910

{311} defect


Control n-type dopants in Ge

0100200300400500600700800

1E+13 1E+14 1E+15 1E+16Dose (at/cm2)

Rs

(Ohm

/sq)

P, 500C-60sP, 500C-1sP, 600C-1s

Above SS implant

15 keV P in Ge; no SiO2 cap

15 keV 5x1015 cm-2 P, 60 s at 50°C


Noise in GeOI Transistors

Ge devices have a higher noise than their silicon counterparts, due to the quality of the interfacial layer.


GaAs on Si

TEM image of a GaAs on Si structure with a graded SiGe buffer to reduce the threading dislocations and a top Si cap

Fitzgerald et al., IEDM Techn. Digest, (2005) 519


Conclusions

Defect analysis requires a combination of state of the art characterization tools for defect detection and identification

Strain engineering is a viable approach for sub 45 nm technology nodes

Alternative substrates are strongly gaining interest and will know a real breakthrough

Local strain engineering has a strong potential

Defect engineering remains of crucial importance

New physical models will be needed (e.g. LF noise)


Acknowledgement

The author wants to acknowledge the discussions with and the use of co-authored

results of the members of the IMEC high-mobility and Ge teams. Special thanks to

M. Bargallo, F. Crupi, M. Caymax, E. Delhougne, G. Giusi, R. Loo, R. Rooyackers,

A. Satta, P. Srinivasan, J. Vanhellemont and P. Verheyen.

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