UNCLASSIFIED

AD. 667 655

SYSTEM /360 INTERFACE ENGINEERING REPORT

David Mills

Michigf.n University Ann Arbor, Michigan

November 1967

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THE UNIVERSITY OF MICHIGAN

Memorandum i

CONCOMP March 1968

SYSTEM/360 INTERFACE ENGINEERING REPORT

David Mills

ior pvblU; r^::^:: tr:-; sale; ita distdb^tica is luül^tsi

Reproducetj by tH>- CLEARINGHOUSE

for Federal Scte^'iftc S Tochn-ca' Infarmolion Springfield Va. 22151

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THE UNIVERSITY OF MICHIGAN

Memorandum 13

SYSTEM/360 INTERFACE ENGINEEFING REPORT

David Mills

CONCOMP: Research in Conversational Use of Computers ORA Project 07449

F.H. Westervelt, Director

supported by:

DEPARTMENT OF DEFENSE ADVANCED RESEARCH PROJECTS AGENCY

WASHINGTON. D.C.

CONTRACT NO. DA-49-083 OSA-3050 ARPA ORDER NO. 716

administered through:

OFFICE OF RESEARCH ADMINISTRATION ANN ARBOR

November 1967

PREFACE

The System/360 interface provides a connection be-

tween the PDP-8 and the multiplexor channel of Systera/360 models

30, 40, and 50, as well as the 2870 Multiplexor Channel attached

lo other models. Eithei byte-interleaved or burst-mode opera-

tion can be sustained at transmission rates up to 70 kj.lobytes-

per-second. Interface control operations are supervised via

the PDP-8 accumulator and interrupt facilities, while data

transfer operations ai^ directed via the three-cycle data break

facility. The interface is attached directly to the channel-

control unit interface cables which interconnect the IBM equip-

ment and occupies one control unit position on the channel.

The equipment satisfies all original equipment manufacturer's

^OtM) specifications as described in the following IBM publica-

tions :

1 . System/360 I/O Interface: Channel to Control Unit original E q u i p n e n t Manufacturer's Informat ion, IBM Corporation, Form A22-6843-3.

2. System/360 Power Cont rol Interface: Original Equip- ment Manufacturer's Informat ion, IBM Corporation, Form A22-6906-0.

The accompanying photographs on the next two pages

show the Data Concentrator, including the System/360 interface

together with its test panel. The interface itself is as-

sembled in the bays immediately above the test panel.

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ACKNOWLEDGMENTS

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In the design of the equipment described herein, Mr.

Dan Pence transcribed the logical functions to r"C Flip-Chip

technology and constructed the working documentation, consist-

ing of logic diagrams and computer-generated punched-card

wiring lists. Working from these wiring lists, the Gardner-

Denver Company of Grand Haven, Michigan, constructed the Flip-

Chip mounting panels using automatic wire-wrap machinery.

Mr. Ken Burkhalter designed the IBM-DEC interface circuit boards

and power control equipment described in Appendix D. The Test

Panel, described in Appendix F, was constructed using

photographic technicues by the Prin-Tek Company of Detroit,

Michigan. All the special printed-cireuit components were

supplied by th. Photo Tek Company of Ann Arbor. Mr. David

Flower and Mr. Warren Kennison assembled the equipment in a

most craftsmanlike fashion.

The IBM company provided documentation which was in-

valuable in the design of this equipment. In particular,

Mr. Les Bailey and Mr. Dan Murphy, both of IBM, have contributed

much useful advice.

vi i

TABLE OF CONTENTS

Page

PREFACE

ACKNOWLEDGMENTS.

LIST OF FIGURES,

I

I I

INTRODUCTION.

CHANNEL INTERFACE LINES

BUS OUT , BUS IN , . . . Outbound Tags 1 n b o u rul Tags Selection Controls Metering Controls.

Ill CONTROL SEQUENCES

3. 1 3.2 3.3 3.4 3.5

Initial Selection Sequence... Service Cycle Special Sequences Polling Operations Equipment Failure Diagnostics

IV PROGRAMMING CONS IÜERATJGNS FOR IBM SYSTEM/360 INTERFACE ,

a.l Command Interface Operations 4.2 Service Interface Operations 4.3 System/360 Control Program Operations

Start 1/0 Halt I/O . Test i/O Programming Notes

V ARCHITECTURE OF SYSTEM/360 INTERFACE

APPENDIX A.

APPENDIX B-

APPENDIX C...........

ANALYSIS OF SELECT LATCH CIRCUITRY..

APPENDIX D

ADDITIONAL CONSTRUCTION DETAILS... .

Dl System Configuration D2 Power Control Uni t D3 IBM/DEC Interface Modules

i x

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xi i i

1

2

2 2

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12 14 18

22 26 36

3 7 3 7 38 39

3 9

62

7 3

83

85

88

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90 9 2 9 4

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TABLE OF CONTENTS (cont'd)

Paj;_e

APPENDIX E 99

APPENDIXE 145

FI The Test Panel 147 F2 Diagnostic Procedures , ... 149

xi

LIST OF FIGURES

Figure Page

i

i i

1

2

3

4

5

6

7

8a

8b

9

iOa

10b

11

12

13

14

15

16

17

18

19

20

21

22

Al

A2

A3

A4

The Data Concentrator , iv

The Test Panel of the Interface v

Channel-Control Unit Interface Lines.... 3

Initial Selection 7

Service Cycle (Burst Mode) 10

Interface Disconnect 13

Control Unit Busy 16

Register Bit Assignments 21

Initial Select ion-HIO 23

Service Cycle—Stop 27

Service Cycle-End 28

Principal Interface Components. 40

ARI, BR1, AR2 Registers 43

BR2 and CTL Registers. . . 44

PDP-8 Data Paths 45

Bus Gating 46

Select Interception 48

Channel Seizure 49

Command Storage/Proceed 51

Status 52

Parity Check , 53

BR2 Gating 55

Command End, . , 56

Service End 58

Cycle Reset 59

Control Operation Decoder and Channel Request Flip-Flop.. 60

Channel Seizure 64

Command Byte Storage 65

Command Status Presentation...... 6 6

Special Status Presentation 67

xii i

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Figure

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LIST OF FIGURES (cont'd)

Page

Service Cycle 68

Service Cycle End 69

PDP-8 Data Break Cycle.. 70

Initial eljcticr. 73

Service Cyc'e 73

Control Unit Busy 75

Interface Disconnect 75

Channel Seizure , 77

C^te Transfer 77

Major State-Service Cycle 79

Data-Break Service Cycle 79

Test I/O Loop 81

SEL OUT/SEL IN ud.nys . 81

Select Latch 86

Select Latch State Table 87

P!.ysical Configuration 91

Power Control Unit 93

DEC to IBM Bus Driver Module 95

IBM to DEC Bus Receiver Module .,... 97

SEL OUT Bypass Module t . . 98

AR1 101

BR1, . . . . 102

AR1/BR1 Pulsing. - 103

AR2 104

BR2 105

AR2/BR2 Pulsing , 106

BR2 Gating 10 7

Control Register. 108

Clearing the Control Register 109

Control Operation Decoder.. 110

I0T Detection Ill

xv

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LIST OF FIGURES (cont'd)

Figurt

E12

E13

E14

E15

E16

E17

E18

F.19

E20

E21

E22

E23

E24

E25

E26

E27

E28

E29

E30

E31

E32

E33

E34

E34

E34

E35

E35

E36

£36

E36

Page

Transfer Direction ,, 112

Address Register Compare. 113

Address Detect 114

Channel Request 115

Select Interception 116

Channel Seizure 117

Command Storage 118

119

120

121

122

123

Status ,,

Command Cycle End .

Data Break ............

Data Break...

Service Cycle Reset

Command Cycle Reset. System Reset........ 124

BUS OUT Parity 125

BUS IN Parity..., , 126

BUS OUT Parity Check. BUS IN Parity Check, .,.,.. 127

BUS-TAGS OUT Gating 128

Select Out Gating. 129

BUS-TAGS in Gating. , . 130

On-Line/Off-Line Circuitry 131

Test Panel Push Button Gating.,.-...,.... 152

Connectors Positions. .... i33

PDP-8 Cable Connecters (Page 1 of 3) 134

PDP-8 Cable Connectors (Page 2 of 3) 135

PDP-8 Cable Connectors (Page 3 of 3) 136

IBM Cable Connectors (Page 1 of .' .

IBM Cable Connectors (Page 2 of 2J.

137

138

Test Panel Connecters (Page i of 5), 139

Test Panel Connectors (Page 2 of 3' 140

Test Panel Connectors (Page 3 of 3}....., 141

xvii

LIST OF FIGURES (cont'd)

Figure

Fl est Panel Layout

Page

148

xix

- i

SYSTEM/360 INTERFACE ENGINEERING REPORT

I, INTRODUCTION

The Systeiii/36ü interface apnears to the resident

System/360 control program as similar to the 2702 Transmission

Control. This approach is felt more fruitful in the face of

heavy commitments to i-ftware support provided by the manufac-

turer. Its pertinent features are as follows:

a. The interface recognizes a class of device ad-

dresses that are assigned according to the conventions estab-

lished by IBM.

b. Recognition of command codes and generation of

status responses are in most cases under the control of the

resident PDP-o control program.

c. Several buffer registers isolate the two machines

so that the exchange of control and data information does not

affect the timing of other control units that may be attached

to the channe 1.

d. Data transmission between the two machines pro-

ceeds in a byte-interleaved or burst-mode fashion at an ag-

gregate data rate which may be programmed by the PDP-8 and

indirectly by the System/560.

The System/360 interface consists of two principal

components: th^ command interface, which services initial

commands issued by t! - System/360 control program through

the multiplexor channel, and the service interface, which trans

raits data and status information between the two machines.

Both of these interfaces operate independently and in an over-

lapped fashion except at the channel interface circuitry it-

self, which is necessarily sequential in operation. At the

channel interface the entire PDP-8 system appears to the

System/360 as a control unit and accesses ti^e interface trans-

mission lines in the fashion prescribed for these devices.

-1-

II CHANNEL INTERFACE LINES

The System/360 interface is con.iectei to the multi-

plexor channel via a set of 34 lines which are common to all

other control units serviced by the channel. All of these

lines except one are simply looped through the interface and

attached to the various bus drivers or receivers as required.

Thus in off-line or povver-down situations it is not necessary

to physically reroute or switch these lines, but merely to

gate off the bus drivers and receivers. The one exception

(the SEL OUT line) is physically broken at the interface. The

interface-inbound SEL OUT line is routed to a terminator

and bus receiver, while the interface-outbound SEL OUT line

is routed from a bus driver. During normal equipment opera-

tion, signals received on the inbound SEL OUT line are processed

internally and then propagated to the next control unit via the

outbound SEL OUT line. During off-line or power-down conditions

the terminator, bus receiver, ^nd driver are bypassed with a

relay.

The interface lines and their nomenclature used

throughout this document are summarized in Figure 1. Following

is a brief description of the function of each of these lines.

For greater detail, the reader is referred to the pertinent

IBM publications.

1 I I I i i

BUS OUT. A set of nine lines, including a parity line,

which propagates outbound information a byte at a time from

the channe.1 to all control units serviced by the channel.

The information is conditioned by the outbound tag lines

(ADR OUT, CMD OUT, SRV OUT) actuated by the channel and

may represent a device address, a control unit command,

or an outbound data byte.

BUS IN. A set of nine lines, including a parity line,

which propagates inbound information a byte at a time from

a selected contiol unit to the channel. The information

-2-

BUS OUT

-/qV- -♦ ~-\VJ CHANNEL BUS IN

ADR OUT

CMD OUT SRV OUT

ADR IN

STA IN SRV IN

SEL OUT SEL IN OPL OUT OPL IN *

HLD OUT SUP OUT ""

REQ IN

MTR OUT* -»

— MIR IN* CLK OUT*

CONTROL UNIT

OUTBOUND TAGS

INBOUND TAGS

SELECTION

CONTROLS

METERING

CONTROLS

*NOT USED

FIUGRE 1. CHANNEL-CONTROL UNIT INTERFACE LINES

-4-

is conditioned by the inbound tag lines (ADR IN, STA IN,

SRV IN) actuated by the control unit and may represent a

device address, a status byte, or an inbound ds.ta byte.

Outbound Tags. Three lines: ADR OUT, CMD OUT, and

SRV OUT used to condition information on BUS OUT. If ADR

OUT is up, the channel is attempting to gain initial selec-

tion of a control unit in order to transmit a command byte.

When selection is achieved, CMD OUT indicates that a com-

mand byte is available on BUS OUT for interpretation by

the control unit SRV OUT is used as an interlock during

data and status transmission cycles These tags are also

used in combination during certain control sequences not

involving the use of BUS OUT.

Inbound Tags. Three lines: ADR IN, STA IN, and

SRV IN used to condition information on BUS IN. If ADR IN

is raised by the control unit, the information provided on

BUS IN identifies the particular device requesting channel

service. If STA IN is raised by the control unit, the in-

formation on BUS IN is the status byte pertaining to the

device, and if SRV IN is raised, the control unit is re-

questing channel service for a data byte. U

Select ion Controls. Seven lines controlling the

seizure and sequencing of transmission operations between

the channel and the control unit. SEL OUT and SEL IN form

a loop from the channel outbound through all control units

in turn and finally inbound to the channel. A signal

propagated on this line is intercepted by a control unit

depending upon its position along this loop, which in effect

establishes its priority for channel service. OPL OUT and

GPL IN are conditioned by the channel and the control unit

respectively and indicate the availability and connection

-5-

status of each of these devices. In particular, a control

unit raises OPL IN when it has achieved selection on the

interface, and is held up for the duration of the partic-

ular channel-control unit sequence involved. HLD OUT is

used in conjunction with SEL OUT to minimize propagation

delays through the select circuitry of the control units.

SUP OUT is raised by the channel to inhibit control unit

seizure of the interface under certain conditions. REQ IN

is raised by each control unit requesting channel service

and conditions the channel to poll the interface for

seizure. Certain combinations of these selection control

lines are used to indicate special conditions such as

system and selective reset, and in conjunction with the

outbound tag lines to indicate special conditions such

as interface disconnect.

Metering Controls. Three lines used to condition

usage meters on the various devices of a System/360 complex.

The equipment described herein makes no use of these lines.

III. CONTROL SEQUENCES

A number of control sequences are possible between

the channel ani the interface and, of these, most have several

variations. All sequences can be grouped in one of three

classes, however:

1. those involving initial-command selection,

2. those .involving data transmission, and

3. those involving presentation of ending status.

For any one device, these sequences proceed in the order nimed;

that is, the device is selected and logically connected to the

channel, then transmits its data, and finally transmits status

regarding the condition of the I/O device at the conclusion of

-6-

the operation. However, certain conditions can occur which are

asynchronous to the progression of an operation through the

states corresponding to the three principal sequences. Such

coiiditions include those that halt data transmission and those

that test device status during the course of an operation.

Some of these can be produced by the channel without interven-

tion by the program. The operation of the interface using

typical sequences is summarized below. Additional details of

operation in exceptional cases are discussed in the pertinent

IBM publications

3. 1 Initial Selection Sequence

Figure 2* shows the sequence of interface tag line

signals during an initial selection procedure. This sequence

is used for all channel commands and, in addition, for the Test

I/O (TIO) sequence. The sequence begins when ADR OUT is raised

by the channel while a device address is on BUS OUT. If the

address has odd parity and lies within the block recognized by

a control unit, that control unit prepares to seize the channel

when SEL OUT rises on the interface. When this occurs, the

control unit

a inhibits propagation of SEL OUT to the next lower-

priority control unit on the interface,

b. raises OPL IN to indicate to the channel that the

control unit has in fact seized the interface, and

c. internally stores the device address presented on

BUS OUT.

The channel then acknowledges OPL IN by dropping ADR OUT. The

control unit then places the just-stored device address on BUS

IN with odd parity and raises AÜR IN This returned address

is checked by the channel for correct parity and for match

Wave forms shown in bottom of figures correspond to inter- face circuitry signals described in Section V. Timing in- formation is given in the form of channel sequence photo- graphs in Appendix B.

7-

OUR ADR

CU SEL

CMD CYC

CMD DLY

CHL SRV

CMD END

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FIGURE 2. INITIAL SELECTION

-8

against the address first transmitted on BUS OUT. If these

tests fail, the channel performs a malfunction reset, which

affects all I/O devices attached to the channel. Depending

upon the particular machine model, this operation may result

in a processor check or in a bit set in the Channel Status

Word (CSW) stored as the result of the channel operation.

Following reception of a correct address on BUS IN,

the channel next places the command byte (all zero bits for

a TIO, nonzero for a valid channel command) on BUS OUT, and

raises CMD OUT. The control unit stores the channel command

internally and checks the byie for odd parity. Following this

operation, the control unit drops ADR IN, which the channel

acknowledges by dropping CMD OUT, an invitation for th*. control

unit to present a status byte.

In most IBM control units, the allowable channel

commands are well prescribed and represent only a few of the

possible 255 codes Accordingly, it is possible to detect

immediately upon storage of the channel command byte whether

the control unit can accept the particular command or not.

Thus the control unit has the option of either accepting the

command by presenting the channel with an all-zero status byte

or rejecting the command with a status byte containing the unit

check bit. In the equipment described here, the command may

undergo analysis by the PDP-8 program, a process which may

require a lengthy period compared to the channel selection

sequence. Accordingly any channel command, other than TIO,

is always accept?,!, even if it does not have odd parity. It

is up to the PDP-8 program to interpret the particular command

code and to transmit possible rejection using an ending-status

presentation containing the unit check bit.

Thus, following the acceptance of the channel com-

mand, the control unit places an all-zero status byte on BUS IN

and raises STA IN, to which the channel responds with SRV OUT.

The control unit now drops all inbound tag and bus lines and

disconnects from the interface. If the channel forces burst

mode at this time, SEL OUT will still be up at the control unit,

-9

and a sequence of SRV IN-SRV OUT signals is expected by the

channel to transmit the data associated with the operation.

However, the multiplex channel will force burst mode ouly in

connection with an Initial Program Load (IPL) operation, There-

fore the equipment considered here is not normally expected to

operate under channel-forced burst mode conditions.

3,2 Service Cycle

Figure 3 shows the sequence of interface tag line

signals during a service cycle procedure This sequence is

used for all data and status byte transmission between the

channel and the control unit. In the byte-interleaved mode,

one such sequence is executed for each data byte separately.

In the control-unit-forced burst mode, the initial part of

the service cycle sequence is followed by alternate SRV IN-

SRV OUT pairs.

The service cycle sequence differs from the initial

selection sequence in that the transmission is initiated by

the control unit rather than by the channel, A control unit

requesting service raises the REQ IN tag line when the 3UP

OUT tag line is down at the control unit (Certain sequences

arf expected to override the SUP OUT signal; see below.)

When the channel next polls the control unit interface by

raising SEL OUT, the highest priority control unit requesting

service inhibits the propagation of SEL OUT, places its device

address on BUS IN, and raises OPL IN and ADR IN The channel

checks the device address for odd parity, retrieves the ad-

dressed subchannel status in its active registers, and issuer

CMD OUT.

The control unit recognizes CMD OUT as permission

to proceed with the operation, and it siext drops ADR IN. When

the channel drops CMD OUT the control unit raises either

STA IN and places a status byte o.i BUS IN,

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b. SRV IN a;id places a data byte on BUS IN for trans-

mission to the channel, or

c, raises SRV IN and waits for a SRV OUT channel

acknowledgment that a data byte has been placed on BUS OUT for

transmission to the control unit

If the device address does not nave odd parity,

the channel performs a malfunction reset If a status byte

does not have odd parity, an interface control check condition

is generated- If, in the case of channel-unbound transmission,

a data byte does not have odd parity, a channel data check

condition is generated Depending upon the particular machine

model, these indications appear as a processor or memory check

and as abit set in the CSW stored as the result of the channel

operat ion .

The channel acknowledges the receipt of a data or

status byte, as appropriate, with SRV OUT. This responre is

also used by the control unit to verify the presence of a data

byte on BUS OUT where appropriate. The channel may alterna-

tively respond to SRV IN with CMD OUT, indicating that the

data region in its main storage is exhaustpd, and may respond

to STA IN with CMD OUT, indicating that the status byte is to

be stacked in the control unit for later presentation to the

channel.

In any case, the control unit responds to an out-

bound tag line at the end of the service cycle sequence by

dropping ail inbound tags and disconnecting from the inter-

face. The channel i. now free to continue polling for other

control units on the interface or to issue new commands to

the same or other control units. In particular, under some

conditions, cert :n channel-generated comnands may be directed

to a busy control unit before device-end status has been

serviced bv the channel Tseo below 1,

-12

3 . 3 Special Sequences

Iuring the course or normal equipment operation and

in certain abnormal situations, special control-unir inter-

face sequenc 's mcy be generated by the channel. Tiese fall

into two classes: those intended to stop device activity by

request from the System/360 program, and those generated either by

manual intervention or by the machine itself for the purpose

of temporarily disconnecting the device from the system.

The first class of sequences includss the interface

disconnect sequence generated by the channel in response to a

Halt I/O (HIO) instruction executed by the System/360 program.

Such a sequence can occur at any time, either within an initial

selection or a service cycle sequence. The sequence is

signaled after *'iie device address has been checked by the chan-

nel and when ADk OUT is up at the control unit while SEL OUT

is down. The sequence usually occurs before the command byte

is stored on initial selection, but may occur after CMD OUT

rises during a service cycle.

Figure 4 shows an interface disconnect sequence on

initial selection. Following such a sequence, the control

unit is expected to remove immediately all signals from the

interface and to present ending status following its device

operation. The ending status is to be transmitted only if

tht associated System/560 subchannel was working at the time

of the sequence and may be cleared by a channel-generated TIO

command prior to program intervention.

The second class of sequences includes the selective

and system reset sequences generated by the channel in re-

sponse either to manual intervention or equipment malfunction.

The system reset sequence is indicated when both OPL OUT and

SUP OUT are down at any control unit. This sequence occurs

when power is first applied to the system, or when either the

SYSTEM RESET, LOAD, or PSW RESTART pushbuttons are depressed

on the System/560 operator's control panel. The selective

u

-13-

ADR OUT

SEL OUT

OUR ADR

CU SEL

CMD CYC

CMD HLT

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FIGURE 4. INTERFACE DISCONNECT

14

reset sequence is indicated when OPL OUT is down while SUP OUT

is up at a control unit during an operation involving that

control unit. This sequence occurs when the channel has de-

tected a malfunction of the control uni* or channel circuitry.

Such a malfunction may involve invalid BUS IN parity, improper

signal sequencing, or excessive sequence timings.

In the case of either the system or selective reset

sequences, the control unit is expected to disconnect from the

interface without presenting ending status for the operation.

Since the control unit may be reselected immediately following

a reset sequence, the control unit must appear busy to the

channel while any internal time-dependent reset operations

are completed.

3.4 Polling Operations

Since both the channel, its attached control units,

and their attached devices operate asynchronously with respect

to each other, conventions for device polling and acknowledg-

ment are required. The polling-acknowledgment conventions

appear at three levels: 5 s.

(-1

a. during the initial selection of a control unit,

b, during the channel seizure procedure by a control

unit, and

c. during the selection and deletion procedures of a

device attached to a control unit.

Additional conflicts for both channel and subchannel access

by the System/360 program are resolved by the channel and in

some systems by the channel controller.

The channel selects an attached control unit with

the initial selection sequence. If the control unit is free

to accept a command (without respect to the status of its

attached devices), it responds with the sequence shown in

Figure 1. If not, then the control unit responds with the

control unit busy sequence shown in Figui- 5. This sequence

begins in the same fashion as the initial selection sequence;

tiiat is, the channel places a device adc'ress on BUS OUT and

raises ADR OUT. When SEL OUT rises at the control unit servic-

ing the device, and if the control unit is busy servicing some

other device, the control unit responds by placing a status

byte on BUS IN and raising STA IN. The channel responds with

SRV OUT unconditionally, ollowing which the control unit

disconnects from the interface. Note that this sequence does

not require the control unit to store the device address

presented on BUS OUT or to present stored status for the de-

vice, even if it is available somewhere in the control unit.

The status byte presented to the channel during the

control unit busy sequence may lake two forms. One form in-

cludes both the status modifier and busy bits, which by con-

vention inform the System/360 program that the control unit

is busy and will present a status byte containing the control

unit end bit at some future time. The other form includes

all three of these bits, which by convention inform the System/

360 program that the control unit is temporarily busy and that the

operation which was rejected by the control unit should be

immediately retried. The second form of status byte is used

when the control unit busy condition is expected to last some-

what less than a millisecond, the interrupt processing time of

typical System/360 programs, and the first form iz used in all

other cases .

Wiien the channel is not busy with some internal

operation and is not in the process of issuing an initial selec-

tion sequence directed to some attached control unit, the chan-

nel normally reverts to the polling mode. In this mode the

channel interprets RHQ IN as a request to poll the interface

with StL OUT, an operation that presumably will result in some

control unit raising OPL IN. In some models of the System/360

product line, the polling mode may be entered at interesting

times, for instance while the channel is retrieving the Channel

-16-

ADR OUT

SEL OUT

STA IN

OUR ADR

CU SEL

CU BUSY

~L J L _J"~

FIGURE 5. CONTROL UNIT BUSY

17-

I I

1

Address Word (CAW) or a channel command from main storage.

Since the System/360 CPU is interlocked becween the time that

an I/O instruction is decoded ard the time that the channel or

the addressed device responds, it is important that the control

unit sequence following REQ IN be as short as possible In

extreme cases cf control unit delay during a Start I/O (SIO)

operation (either addressed to the control unit or not), a

processor check may occur when the Svstem/360 CPU microprogram

attempts to update its interval timer

Data byte transmission operations for any particular

device take precedence over all other channel operations, and

are guaranteed to proceed without interference to the subchan-

nels connected to other devices serviced by the channel Status

byte transmission operations, on the other hand, are considerab-

ly more involved and may take one of two alternate forms de-

pending upon whether the subchannel in question is busy or not.

An ending status presentation to a busy jubchannel must

contain the channel end bit, but may contain others as well.

Such a status presentation will always be accepted by the chan-

nel with a SRV OUT response to a STA IN during the service

cycle. Once this status has been stored in local subchannel

storage, the channel requests a System/360 CPU interrupt which

causes a channel status word (CSW) containing the subchannel

status to be stored in main storage An ending status presenta-

tion to a subchannel not in the busy state will be automatical-

ly stacked in the control unit with a CMD OUT response to a

STA IN tag during the service cycle Before slacking the status

at the control unit, however, the channel store? the device ad-

dress of the requesting control unit in a special register

called the Interrupt Buffer (IB) (or Interrupt Queue) At this

time the channel requests a System/360 CPU interrupt, and, when

granted, caui"; a channel-generated pseudo-Test I/O command

to be issued to the device whose address is stored in the IB.

The control unit in question now furnishes this status as the

result of an initial selection sequence rather than the service

18-

cycle sequence o iginally requested. Not a1! IBM control units

can tolerate this interesting procedure; and, in fact, well-

known machine hang-ups revealed in IBM documentation in con-

nection with the 2702 Transmission Control ar? due to the

failure of that device to process the pseudo-Test I/O.

3 . 5 Equipment Failure Diagnostics

Most control unit component malfunctions can he

diagnosed by the channel; and, in many cases, the System/360

control program can recover from the malfunction condition,

record the failure, and continue system operation. In the

case cf the programmable control unit equipment considered

here, certain invalid programming sequences can also produce

such malfunction indications to the channel. Six malfunction

conditions are i;copnized by channel circuitry as probably

originating in an .ached control unit These may or may

not be detected separately or as distinct from a processor

check, depending upon the machine model:

1. Channel timeout. The System/360 CPU had not

been released a pre-set interval (typically 150 microseconds)

following issuance of an I/O instruction,

2. Addrsss-in check. The channel detected a

parity error on the address received from the control unit

during a service cycle,

3 Status-in check. The channel detected a parity

error on the status byte received from the control unit.

4 Incorrect selection The address received from

the control unit during an initial selection sequence does not

match that transmitted by the channel

5. No response The control u ,t did not respond

to re-seiection on a chain-command operat on

6, Incorrect tag sequence. The control unit dis-

connected from the channel before tbe channel dropped the

SEL OUT tag line

-; 1 I

-19-

Any of these malfunctions cause the channel to assume

an interface control check condition, which may be indicated

as a bit set in the CSV! stored as the result of the operation

and further detailed in the log-out area peculiar to the

model. Condition 6 can occur on the multiplex channel only

as the result of an Initial Program Load (IPL) operation and

will always be produced when such an operation is directed to

a control unit such as the 2702 Transmission Control or the

interface equipment described herein

IV- PROGRAMMING CONSIDERATIONS FOR IBM SySTEM/360 INTERFACE

The System/360 interface is composed logically of

two subinterfaces: the command interface and the service in-

terface. The command interface stores the channel command

and device address developed during the multiplex channel

initial selection sequence and presents the appropriate status

byte to the channel to terminate the sequence. At the conclu-

sion of the sequence, appropriate bits are set in a control

register tc indicate the particular type of sequence to the

PDP-8 interrupt processor The service interface supervises

data break operations between the PDP-S and the multiplexor

channel. This interface is started by the PL)P-8 program by

loading a three-bit command code in the control register,

following which three-cycle data breaf. operations occur for

data transmission between a block of PDP-S memory and the

channels Both data and ending-status bytes are transmitted

in this fashion At the conclusion of the operation, either

at channel-stop or word-count-equal -rero tunes, bits are set

in the control register to indicate the termination condition

to the PDP-S interrupt processor

Five registers in the interface are available to

the PDP-8 program Two of these, AR1 and BR1, arc used in

connection with the command interface, while another two, AR2

and BR2, are used in connection with the service interface

-20-

The fifth register, CTL, is common to both interfaces, and

serves as the controlling element for the various operations.

The AR1, BR1, and AR2 registers can be read, cleared, and

loaded (one's-transfer) from the AC of the PDP-8. The BR2

register is connected only to the data break facility. The

CTL register can be read, inverted, and tested bit-by-bit with

appropriate microinstructions(see below) Some of these

registers need not be read or loaded during the common inter-

face operations; the general read/load facility is included

primarily for diagnostic utilities Figure 6 illustrates the

ccdiig of the various register bit assignments and establishes

the I0T microinstruction codes for their access.

The operation of the control register invert-under-

mask (CTL INV) and test-under-mask (CTL TST) microinstruction

is as follows: Both of these instructions address the twelve

control register bits in one-to-one correspondence with the

bits of the AC The operation of the CTL INV microinstruction

results in a bit-wise inversion of each bit in the control

register for which the corresponding bit in the AC is a one.

The operation of the CTL TST microinstruction results in a

single-instruction program skip if each control register bit

which is in correspondence with a one bit in the AC is a one.

If any control register bit in correspondence with a one bit

in the AC is a zero, no program skip is generated An uncon-

ditional skip is generated if the AC contains all zeros.

The RD, CLR, and WR modifiers may be applied to the

registers designated AR1, SRI, aad AR2 The sequence of the

IOP pulses is such that ths micro-operations are performed

in the order listed The RD, TST, and INV modifiers may be

applied to the register designated CTL The micro-operations

are performed in that order. Appendix F illustrates segments

of code that are applicable in common programming situations.

-

"

-21

10 H 2 IU s: z

w 10 < H

CO

D£ W t-< CO M O aj a:

uj

oo I

a a.

o 0

oc i

a a.

o «a

a. a, a.

-22-

4.1 Commaid Interface Operations (Pigure 7)

Three of ;he four System/360 I/O instructions will

result in a channel sequence in the command interface, and

two of these will normally end by interrupting the PDP-8 pro-

gram. An SIO instruction executed by the S/stem/360 will result

in one or more channel commands being fetched from System/360

core storage and transmitted to a control unit. If the device

address specified in the Sr0 instruction lies within the block

recognized by the command interface and if the interface is not

busy (i.e., holding a previously issued command), then the inter-

face will seize the channel and store the device address in AR1

and the coumand byte in BR1, If the channel sequence is gener-

ated as a result of a valid channel command,the command byte

stored in BRl must be nonzero, and will be an odd number if

channel-outbound service is indicated and an even number if

channel-inbound service is indicated.

Note that in order for the selection sequence to be

initiated, the parity of the device address must be odd. If

this parity is odd and yet the parity of the command byte is

not odd,then the CMD PCK bit of the control register ii Svt.

This situation, interpreted as a BUS OUT parity check, does

not affect the progress of the selection sequence or the status

byte subsequently transmitted to the channel.

At the conclusion of the initial selection operation,

the CMD END bit of the control register is set if the chamiel

accepted the interface-generated all-zero status jyte and

the CMD STK bit if the channel rejected the byte. If the

channel sequence is generated as the result of a valid channel

command, an occurrence of the later situation must be inter-

preted an, a System/360 machine check.* Wl.^n cither the CMD^END

or CHD STK bits are set.the FDP-S is interrupted

* Note that in current System/360 j£h~nnel equipment, stack on initial selectirn fCRD STK) neveF occurs on an all-zero status byte. In the case of a nonzero status byte, stack on initial selection will be generated only in certain cases

ff 1 35 1

23-

ADR OUT f"""' 1 CMD OUT J BO^O 1 STA IN J BI-

r O 1

SRV OUT (

CMD END J

INITIAL SELECTION-STATUS ACCEPTED

ADR OUT r

CMD OUT J BO=0 L

STA IN

CMD OUT

J BI=10 L

I CMD STK J

INITIAL SELECTION-TIO STATUS STACKED

ADR OUT p"-——"^]

SEL OUT j

CMD HLT

J L

INITIAL SELECTION-HiO

FIGURE

-24-

A Halt I/O (HIO) instruction executed by the Systein/360

causes a special channel sequence to be transmitted to a control

unit. If the device address specified in the HIO instruction

lies within the block recognised by the command interface and

if the interface is not busy, taen the interface will seize the

channel and store the device address in AR1. BR1 will be

forced to an all-zero byte. This sequence ends by setting the

CMD HLT bit of the control register. A selective reset sequence

generated by the channel during the progress of any command in-

terface operation will also set this bit.** When the CMD HLT

bit is set, the PDP-8 is interrupted.

A Test I/O (TIO) instruction executed by the System/360

causes a special channel sequence which is identical to tne SIO

sequence except that the command byte contains only zero bits.

If the device address specified in the TIO instruction lies

within the block recognized by the interface and if the inter-

face is not busy, then the sequence ends by the transmission to

the channel of a status byte containing only the status-modifier

bit. If the channel accepts this byte, the interface is released

and the PDP-8 is not disturbed. If the channel rejects the

status byte, then the CMD STK bit is set in the control register

and the PDP-8 program is interrupted. It is the responsibility

involving command chaining. Since the command interface generates a nonzero status byte only in response to a Test I/O instruction, and since this "instruction" may not occur as an element of a channel-command sequence, it is rot at all clear from extant documentation whether the CMD STK bit can ever be set in any likely programming situation.

A selective reset sequence is generated by channel equip- ment, at least in some models, in response to a status presentation of bad parity and possibly in response to an invalid tag-line sequence. A presentation of a device ad- dress of bad parity in conjunction with ADR IN will usua1ly result in a channel-generated system reset sequence. A presentation of a data byte "»f bad parity is not always detected by the channel itself, but may be detected by the CPU or memory bus register circuitry and cannot be dif- ferentiated from parity errors due to other causes.

25-

u of the PDP-8 program to retransmit a status byt . containing

the status modifier bit via the service interface when allowed

by the channel (however, see preceding footnote). Note that

this behavior in connection with the TIO instruction is con-

sistent with that of the IBM 2702 Transmission Control and

implies, in particular, that the command interface cannot pro-

vide ftatus in response to a program-generated TIO inrtruction.

Note further that pseudo-TIO instructions can be geneiated by

the channel without intervention by the prrgram, and in these

cases the command and service interfaces mu.-t cooperate in the

successful transmission of a status byte to ehe channel. Such

situations arise in connection with ending-status transmissions

to subchannels not in the busy state (see below).

If a system reset sequence i:; generated by the ch n-

nel, either as the result of power-up, initial program load,

or manual operator intervention, the CMD RST bit of the control

register is turned on. This operation clears all other bits

of the control register and results in a PDP-8 program inter-

rupt. All System/360 registers and subchannels are reset and

placed in the available state. Pending data and status trans-

missions on the part of the PDP-8 should be suspended.

If any System/360 channel operation is directed to

the command interface when either the CMD STK.CMD RST.CMD HLT,

or CMb END control register bits are set, the command inter-

face will immediately reject the operation with the control

unit busy sequence, which involves fie transmission to the

channel of a status byte containing the status modifier, busy,

and control unit end bits. This sequence is by convention

interpreted by both the channel and the System/360 program

as an indication to immediately retry the operation. For this

reason, the resident PDP-8 program should give high priority

to command interface interrupts, since the System/360 program

may be hung up during the response interval. The PDP-8 in-

terrupt processor clears such interrupts by inverting the

-26-

appropriate bit of the control register to a zero. Previous

to this operation, meaningful contents of both the AR1 and

BR1 register must of course be preserved in core storage by

the interrupt processor. It is possible in some System/360

programming systems that tight TIO or HIO loops may be exe-

cuted under certain conditions. In the case of the HIO instruc-

tion, the resultant load on the command interface will most

certainly lock up the PDP-8 interrupt processor, which then

must clear the System/360 condition, presumably by the trans-

mission of ending status to the channel. In any case, the

PDP-8 program must be aware of situations inherent in the

particular parent System/560 supervisory programming system

in which TIO or HIO loops are involved or in which the multi-

plex channel is masked against interrupts, and must give high

priority tc channel service under those conditions."

4.2 Service Interface Operations (Figure 8)

In all service-interface operations, a block of data

is transferred either channel inbound or channel-outbound.

The three-cycle data break facility of the PDP-8 is used for

this block transfer operation, which once initialized by *he

PDP-8 program, continues until the PDP-8 residual word

count decrements to zero, until the channel detects

that a System/360 core memory storage area is exhausted,

or until the System/360 program issues an HIO instruction. All

transmission operations make use f only the low-order eight

A typical instance of a tight TIO loop occurs after present- ation of a unit check to certain present System/360 pro- grairming systems. Programming constraints imposed by other control uniti, in particular the 2841, require that a TIO be directed to the contxol unit immediately following a unit check. In such a case, the selector channel must be disabled before issuance of the TIO. In such cases, the same behavior may exist on the multiplexor channel, a behavior which is strongly disadvised, since not only the command interface but other IBM control units as well will hang up the system for some time.

27.

SERVICE CYCLE (BYTE-INTERLEAVED MODE)

CHL REQ

SERVICE CYCLE-STOP

Figure 8a

28-

w

o CO

cy

OS

C9

Q Z UJ

I

>-

UJ u

UJ to

XI 00

UJ a:

u

LJ

n .1

■ i i

j

If

,.

| t

II

if

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29-

bits of a PDP-8 core memory location The four high-order

bits are ignored in channel - inbound operations, and are re-

placed by zeros in channe1-outbound operations Either data

bytes or status bytes may be transferred using the appropriate

interface order codes (see below). in the case of status byte

transmission, the servce interface will automatically re-

present status to the channe] following a stack-status channel

sequence.

All data and most status operations involving the

service interface take place only when the associated System/

360 subchannel i i busy, that is when a valid channel command

has been stored by the command interface. If the low-order

bit of the channel command is a zero, then channel-inbound

service is requested and the PDP-8 program must select the

interface-outbound data operation. If the low-order bit of

the channel command is a one, then channel-outbound service

is requested and the POP-i- program must select the interface-

inbound data operation Violation of these constraints will

usually result in either a channel check, processor check,

or storage check, depending upon the particular System/360

model.

Status presenli. .,o the channel when the sub-

channel is busy will not usually be stacked by the channel;

and, if a status presentation happens to be stacked, it can

eventually be cleared by re-presentation to the channel. If

the subchannel is available to the System/360 program, then

any status presentation will be automatically stacked and

must be cleared by a channel-generated pseudo-TIO command.

Such considerations dictate a careful organization of the

PDP-8 program to avoid System/360 hangups due to conflicts

at the command and service interfaces

A.'1 service interface operations involve a pro-

grammed procedure which

30-

a. presets the word count and current address loca-

tions accessed by the three-cycle data break facility,

b. loads AR2 with the specified device address,

and finally

c. loads a three-bit order code into the control

register.

The service interface then proceeds with alternate channel

sequences and three-cycle data break operations until either

the PDP-8 word count is decremented to zero, or until a stop

sequence is generated by the channel. The appropriate bits

are then set in the control register and the PDP-8 program

is interrupted. The interrupt is cleared by inverting the

appropriate control register bits to zeros.

In the case of data operations, operation can be

selected in either the byte-interleaved or burst mode. The

byte-interleaved mode is appropriate for either low-speed

operations with all models or both low- and high-speed opera-

tions with the higher-numbered models. Depending upon the

width of the data paths to core ■mamory and the degree of CPU

involvement in the multiplexor channel operations, the burst

mode may be appropriate for high-speed operations with the

lower-numbered models.

A channel-outbound byte-interleaved data operation

is started by loading an octal 2 into the high-order three

bits of the control register. An octal 3 starts the same

operation in burst mode. These orders initiate a data opera-

tion from the channel to the PDP-8 core memory. When the

PDP-8 word count decrements to zero, the SRV END bit is set

in the control register. When a stop sequence is transmitted

by the channel in response to a servi .e request by the inter-

face,the .SRV HIT bit is set in the control register. No

data byte is transmitted to the PDP-S core memory on a SRV

HLT cycle.

LJ

i I

31

This operation is suppressibie That is, if the

channel is undergoing some critical sequence which should not

be interrupted for lower priority operations, the service

interface will suspend data transmission Such is the case

when another control unit on the channel is operating in

burst mode or when certain status operations are pending at

the channel Tf an operation is not outstanding in the

System/360 subchannel addressed by AR2, then, depending upon

the model, the channel wi'^ either respond unconditionally

with a stop sequence or ar interface disconnect sequence,

either of which sets the SRV HLT bit of the control register,

or hang up the channel. If a data byte presented by the

channel does not have odd parity, then the SRV PCK bit is

set in the control register. This condition does not affect

the further progress of the operation and in particular does

not cause a PDP-8 program interrupt

A channel-inbound byte-interleaved data operation

is started by loading an octal 4 into the high-order three

bits of the control register An octal 5 starts the same

operation in burst mode. This order initiates a data opera-

tion from the PDP-8 core memory to the channel. When the

PDP-8 word count decrements to zero, the SRV END bit is set

in the control register. The last byte fetched from FDP-8

memory on the SRV END cycle is transmitted to the channel.

When a stop sequence is transmitted by the channel in response

to a service request by the interface, the SRV HLT bit is

set in the control register The last byte obtained from

PDP-8 memory on a SRV HLT cycle is then lost whether or not

the SRV END bit is set during the same cycle.

The commaics above under channel-outbound data trans-

mission concerning data suppression and operation with an

available subchannel apply also to channel - inbound data trans-

mission Odd parity is automatically generated on all channel-

inbound operations whatever their nature, and the SRV PCK

control-register bit is never affected by such operations.

it'

When either the SRV END or the SRV HLT control reg-

ister bits become set as a result of a service interface

operation, the PDP-8 program is interrupted. The interrupt

processor can determine how many data bytes have been success-

fully transmitted by inspecting the residual word count

stored by the three-cycle data break facility and applying the

modifying factors shown in Table 1. If the SRV HLT bit is

not on at the conclusion of an operation, the opportunity

exists to transmit additional data blocks. If both the

SRV HLT and SRV END bits are set in the control register

following a channel-outbound data operation, an interface

failure is evident.

At the conclusion of the transmission of all data

blocks, and in any case following any operation terminated

by the SRV HLT bit, a status presentation is expected by the

channel. Such a presentation must include the channel end

bit and may include others as well. Following the presenta-

tion of channel end, the subchannel involved reverts to the

interruption-pending state and may allow certain I/O instruc-

tions addressing the subchannel to proceed directly to the

command interface. The subchannel reverts to the available

state upon receipt of an interrupt response from the System/

360 CPU, following which any I/O instruction may be directed

to the command interface. The channel end and device end

bits may be combined in a single status byte.

A standard status operation is ont in which a status

byte containing the channel-end bit is to be transmitted to a

working subchannel. Such an operation is started by loading

an octal 7 into the high-order three bits of the control

register. This order initiates a status operation involving

status byte transmission from the PDP-8 core memory to the

channel. Usually only one byte will be transmitted to the

channel on any one operation; but, regardless of the number

of bytes actually transferred, the operation can legitimately

terminate only when the PDP~8 word count decrements to zero.

-33-

4)

*-> ■H H in C

H

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54-

a condition that sets the SRV END bit in the control register

and interrupts the PDP-8 program. If an interface disconnect

or selective .eset sequence is transmit ed by the channel in

response to a status presentation, then ;he interface will

imm^v'iately disconnect from the channel and cause the

3R HLT bit to be set in the control register.

The standard status operation is not suppressible

by the channe'. That is, status presentations cannot be

locked out of the system if the channel is disabled but

has an interrupt pending for another device. Under

these conditions, a T10 instruction issued by the System/360

program can clear pending status at the service interface.

Such a prof, 'dure is called for following presentation of unit

check in a status by-.c- to certain System/560 programming

systems (see preceding footnote). Such systems regularly

:ollow presentation of unit check by a Sense channel com-nand

while the channel is disabled, and rely on clearing -^vice

status using a TIO loop. Note that in such cases a bu^y

indication is returned to the System/360 program as long

PLS the subchannel is working; and, in particul?r, the TIO

is not propagated to the device itself. Thus, if the

subchannel is working, a standard status operation will

always terminate with the- channel accepting the presentation

by the service interface, and in particular without the

generation of ps^udo-TlO commands on the part of the channel.

If a standard status presentation is once stacked

by the channel for any purpose, then the interface itself

automatically "demotes" the priority to that of a special status

presentation, A special status operation is one in which a

states byte is to be transmitted to a subchannel not in the

working --täte. Thai is, a subchannel in either the available

or interruption-pending tates. Such an operation is started

by loading an octal 6 into the high-ordfr three bits of the

control register. This order initiates a status byte trans-

misjion in the same manner as the standard operation, with

-i

n :

-35-

the exception that the presentation is suppressible by the

channel. Such behavior is necessary to avoid the lockout of

a channel-end status presentation of a lower-priority control

unit on the channel interface cable by an unsolicited status

presentation b> the service interface. As in the standard

operation, the special operation ends by setting the SKV END

bit in the control register.

To summarize the application of the two kinds of

status operations, the standard operation is used to transmit

a status byte, v^hich must contain the channel-v*nd bit, to a

working subchannel; and the special operation is used to trans-

mit a status byte to a non-working subchannel. A failure to

make this distinction will result in a machine hangup in the

lower-numbered models of the System/360 product line and in

an interface control check (channel timeout) in the higher-

numbered models. Such situations may result in a diagnostic

Channel Status Word (CSW) to be stored by the System/360.

If SUP OUT is up when SRV OUT is raised by the channel

in response to an ending status presentation, the CMD CHN bit

cf the control register is set. Such an action is interpreted

as an indication That the channel is command-chaining the

previous operation and is about to reselect the interface for

issuance of a new channel command. The indication of the CMD

CHN bit is only advisory to the PDP-8 program and does not

affect the piogress of any channel or interface sequence. De-

pending upon the circumstances involved, the PDP-8 program

may process this indication as a request to save such status

presentation? as the attention bit until the end of the

System/360 channel program, or to assign high priority to

command interface operations so that the immediately following

rejelection procedure will not delay the channel.

36-

4.3 System/360 Control Program Operations

Interface programming considerations for the System/

360 resident control programs are sunlar to those for the

2702 Transmission Contrt- However, due to the somewhat

richer architecture of the interface, the behavior of the

two machines will be slightly different. The main differences

are:

1. channel-end and device-end status presentation

do not necessarily have to occur in the same byte,

2. burst-mode operation can be sustained,

3. no immediate channel command operations are

possible,

4. unsolicited status presentations are possible.

Considerations 1 and 2 imply that it is possible

to use the interface on a shared subchannel, effecting a cost

reduction in channel equipment on somt models. However, since

it is not possible to determine at initial selection time

whether a particular device attached to the PJP-8 and logical-

ly connected to a particular Syr,tem/560 subchannel can or

cannot accept a channel command (consideration 3), use of

this capability would be rather awkward. Consideration 2

implies that system performance at moderate data rates can

be materially impi.oved in the lower-numbered mode]s by pro-

gramming the PDP-8 to operate in short multi-byte bursis.

The System/360 programming problems in connection with burst-

mode operations are similar to those arising in connection

with tape control unit operations on the multiplexor channel.

Consideration 3 is another implication of the general inter-

face characteristic that all commands are accepted if the

interface is not busy. Consideration 4 is an implication

of the capability of the anterface to clear asynchronous

unsolicited status presentations as the result of a pseudo-

Test 1/0 instruction.

! I

I

-37-

Following is a short summary of the operation of

System/360 1/0 instructions when directed to a device ad-

dress recognized by the interface. Only thos? features of

operation dependent upon the peculiar characteristics of

the interfs e are emphasized.

Start I/O

Issued to a nonworking channel and subchannel,

this instruction will always result in a comma id interface

operation involving the transmission of a channel command to

the interface. If both the command and service interface

are idle before transmission of the channel command, then

condition code 0 is set at the conclusion of the Start I/O

operation. I/O activity is begun and the subchannel is

placed in the working state. If the command interface is

busyj then conditio1: code 1 (CSW stored) is set at the con-

clusion of the operation. The device status field of the CSW

contains the busy, control urn... end, and status modifier

bits. No I/O activity is started and the command interface

is undisturbed following this operation. Normally the in-

dicated busy condition ma/ be expected to last in the order

of a few hundred micrcseconds, representing the interrupt

processing time of typical PDP-8 programs. If the command

interface is idle and the service interface is holding

pending status for the device addressed by the Start I/O

instruction, then condition code ] is set at the conclusion

of the operation. The device status field of the CSW con-

tains the status presented by the service interface and in

addition the busy bit. No I/O activity is started and both

the command and service interfaces are idle following the

operation.

Halt I/O.

Issued to a nonworking channel, this instruction

will always result in a command interface operation without

regard to the state of the subchannel In addition, the

-38

subchannel will be set up to signal the service interface to

stop data transmission the next time a service cycle is re-

quested If the command interface is idle prior to the is-

suance of a Halt 1/0 instruction, then condition code 1 is

set at the conclusion of the Halt 1/0 opei'ation and the status

field of the CSW ^s replaced with zeros. 1/0 activity is

stopped by the addressed device, which will then provide end-

ing status under control of the resident PDP-8 program. If

the command interface is busy, then condition code 1 is aiso

set following the operation, but the status field of the CSW

contains the busy, control unit end, and status modifier bits.

The Halt I/O indication has not been stored by the command

interface, although the subchannel is set up to signal this

condition when the service interface next requests a service

cycle

Test I/O

Issued to a nonworkmg channel and subchannel, this

instruction will always result in a command interface opera-

tion but will not affect the PDP-8 program unless status

presented is stacked by the channel (Ard whether this can

ever happen is highly dubious—see comments elsewhere in this

document,) Condition Code 1 will always be stored at the

conclusion of the Test I/O operation If the command inter-

face is b'^sy prior to the issuance of this instruction, then

the status field of the CSW will contain the busy, control

unit end, and status modifier bits If the command inter-

face is idle and status for the addressed device is available

at the service interface, then that status replaces the status

field of the CSW If neither of these conditions hold, then

tne single status modifier bit is placed in the status field

of the CSW

. i

-39-

Programming Notes

Contrary to published doctrine, it is evidently

possible to cause I/O interrupts from devices whose subchan-

nels are working, but without including the channel end bit

and without affecting the status of the subchannel. It is

not at all clear whether this is possible on all models or

whether unknown machine incompatibilities can occur. Use of

this feature (for instance as an attention intei upt) in

real-time control environments is obvious.

In some programming systems, an automatic Sense

channel command is issued {with channels disabled) when a

unit check bit is set in a status byte. These systems rely

on a Test I/O loop to clear ending status from the Sense

command. If the Test I/O loop is looking for device end,

then the cooperating PDP-8 program must present channel end

and device end together on the status byte which ends the

Sense command. Alternatively, the PDP-8 program must arrange

that a channel end status presentation for a particular device

address be followed onl^ / status pertaining to the same

device. Otherwise conflicts between the channel and the inter

face can occur in which the channel is asking for status (via

a programmed or pseudo-Test I/O) for a device that the service

interface is just not prepared to surrender.

V. ARCHITECTURE OF SYSTEM/360 INTERFACE*

The System/360 interface contains the registers and

control circuitry to provide a bidirectional asynchronous

transmission of both command, status, and data bytes be-

tween the System/360 multiplexor channel and the PDP-8. Tne

interface consists of four data registers, their transfer

gates, a cortrol register, and various sequencing circuitry.

The organization of these components is shown in Figure 9.

Logic symbology in this section corresponds to IBM standard usage Sei5 Preface

40-

C/3

>-

< B.

1-4

Of aa

* BO

f o

*< • (wai)

SDVX QNnosin 0 sa 00

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t/5 t—t _) CO (M O t o: Of

eg «c H

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0£ CQ ee =3

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♦

t CO 0£ (wai) t < >H cnv i ^

< f o QNnoaNi < sa

A

>■

H 1—4 »—<

CO cs < H CL 3

O

< oo

Q I Z O- 3 Q O CL 60 ^-'

< oo

Q I z a, 3 Q w O ß- H 03 w Z H w 3 z O c

a. s o

z u >-H

w CJ u < <

OS UJ

H z I-H

■^ oo _J HH 1 <

a. CL,

05 Q 1—1

z a. u z l-l

Of a.

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-41-

Referring to Figure 9, the four data registers are

designated Address Register 1 (AR1), Buffer Register 1 (BR1),

Address Register 2 (AR2), and Buffer Register 2 (BR2). All

four registers are provided with jam-transfer direct-coupled

diode-capacitor-diode (DCDJ gates from the test switches,

and, in addition, all except BR2 are provided with ones-

transfer DCD gates from the PDP-8 AC AR1 is used to hold

the device address presented by the channel during the initial

selection sequence and is provided with jam-transfer direct-

coupled (DCj gates from BUS OUT BR1 is used to hold the

command byte presented by the channel during the initial

selection sequence and is provided with ones-transfer DC

gates rrom BUS OUT. AR2 is used to hold the device address

presented to the channel during a service cycle. No inbound

transfer gating is provided except for the DCD gates mentioned

above. BR2 is used to hold a status or data byte during a

service cycle and is provided with ones-transfer DCD gates

from the PDP-8 MB and with ones-transfer DC gates from BUS OUT.

BUS IN is provided with ones-transfer DC gates from ARI, AR2,

and BR2 as well as constant generators 10, 40, and 70 (hex),

which are used to synthesize certain status bytes. The

PDP-8 AC is provided with a special set of ones-transfer DC

gates called the EAC bus, which is in turn provided with

ones-transfer DC gates from AR1, BRl, and AR2. The EAC bus

is used both to isolate the PDP-8 AC bus from the loading of

the transfer gates and to provide a uniform interface for

additional equipment, other than the interface, which may

be connected to the PDP-8. The PDP-8 MB is provided with onos

transfer gates from BR2. These gates are us^d in connection

with a special data multiplexor described elsewhere.

A nine-bit parity detector connected to BUS OUT

indicates that odd parity is present on these lines and is

used in conjunction with AR1, BR1, and BR2 when these re-

gisters are loaded from BUS OUT A parity error during the

42-

BR1 or BR2 loading operation will set the CMD PCK or SRV PCK

bits of the control register respectively. An eight-bit

parity generator connected to the BUS IN transfer gates pro

vides odd parity for the BUS IN (P) line and is used in con-

junction with all BUS IN operations.

An eight-bit zero detector connected to BR1 is

used during the initial selection sequence to detsct the occur-

rence of a Test I/O channel command and to condition the follow-

ing BUS IN status accordingly. An eight-bit compare circuit

is connected to AR1 and AR2 to detect when these two registers

contain identical bits and is: used during the pseudo-TIO

status sequence.

A three-bit decoder connected to BUS OUT is used

during the initial selection sequence to determine whether

the device address present on BUS OUT falls within the block

serviced by the interface. Eight blocks of addresses, each

consisting of a contiguous block of 32 addresses, may be

selected by a jumper card.

The twelve-bit Control Register (CTL) is composed of

a three-bit Order Register (OR) and a nine-bit Status Register

(SR). The OR is used to hold the order code during a service

cycle and is automatically reset following the conclusion of

a block transfer operation. The SR is used to hold tne

various bits that indicate termination conditions of the

interface sequences However, the SR has no direct connection

with any status byte that may be presented to the channel.

The logical details of these registers and their

transfer gates are shown in Figure 10, Figure 11 shows the

logical details of the PDP-8 data paths, and Figure 12 shows

those of the BUS IN data path? Circuit names, which appear

only in this simplified description, are indicated on these

diagrams In some cases the actual circuit names and logical

details differ from those recorded here The logical details

of the circuitry for all of these components are straight-

forward and are recorded in Appendix E, The logical organiza-

tion of the contro] and sequencing circuitry, however, is

- -

., I

45-

BAC{4-11)

SW(0-7)

B0(0-7)

AC-^ARl

SW-+AR1 BO-»-ARl O-^ARl

BAC(4-11)

SW(0-7)

AOAR2 SW-^AR2 0-*-AR2

ARl(0-7)

AR1=AR2

AR2(0-7J

AC*BR1 SlV'->-BRl BO-^-BRl

0-»-BRl

BRl(0-7)

BR1 = 0

NOTE: PWR CLR CLEARS ALL REGISTERS.

FIGURE lOa. AR1, BR1, AR2 REGISTE RS

44-

MBC4-11)

SW(0-7)

BO{0-7)

MB-*-BR2 SW-fBR2 B0-*-BR2 0-^BR2

BAC(4-11)

SW(0-2)

INV-*CTL 0-+-CTI ^"^^

SW(0-2)-K:TL{0-2) 0-^CTL(0-2) 0-»-CTL(6)

CTL OP

vMB(4-11)

•CTL OP(0--7)

0 IDLE 1 IDLE 2 BO REQ 3 BO REQ(BURST) 4 BI REQ 5 BI REQ(BURST) 6 STA REQ 7 STA REQ(PRI)

CrL = 0 1 2 3 4 5 6 7 8 9

10 11

:} OP

CMD CHN CMD PCK SRV PCK SYS RST CMD STK CMD HLT CMD END SRV HLT SRV E

LTS ND/

CMD 1NTF

SRV INTF

FIGURE 10b. BR2 AND CTL REGISTERS

45-

ARl(0-7)

AR1 SEL

ES (1'AND)

1«) ^>

BRl(O-V) Qlly

BR1 SEL

BRi I \ GATESl /

(8)

AR2(0-7)

AR2 SEL

F ^SGATES > V fNAND) V

(8)

♦ EAC(O-U)

CTL(0-

CTL SEL '"O CTL

GATES J(.NAND)

(12)

EAC(O-li) ^_ f>

EAC INV

(12) ^>

EAC GATES (NAND) (12)

EAC-AC

_>vv-

EAC(O-li)

c>

•BA cco-U) Q_

U +BAC(0-11)

EAC EAC»SKIP—i—| TEST

(12)

^

AC(O-U)

SKIP

Mß(3-8) L-v>l i or

HET

ARl SEL BRi SE;, AR2 SEL CTL SEL

EiGIiRE II. PDP-g DATA PATHS

46-

00-*BI

AR AR

_N BRI } K l(0-7)( ^3ATE5 ~—N IH-BI ^ (HAND) V

AR2 AR2

(0-7)[^S

BR2 1.32

70+BI

10+BI

40+BI

__is. BR2 (0-7)| >GATES -►BI V (HAND

0u< ,1 AR1-BI AR7+BI BI

BR2-<-BI 10-81 4 0-BI 70-»BI

PAR

GATE

PAR GEN (8)

|BI

^1 1

BI(P)

ADR DET

-B0vÜ-7)

-B0 (0-7) |— ^ "v -^ j V (8) 1/

PAR

GEN

(8)

BO PAR

| 1 ■ :

n n

n U

FMüRE 12. BUS GATING

5-5

li

n u

n

0

n

0

I n J

i i

u

f i

n u

: n

n

• 47-

central to the operation of the interface and is discussed

below.

Figures 15 and 14 show respectively vhe logical

organization of the circuitry used to intercept polling

signals from the channel and that used to seize the control

unit interface for the various kinds of sequences. During an

initial selection sequence, the OUR ADR gate (Figure 13)

detects the conditions for channel-requested service (initial

selection) and the REQ IN gate detects the condition for

control-unit requested service (service cycle). These gates

may not respond simultaneously.

The remaining circuitry shown in Figure 13 is used

in conjunction with the channel polling signal to detect the

conditions under which the interface may seize the channel.

The principal function il block in this circuitry is the

select latch, shown in simplified form in Figure 13 but

actually consisting of two interconnected flip-flops. This

rather interesting circuit is a high-speed two-mput switch

with inputs derived from SEL OUT and from the two service-

request gates OUR ADR and REQ IN. An analy ^s of this circuit

is given in Appendix C .

When SEI OUT rises at the interface while either of

the two service-request gates OUR ADR and R^Q I!,' have true-

valued outputs, the interface will fall into one of three

states: CMD CYC, SRV CYC, or CU BUSY (see Figure 14). If

OUR ADR is true and if the command interface is not busy

(i.e., contains no previously stored command), then CMD INT

is falsj and CMD CYC state is entered; if OUR ADR is true

and if the interface is busy, then CMD INT is true and the

CU BUSY state is entered. If OUR ADR is false and if REQ IN

is true, then the SRV CYC state is entered Entrance into

either the CMD CYC or the SRV CYC state causes OPL IN to be

raised after a short delay to allow the circuitry to stabi-

lize, and entrance jnto the CMÜ CYC state causes the address

presented by the channel on BUS OUT to be jam-transferred to

48-

OPL OUT AND OUR ADR

ADR OUT BO ODD PAR' ADR DET OPL IN

AND REQ IN

SUP OUT CHL REQ

OUR ADR OR AND

CU SEL REQ IN

FL GU SEL

' HLD OUT

AND SEL PF SEL OUT

AND

OPL IN I

FIGURE 13. SELECT INTERGEPTION I

fl

II

-49-

OUR ADR AND

CMD INT CU BUSY

CU SEL 9

FL CU BUSY

{ '

AND BO-^ARl

CMD CYC

PL CMD CYC

\ w

RST CMD

CMD CYC AND OR l OPL IN

AR1=AR2

CHL REQ STA REQ I ADR IN DLY CMD OUT

OR SRV CYC

REQ IN AND CU SEL FL . SRV CYC

RST SRV

FIGURE 14. CHANNEL SEIZURE.

-50-

AR1. Entrance into the CU BUSY state causes the control-unit-

busy byte to be placed on BUS IN, and STA IN to be raised

without disturbing any of the active interface '•egisters. The

CMD CYC and SRV CYC flip-flops each have their own reset line,

whiwh is connected to gates described below. The CU BUSY flip-

flop is reset when SEL OUT drops.

Figure 15 shows the logical organisation for the

circuitry used during the command-stora^e/proceed phases

of the sequences initiated by entrance into rither the CMD CYC

and SRV CYC s^zies. Both of these sequences begin by placing

on BUS IN the contents of AR1 or AR2 as appropriate and pro-

ceeding through the channel sequence until CMD OUT is dropped.

During the CMD CYC sequence the byte on BUS OUT is transferred

to BR1 when CMD OUT is raised by the channel. The short delays

indicated on Figure 15 allow time for ehe parity circuitry to

stabilize before bus transfers are executed.

Following the command-storage/proceed phase of either

the CMD CYC or SRV CYC sequence, both the CMD L'LV and CHL SRV

flip-flops are set. These flip-flops are reset when OPL IN

drops. When the CHL SRV flip-flop becomes set, a byte of

data or ft^tus information may be transferred between the

channel and the interface. If the CMD CYC flip-flop is set,

then the sequence ends by presenting to the channel either an

all-zero status byte or a status byte containing the status

modifier bit, depending upon whether BR1 has been stored as a

nonzero byte or a zero byte respectively. If the SRV CYC flip-

flop is set, then the sequence ends by transferring a byte

from BUS OUT to BR2 (channel-outbound service requested) or

from BR2 to BUS IN (channel-inbound data or status service

requested) with the appropriate tag line. If the CU BUSY

flip-flop i? set, then a status byte containing the status

modifier, control unit end, and busy bits is placed on BUS IN.

Appropriate delays are included to allow time for the parity

circuitry to stabilize and for skew distortion tc stabilize.

Outbound parity-checking circuitry is shown in Figure 17.

J

il

n

-51-

n

n

CMD CYC AND ARi-^BI

ADR OUT

CMD DLY OR ADR IN

DLY SRV CYC

AND ARZ-^BI

C"D OUT AND

DLY

ADR IN J

CMD DLY

FL CMD CYC

OPL IN

AND BO-BR1

CMD CYC

SRV INT AND CDCD; BPK STA

MPX SEL SRV CYC

BT2A OR CHAN SRV

CMD DLY AND [DCD]

CMD OUT* FL CHAN SRV

RST CHN

♦DROP TRANSITION

FIGURE 15. COMMAND STORAGE/PROCEED

I

-5?-

CMD CYC

SRV CYC

CHL SRV

BR1 = 0

S1A REQ

CU BUSY

AND CMD STA

AND SRV STA

AND SPC STA

AND

AND

OR

DLY

AND

00-+BI (ACCEPT)

40-*BI{STA MOD)

STA IN

70-»Bl I - BUSY)

lO-^BKBUSY

u

if ! ti 1

n

FIGURE 16. STATUS (J

n

-53.

ö a Q

BO^BRl AND CMD PCK

BO ODD PAR , FL

CMD PCK

BO-*BR2 AND SRV PCK

M. FL SRV PCK

FIGURE 17. PARITY CHECK

n

-S4-

If a status request is pending at the time an initial

selection procedure is signalled by the channel, then, if t.le

contents of AR1 match those of AR2, the SRV CYC flip-flop will

be set when the channel command is stored in BR2. f ee gate

next to SRV CYC flip-flop in Figure 14.) This special condition

is detected when the status byte is transmitted to the channel.

If both CMD CYC and SRV CYC flip-flops are set following the

command-storage/proceed phase of the sequence, then BR2 is

transferred to BUS IN and STA IN is raised. K, furthermore,

the command byte stored in BR1 during the sequence Contains

nonzero bits, then the busy bit is logically OR'ed into the

status byte. Figure 18 shows the details of the BR2 gating.

The terminating conditions for the CMD CYC sequence

are shown in Figure 19. If a nonzero command byte has been

stored in BR1 during a CMO CYC sequence, and if the channel has

responded to presentation of the all-zero status byte with SRV

OUT (any other response is an equipment check), then the CMD

END bit is set in the control register. If an all-zero com-

mand byte has been stored in BR1 during the sequence and if

the channel has responded to the presentation of the status

byte containing the status modifier bit with CMD OUT (stack

status on initial selection), then the CMD STK bit is set in

the control register. These are the only two bits that can

be set following a complete CMD CYC sequence, and they are

mutually exclusive.

If at any time, either during an interface opera-

tion or not, both SUP OUT and OPL OUT are down at the inter-

face, the CMD RST bit i= set in the control register. This

operation clears all control register bits except the CMD RST

bit, which is forced to the set condition, and in addition

clears all flip-flops in the interface to the channel-disconnect

condition. If during a CMD CYC sequence ADR OUT is up at the in-

terface while SEL OUT is down (interface disconnect) or SUP OUT

is up while OPL OUT is down (selective reset), then the CMD HLT

| i

I ':

0 n u

U

fl u

u n y

ü n ü

n 11

i I u

-SS-

0 u

n

n 1 I i j i-i

i 0 ü

n 5 I

n Ü

SRV IN AND

BO^BR2

3RV OUT BO REQ

3

SRV CYC AND CUL SRV

CTL(O) OR BR2-»-BI

SRV STA

SPC STA

OR SRV IN

AND

OLY

OR

[DCD]

0-»'BR2 (PULSE)

MPX SEL AND

BT2(PDP-8)

BRK STA(PDP-8)

CTLfO) 0002-^DA(PDP-8)

MPX HEI BR2-*Mbv.DP-8)

AND

IpcU

MB->BR2

BTl(PDP-8)

. BR2 GATIN

(PULSE)

BRK STA(PDP-8)

CTLCO)

F IGUR B 18 G

n I i

56-

CMD STA AND

AND

CMD END BR1 = 0

SRV OUT FL

CMD END

CMD STK

CMD STK FL

CMD STK

CMD CYC

ADR OUT

SEL CUT

OPL OUT

SUP OUT

f-

T

AND OR

n CMD HLT

FL

AND

AND fi-cn

FL

CMD HLT

SYS RST

(PULSE)

CMD RST

m il

FIGURE 19. COMMAND END

fl II

#* n = =

u

n i f

: i

-57-

bit of the control register is set. This operation clears

all flip-flops in the interface to the channel-disconnect condition.

The terminating conditions for the SRV CYC sequf ice

are shown in Figure 20. This sequence may end in three ways:

a. in a request for a data break operation to

fetch a data or status byte from PDP-8 core memory (SRK REQ) ,

b. m an ending condition which stops data trans-

mission and interrupts the PDP-8 program (SRV END and SRV HLT), or

c. in a stack-status condition which disconnect; the interface from the channel and

channel service, immediately re-requests

The PREP END flip-flop is set on a data or status

opeiation in which the PDF-8 block transfer word count de-

crements to zero. In the channel-inbound case the channel

luust either accept or reject the byte before an ending-con-

dition bit (SRV END or SRV HLT) is set in the control register.

Following the ending operation in the case either

of a CMD CYC or SRV CYC sequence, the interface is disconnected

from the channel with the circuit shown in Figure 21. Here

the various terminating conditions are detected and the reset

signals for the CMD CYC a SRV CYC flip-flops are generated.

In addition, signals are derived that condition the PDP-8

interrupt bus (INT REQ) and that indicate that the command

interface is busy (CMD INT).

The channel-request circuitry is shown in Figure 22.

Note that when a channel-outbound request is initiated a

special pulse is generated which sets the CHL REQ flip-flop

and starts the operation. Conversely, when a channel-inbeund

data or status request is initiated a special pulse is gener-

ated which sets the BRK REQ flip-flop (see Figure 20) and starts the operation.

-58-

wc=o 1 AND O D C M C M n

MPX SEL FL ■T

' 0+011(0-2}

SRV OUT ANP OR

SRV END

SRV CYC

(

. SRV HLT AND

<

AND [DCD]

BOREQ

BT1 BRKSTA

FL SRV END

AND

DCD

OR

SRINT 1

CTL(O) BRK REQ

FL BR" REQ

AND

ADR ACCP

SF V HLT

AND CR FL SRV HLT SRV IN CMD OUT

AND OPL OUT "

AND

—^ —

ADR OUT

FIGURE 20. SERV1CL END

i I

i \

u

a LJ

I ! i |

I t Ü

u

a

59-

CMD RST CMD END CMD HLT CMD STK

OR

OR

CMD IWT

INT REQ (PDP-8)

SRV END OR <

(

SRV INT

SRV HLT OR

0-^CTL(0-

DLY

0?. RST SRV

BR:. REQ

DLY

CMD INT OP. RST CMD

CMD CYC AND CMD BUSY

SRV OUT DLY

AND CHL SRV .

CMD OUT

FIGURE 21. CYCLE RESET

CTL(O)

60-

CTL(l)

FL

CTL(2j

2 a u m a

< U o

OR

OR

BO REQ

BI REQ

FL OR STA REQ

0

BO REQ OR AND

(DCD)

BT2A(PDP-8j(PULSE) AND SRV INT

BRK 3TA(PDP-8) CHAN REQ

MPX SEL FL CHAN R

SRV L'YC AND OR SRV OUT

SRV HLT

FIGURE 22. CONTROL OPERATION DECODER AND CHANNEL REQUEST FLIP-FLOP. V

Ü

i I

if

u i f

u

•61

Additional details of interface operation are sum-

marized in flow chart form in Appendix A. Circuit details

are shown in Appendix E.

U

n

11 u

Q

0 n I

J

n i \ w

;

APPENDIX A

CHANNEL SEQUENCE FLOW CHARTS

64-

RAISF STA IN (70-BI)

PROPAGATE SEL OUT

DROP ALL TAGS

FIGURE Al. CHANNEL SEIZURE

i i

-65-

U

u

0

Ü

BO-^ARl 0 •♦BRl

RAISE OPL IN

RAISE ADR IN (ARl-^BI)

B0-*-BRl

SET SRV CYC LATCH

SPC STA

FIGURS A2. COMMAND BYTE STORAGE

6ö-

SET CHL SRV LATCH

SET CMD END LATCH

RESET CMD CYC LATCH J

YES

RAISE STA IN (OO-^BI)

DROP ALL TAGS

r RESF CMD DLY AND

CHL SRV LATCHES

RAISE STA IN (40-^81)

\ f 1 i

Ü

FIGURE A5. COMMAND STATUS PRESENTATI ON \ \

IT II

-r Is

-67-

ii

n

I

( SPC ? I STA /

RAISE STA IN

CBR2+10+BI)

RESET CMD cy: AND

SRV LYC LATCHES

RAISE STA IN (BP.2+BI)

RESET CMD DLY AND

CHL SRV LATCHES

FIGURE A4. SPECIAL STATUS PRESENTATION

-68-

V SET

SRV CYC LATCH

RAISE OPL IN AND ADR IN {AR2-*BI)

RAISE SRV IN

RAISE SRV IN CBR2+BI)

Ui I i

II I

FIGURE AS. SERVICE CYCLE

n t : 1 I

i

u -69-

i i I i

u

U

Ü

FIGURE A6. SERVICE CYCLE END

70-

f

:

l i MB+BR2

:

RESET ^V BRK REQ ) LATCH J

SET PREP END LATCH

SET CHL REQ LATCH

( PR RESET

PREP END SET SRV HLT LATCH

| 1

^

FIGURE A7. PDP-8 DATA BREAK CYCLE

if y

: I i i

■ J

U

n

APPENDIX B

CHANNEL SEQUENCE PHOTOGRAPHS

m

\m /

n n .i

U

n i ! i i

-72.-

n u

1/xS/CM

Fig. Bl INITIAL SEIECTION

n

u

u

u 1/iS/tM

Flg. B2 SERVICE CYCLE

REOIN

OPLIN

ADR IN

CMDOUT

SRV IN

SRV OUT

■74-

FIGURE Bl

INITIAL SELECTION (lys/cm)

Line Name Signal Name Pin Polarity

1 ADR OUT ADO 1B01S IBM

2 OPL IN OP1 1B01D IBM

3 ADR IN ADI 1B()1H IBM

4 CMD OUT CMO 1B01T IBM

5 STA IN STI 1B0IE IBM

6 SRV OUT SRO IB31D IBM

Line

FIGURE B2

SERVICE CYCLE (lys/cm)

Name Signal Name Pin Polarity

1 REQ IN -> OPL IN

3 ADR IN

4 CMD OUT

5 SRV IN

6 SRV OUT

REI

OPI

ADI

CMO

SRI

SRO

1B31M IBM

IB^IP IBM

1B01H IBM

1B01T IBM

1B01K IBM

1B31D IBM

n 75.

1/iS/CM

Fig. B3 CONTROL UNIT BUSY

0.5/iS/CM Fig. B4 INTERFACE DISCONNECT

SUP OUT

-76-

FIGURE B3

CONTROL UNIT BUSY (lus/cml

L ine Name S ignal Name Pin Polarity

] ADR OUT ADO 1B01S IBM

2 SEL OUT SEL OUT 1B01P IBM

3 STA IN STI 1B01E IBM

4 SUP OUT SUO 1B01V IBM

FIGURE B4

INTERFACE DISCONNECT (0.5ys/cm)

Line Name Signal Name Pin Polarity

1 ADR OUT ADO 1B01S IBM -> SEL OUT SEL OUT 1B01P IBM

3 OPL IN OPI 1B01D IBM

4 ADR IN ADI 1B01H IBM

5 SUP OUT sue 1B01V IBM

:: -;

n

n

i {

Ü

i i

-77-

0.5/1 S/CM Fig. B5 CHANNEL SEIZURE

CMDCYC

OPLIN

1.0 SCM Fig. B6 GATE TRANSFERS

-78-

Line

FIGURE BS

CHANNEL SEIZURE (0.5ys/cm)

Name Signal Name Pin t olarity

1 ADR OUT

2 OUR ADR

3 SEL CUT

4 CU SEL

5 CMD CYC

6 OPL IN

ADO +

OURAD+

SEO+

SEL +

CMDCY+

1B18P

3B10P

1A22N

3B10F

3312L

1B01D

DEC +

DEC +

DEC +

DEC +

DEC +

IBM

Line

FIGURE 86

BUS TRANSFERS (LOys/cm)

Name Signal Name Pin Polarity

1 OUR ADR OURAD+ 3B10D DEC +

2 BO-*ARl BOAR1+ 3B13P DEC ♦

3 ADR IN BADI + 3A09D DEC ♦

4 ARl-BI AR1BI+ 3A13D DEC +

S CMD OUT CMO + 1A25U DEC +

6 BO-^BRl BOBR1+ 3A13J DEC

11 u

-79-

1.0MS£M

Flg. B7 MAJOR STATE-SERVICE CYCLE

MPX REO

MPX SEI BRK STA

CHI REQ

BT1

BT2A

l.C^S/CM

Fig. B8 DATA BREAK-SERVICE CYCLE

-80-

!

i CHL REQ

2 CU SEL

3 SRV CYC

4 CMD DLY

5 CH', SRV

6 BRK REQ

FIGURE B7

MAJOR STATES-SERVICE CYCLE (lys/cm)

Line Nam^ Signal Name Pin Polarity

CHNRQ+ 3B18P DEC+

SEL+ 3B10F DEC+

SRVCY* 5B13N DEC*

CMDLY+ 3A(«7J DEC +

CHS^V-t- 3A07P DEC* }]

5RKRQ+ 3B17P DEC+

•T 'I |i

FIGURE B8

DATA BREAK-SERVICE CYCLE (lus/cm) l|

Line Name Signal Name pin Polarity

REQ1 3A17D DEC- rj

SEL1- 27 ■ }£ DEC-

BRKSTA iB'UP DEO

CHNRQ+ 3B18P DEC+

BT1 3B29G DEC(P)

BT2A 3B2&T DEC(P)

1 MPX REQ

2 MPX SEL

3 BRK STA

4 CHLREQ

5 BT1

6 BT2

II

-81-

2/iS/CM Rg. B9 TEST PO LOOP

SUP OUT

IMS/CM

SEL OUT

SEL OUT PROP

SEL IN

0.1/uS/CM

SfcL OUT

SEL OUT PROP

Fig. BIO SEL OUT/SEL IN DELAYS

82.

FIGURE B9

TEXT I/O LOOP (2us/cm)

Line Name Signal Name Pin Polarity

ADO 1B01S IBM

OPI IBflD IBM

CMO IBjJIT IBM

STI 1B01E IBM

SRO 1B01O IBM

SUO 1B01V IBM

1 ADR OUT 1 OPL IN

3 CMD OUT

4 STA IN

5 SRV OUT

6 SUP OUT

FIGURE BIO

SEL OUT/SEL IN DELAYS

Line Name Signal Name Pin Polarity

(lus/cm)

1 SEL OUT SEL OUT 1B01P IBM

2 SEL OUT PROP SEL ?RP 1B02P IBM

3 SEL IN

(O.Iys/cm)

SEI 1601M IBM

1 SEL OUT SEL OUT 1B01P IBM

2 SEL OUT PROP SEL PRP 1B01P IBM

0

0 )

Lj

£ I

L]

! f

I APPENDIX C

ANALYSIS OF SELECT LATCH CIRCUITRY

ANALYSIS OF SELECT LATCH CIRCUITRY

The select latch consists of two interlocking flip-

flops interconnected as shown in Figure Cl. The outputs of

one flip-flop are designated 0 and 1 in the diagram and those

of the other flip-flop as 2 and 3. The latchback lines con-

nect from 1 to 1' and 3 to 3' respectively. The request

signal is designated —REQ and the select signal as SEL.

By straightforward analysis, -he state table of

Figure Cl is derived, which gives the outputs of the circuit

as a function of the inputs. Four states may be recognized;

and these are called Q, R, S, and T . (T does not appear

for any output and is an unstable state.)

A transition diagram for this circuit is shown in

Figure C2. The stable states are designated idle (no activity),

select (this control unit selected),and bypass (some other

control unit selected) . Gates connected to the circuit detect

the select and bypass states and inhibit propagation of SEL OUT

in the bypass case. These states and the output decoding are

so arranged that races between states cannot occur and so that

no noise appears on any output during transitions.

The circuitry is implemented using standard modular

components of about 35 nS propagation delay. Decisions and

state transitions must be completed in times comparable to

this .

Two of these circuits are used in the System/360

interface. One is connected to the CU SEL line and used in

the channel seizure operation; and the other is connected to

the CU BUSY line and used in the control unit busy operation.

■ 85-

86-

iridino

o •-* ra

a z < z

►

'

a z < z

(

a z < z

1 a z < z

K5 UJ

i .^

u H <

u UJ

UJ

UJ a:

t-H u.

n

y

Si

sindNi

n

87-

TABLE I

INPUTS

0

OUT PUTS

-REQ SEI 1 ■ 3' 1 n 3 STATE

0 0 0 0 .1 1 1 1 Q

0 0 0 1 1 1 0 I Q

0 0 0 1 1 ! 1 Q

0 0 1 1 1 0 1 Q

0 1 0 1 1 1 1 0 R

0 1 0 1 1 0 0 1 S

0 1 0 1 1 1 0 R

0 1 1 1 0 0 1 S

0 0 1 1 1 1 Q

0 1 1 1 0 1 Q

0 0 0 1 1 1 Q

0 1 0 1 1 1 Q

1 0 0 1 1 1 0 R

1 0 1 1 0 0 1 s 1 0 0 1 1 0 R

1 i 0 1 1 0 R

00,10

FIGURE C2. SELECT LATCH STATE TABLE

APPENDIX D

ADD'TIONAL CONSTRUCTION DETAILS

L

1 1

ADDITIONAL CONSTRUCTION DETAILS

Dl. System Configuration

The System/360 Interface as a component of the Data

Concentrator is assembled in two equipment racks which also

house a high-speed paper tape reader/punch and the various

power supplies and connectors which service the system. The

euqipment layout in these racks is shown in Figure Dl. The

PDP-8 occupies one of these racks in which space is available

for further expansion of extended memory, from the now

present 12K. The other rack contains interface circuitry, the

reader/punch, and the power supplies. The top three bays con-

tain the interface circuitry itself. These bays are connected

to the Test Panel immediately below, to the PDP-8, and to the

Channel Interface connectors (bottom bay) with DEC module con-

nectors. The tape transport for both the reader and the punch

are mounted on slides immediately above the operating table

as= shown. The two logic bays which service this equipment

are installed immediately below the table. Except for the

attacned PDP-8 cables, which are routed tiirough the interface,

this equipment is entirely independent of the interface.

At the bottom of the rack is a panel which carries

the four channel interface connectors. The eight cables which

connect to the Data Concentrator side of these connectors are

routed to DEC module connectors on Bays 1 and 2 above. The four

cables which connect to the IBM side of these connectors enter

through the fan hole in the bottom of the cabinet The fan

itself has been relocated to a panel on the rear plenum door

immediately below the power supplies.

The power supplies and AC distribution system are

mounted on the rear plenum door. A resonant -1ransformer—

regulated supply provides +10 volts aad -15 volts to the in-

terface equipment and Test Panel. A separate supply provides

various voltages to the reader/punch equipment. Power for

-90-

I

1

I

1

1

J

J

i

-91-

RACK 1 RACK2

SPARE SPARE

PDP-8

BAY 1

BAY 2

BAY 3

INDICATOR PANEL

PCOl TAPE

READER/PUNCH

MEMORY EXTENSION

PCOl BAY 1

PCOl BAY 2

SPARE

CHANNEL CONNECTORS

TABLE

FIGURE Dl. PHYSICAL CONFIGURATION

]

-92-

margin-check operation is obtained from an internal supply of

the PDP-8. Switches mounted on each mounting bay allow power

for that bay to be obtained either from the regular supply

or the margin-check supply. The Power Control Unit provides

AC power to the Data Concentrator in response to control

signals issued by the parent IBM system. Power requirements

for the Data Concentrator, including the PDP-8, total about

two kilowatts at 115 VAC. A single 30-ampere circuit is used

to power the equipment.

D2 Power Control Unit

All line power to both the PDP-8 and the interface

circuitry is controlled by the Power Control Unit. This

equipment sequences power on and off in response to standardized

signals furnished by the System/360. The operation of the

equipment in response to these signals is summarized in

System/36Q Power Control Interface-Original Equipment Manu-

facturers' Information, IBM Corporation, Form A22-6906-0.

The Power Control Unit (Figure D2) includes a

24V DC power supply, which is connected to the line power

at all times, and two relays. One of the relays is actuated

by the power sequence control of the channel and turns on the

line power to the PDP-8 and interface circuitry. The other

relay is actuated by a DC power supply in the interface

circuitry and enables the power sequence control of the channel

to step to the next control unit on the interface.

Two switches are used to control the operation of

the equipment. One of these, the LOCAL/REMOTE switch, is

used to transfer control of the equipment between the channel

(REMOTE) and the local controls (LOCAL) for maintenance pur-

poses. This switch should not be actuated while the equip-

ment is in the on-line state. The other switch (POWER ON/OFF)

actuates a relay which turns on line power to the PDP-8 and

interface circuitry. ft is effective only when the LOCAL/

REMOTE switch is in the LOCAL state.

I

I

i

I

J

I

J

BLANK PAGE

/ /

-93-

o 0. 03

' j 0£

U3 f- H U o — a Z 3 o 3 O B.

n Ui

I Ü

EPO CONTROL 30DEC66

KEB

1 ( »

'. IN

SID

E

POW

ER

ST

RIP

-

■"i ' .

/ < 1

J o H

o Ü a: LU 3B o o.

a

u

-ojb-

r i

u

-94-

D3 IBM/DEC Interface Modules

The accompanying circuits have been designed to

provide IBM/DEC compatibility in a package appropriate for

installation in DEC 1943 Mounting Panels. Characteristics

have been chosen to satisfy the requirements outlined in

System/36Ü I/O Interface—Channel -to-Control Unit Original

Equipment Manufacturers' Information, Form A22-6843. None

of the available DEC modules satisfy these requirements,

notably that which specifies that the components not disturb

the interface bus lines in the event of power failure or off-

line operation.

BUS DRIVER (Figure D3)

Input

DEC standard levels of -3v and ground, The circuit

acts as an AND for negative true-valued inputs and as an OR

for positive inputs. Other input characteristics are identi-

cal to those of the Rill Diode Gate.

Output

IBM Standard SLT bus levels of ground and +3v. SLT

conventions assign a logical 0 to ground level and a lo.ical

1 to +3v. The leakage in the 0 state is less than InA at +3v

and the output voltage in the 1 state is 3.85V at 59.3 mA and

4.5 at 30 pA. In a power-off condition the leakage in either

state is less than InA.

Performance

Propagation delay is 45ns for output rise (0 to +3V)

and 2Sns foi output fall (+3v to 0). Transition time is 20n5

for output rise and 10ns for output fall. Characteristics

are not significantly affected for power supply variation of

^SV on either the +10V or the -15V supply.

n

..95 r,-

> o

i mo

tu

=> Q O

x a > ez

CO

CQ

H

U

a

CJ3 i—( u.

-96-

BUS RECEIVER (Figure D4)

Input

IBM standard SLT bus leveis of ground and +3V. SLT

conventions assign a logical 0 to ground level and a logical

1 to +3v. The circuit is non-inverting. Input bu« load-

ing is +250IJA at +3V and-gopA at ground. ( + equals conven-

tional current into the receiver input.) The input impedance

(at Ikc/s) is 10K ohms. In a power-off condition the input

bus is loaded at iiSSyA for an input voltage level of +3v,

and linearly decreases to zero as the input voltage falls

to zero.

Output

DEC standard levels of -3v and ground. Output

characteristics are identical with those of the Rill Diode

Gate.

Performance

Propagation delays and transition times are all

20ns for both output rise and output fall. Characteristics

are not significantly affected for power supply variations

of -f^SV on either the +J0V or -15V supply.

SELECT-OUT BYPASS (Figure D5)

This module contains an encapsulated DPDT relay,

together with its driving circuitry, ant' in addition an

electronic switch which provides termination for the SEL OUT

signal on the channel-control unit interface cables. The

terminator is a 92-ohm resistor. Bus voltage levels are

expected to be in the »ange zero to +5V.

Input s

DEC standard levels of -3v and ground. Relay driver

ground level activates relay armature. Terminator switch:

ground level causes terminator to be disconnected.

-97-

4 0-15V

ALL TRANSISTORS 2N2894

FIGURE D4. IBM TO DEC BUS RECEIVER MODULE

98-

s u

1 T

—O

f .* ' N

u- —O

TERMINATOR DRIVER

-15V

+ 10V

FIGURE D5. SEL OUT BYPASS MODULE

APPENDIX E

LOGIC DIAGRAMS

? ,5

; S

-101-

U

ü

U FIGURE El. AR1

102-

1 B9(0-7) + > NAND R123

2B13 2B15

K AND R002 2B17

BR] ̂ r INV R107 2BI8

TSTI0-

j

BQbRl* P^ F V K

T '

PDCBR1

IN 5 V

• i

INV R121 3A12

TSTIO+

N^ E D iswrii.7u

PSWBRl

V AND (DCD)

n i

FL R205 2A13 2A16

\/

> ; " BR1{0--. ,-

■ ' "■ 1

l

AND (DCD)

BRl(0-7)+ >

1 s 1 Hi

« i f

y

|SW(0-7)-

PACBR1

AND (DCD)

$ |BAC{4-11)-

BRIAC+

9=m

K NAND R123 2B13 2B15

i w

^ EAC(4-il)- > Y \ f

FIGURE E2. BR1 [ !

Ü 103-

PWCLR-

I0P2-

AR1AC- AND (DCD)

OR P.A. R603 2AJ58

PB0 S.T. W50i 2A04

SWAR1

AND (DCD)

S D,F K

L OFTST-

P.A. R603 2A08

PDCAR1

PSWARi

P.A. R603 2A08

PACAR1 T

IOP4

/»ND (DCD)

R AR1AC-

S

PWCLR-

B9AR1

FBI

OFTST-

H C.J.

jn AND (DCD)

IOP2-

AND (DCD) BR1AC-

E

F

OR P.A. R602 2B20

S.T. W501 2A05

SWBR1 D.F AND

(DCD)

P.A. R603 2B16

PDCBR1

PSWBR1

P.A. R603 2B16

M IOP4-

AND (DCD)

K BR1AC-

L

FrtCBPl

FIGURE E3, AR1/BR1 PULSING

104-

PDCAR2

|SW(g-7)4 JjT

PSWAR2

PACAR2

AND (DCD)

{SW(0-7)- J)

AND fDCD)

|BAC(4-11)- ^

AND (DCD)

FL R205 2A20 2A23

AR2AC+

AR:BI+

c> NAND R123 2B21 2B23

i> NANH R123 2821 2B23

AR2(0

AR2(0-7)+

2Ej>

EAC(4-11) J>

BBI(0-7 ^>

; ]

[ i

Li

j

y

i

FIGURE E4. AR2

^^■M

-105-

IBQf0-7)

B0BRZ+

PDCBR2

PSWBR2

PMBBR2

J NAND •^ D 1 -) T R123

2B25 2B28

{SWf0-7)^ ^

SEL1

BB2BI+

AND (DCDJ

|SW(0-7)- J)

AND (LCP)

rBME(4-ll)- J)

AND (DCD)

FL R205 2A25 2A28

5Z

^ NAND R123 2B2S 2B28

^

NAND R123 2B25 2B28

BR2(0-7)

BR2(0-7)+

$

>

MB(4-11) c>

BEI(0-7) ^>

FIGURE ES. BR2

PWCLR- OR

P.A. R603 2A24

J I0P2-

AND (DCD)

D AR2AC-

1

PB2

OFTST-

PWCLR-

2BR2

PB3

OFTST-

S.T. W501 2A06

SWAR2 D.F K

-n AND

PCD)

IOP4-

AND (DCD) AR2AC-

R

S

P.A. R603 2A24

XI AND

|(DCD)

BR1-

AND (DCD) BRKST-

P

R

OR P.A. R602 2320

S.T. W501 2A07

SWBR2 D.F D AND

(DCD)

P.A. R603 2B24

PA R603 2A24

PDCAR?

PSKÄR2

PACAR2

PDCBR2

PSKBR2

: f

ft

BT2A-

BRKST- AND (DCD)

r.A. R603 2B24

PMBBR2

FIGURL F.6. AR2/BR2 PULSING

-107

BSRI + SRO + BOREQ+

NANÜ R121 1B26

BOBR; |lNV: -

BOBR2+

R107 1B25

SRVCY+ CHSRV+ BIREQt

SRSTA- SPSTA-

SRVCY+ CHSRV+ BOREQ+

M NAND R121 1B24

M

IN

CHSRV+

NAND R121 1B2S

SCCSBI

NAND R121 1B24

SCCSBO

NAND R121 1B25

NAND R121 1B2S

ZBR2

1<

BR2BI+

BSRI +

ZBR2

CTL0P+ S NAND R121 1B26

BRKST- BRKSTA T R SEL1 + U

FIGURE E7. BR2 GATING

-108-

2CTL0

K . |BAC(p-2)- ■■ \

AND (DCD)_

—1/

I0P4- R AND (DCD) P.A. R603 2B16

mc

FL R2P5 3B16 3B17

_K T CTL(0-2)- >

CTLAC-

_.A

\ - —~V

S K )

AND (DCD)

CTL(0-2)+ > V V

K |sw(«-2)- ;

AND (DCD)

y

SWCTL K NAND R123 5A25 3B25

SCTL(^-n)+ > CTLAC + K

EAC(0-11)

ZCTL3 _ •v

|BAC{3-S,7-11)- ■v AND

(DCD)

1 FL R205 3B19 3B22

fS CTL(3-5f7-ll)- >

_N K _

AND (DCD)

CTL(3-5.7-ll)+ > V V

ZCTL6

AN DC ( r

D D)

BAC06- •sr"

AND [DCD) _

r FL

R20S 3B18

rTL06-

AND "" DCD)

CTL06+

PBAC (

SVSRST

.»

FIGURE E8. CONTROL REGISTER

-109-

+ Sl. (M J SL H IJ

U H M u

u

vO -3 H U M

IS. U a

a rt t^ 2 CM r-t < ^ < Z Ct tn

in

H OS CO >

H i»

»J ac rj H -J si U u ►J 0- s H *—» a. U N

Q »H l«v Z rvi —< < -H < 5^ «• M

5: z a.

f- i -j tf) ä f- o: -j u w u 0, > 2 f—t

to CL. M

H

.^Ä > «■, -H Z ^i CO t-1 Oi to

=5 vO u a I

Q rH t-. Z «N 1-^

< -1 < z oi to

•-5

1 a: f- -j j u a- X HH

a. N

as

H co i—*

ta tu a:

~] o a:

Z o

w

H CJ Z l-H

<

a:

i—i

u.

no-

BOR1 BOREQ+

: 1

i i

K

DECODER R:5I : \2 2

0

1

2 P

|CTL(0-2)+ > V D

NAND R113 3A23

F .

3 R BOR2 E D BOREQ- E INV R107 3A24

j

4 S BIR1 BIREQ+

\

H NAND Rli3 3A23

K . i J

5 T BIR2 J F BIREQ- - K H INV R107 3A24

«

CTL(0-2}- )

6 U STR1 STREQ+

. 1 V

L NAND R113 3A23

N

7 V STR2 M

DISABL

**

I "

P NAND R113 3A2 3

S

suo* R I T

FIGURE ElO: CONTROL OPERATION DECODER

BOR2 T NAND R113 3A23

V BURST+

BIR2 U K INV

R107 3A24

J BURST-

n

■

Ill

AR1AC-

--

FIGURE Ell: IOT DETECTION

u

n

112.

AR1AC- S NAND R121 3B06

EACENB BR1AC- T R 1 AR2AC- U CTLAC- V H

NAND R113 3A06

K

I0P1 ^ J

^3B24

,

L NAND R113 3A06

N S

RDENB ^ INV. R107 3A13

RDENB+ U s R M

INV. R107 3AI3

EACAC+

READ ENABLE

EACAC-

u

IOP2 ACTEST

SKPENB

3B24

J

CTLAC-

NAND R121 3B06

H

BOREQ.

SEL1 +

DICD R001 3307

NAND Rill 3B08

CTLSK1

CTLSKP

NAND R113 3A06

NAND R121 1B28

FIGURE E12.

H M SKIP- INV.

R107 1A30

SKIP

SKIP +

XFER

TRANSFER DIRECTION

If

113-

JEAC(g-ll)-

3B24

D-S

|BAG(g-11)- J> INV. Rlg7 3A27 3B27

BAC(0-11)+

3B24

ACTEST

MASK TEST

EAC{0-11J+

EACAC+

NAND R123 3A05 3B05

ALLgLJJJ ^

GATE EAC AC

LEAC(0-11)

iSW(0-7)^

INV. R107 2B18 2819

^

INV. R107 2A29 2B19

EAC(0-11)+ >

SW(0-7 ^>

[ARlf0-71>

lAR2(0-7)^

3B14

AR = AR

ADD. REG. COMPARE

FIG' RE E 13

-114

40BI +

BBI1-

BBI2-

BBI3-

MAT US

\B0(V-2U y

JBO(0-2)- ^\

M 001F

JUMPER W990 iP3f)

ADRDT- INV. R1J37 1B27

ADRDTf DECODER N 203F E D S R R151 P 40SF F iB29 J^ 607F H

S S09F J T A,0BF K U C0DF L V E0FF M

N

ADDRESS DETECT

FIGURE E14

ÜS-

SRVCY+

SRO +

PWCLR-

CTL10-

SYSRST

BOREQ-

NAND R121 3A21

:LRCR-» NAND R121 iA21

H M INV. R107 3A14

&

AND (DCD)

BT2A- V AND (DCD) SRINT- S

NAND R121 3A21

SBM S BRKSTA T R SEL1 + U SRVCY- V

FL R20b 3B18

:MNRQ-

CHNRQH

CHANNEL REQUEST

FIGURE E15.

-116

B9PAR-

OURAÜ+

K INV. R1(S7 3B1(5

SPROP+

R J

aPROP-

; i

Li

FIGURE E16, SELECT INTERCEPTION

117-

i 1

0

:

CM I NT:

OURAD+

NAND R121 3B11

0URCM1

D " J

J~

NA.ND R121 3B11

QURCM; r

NAND R121 3B11

NAND R121 3S11

E

0URCM4

OURCM3

StL +

PWCLR- INV. RIO? 1A21

PWCLR- R

RSTCMD

NAND R121 3 B 1 2

1 NV RJ07 3B13

CUBSY*

CUBSY-

NAND Ri21 3Bl2

INV. R123 2B23

INV. R123 2B23

INV. R107 3313

F BOAR1+

BOAR1-

BOP1 + 1HV . Riß? 1A30

3 SRV " K

INV ADO* P R107

1A30 CMDCY*

AR = AR

CHNRQ«D

STREQ*| 5A 1+ J

CMO+ L

AND R0PI 5B15

NAND R121 3B12

NAND Rill 3B14

INV RIP; 3B13

NAND R12I 3B12

CHDCYt

INV. aifi? 3B13

CMDCY-

SRVCY-

E CSAC H K

M

RSTSRV

I N V . R107 3 B 1 3

NAND R:21 3B?6

D BOPI+

t, INV. Riß? 3B13

INV. R107 3A14

BOP1 T

SRVCY+

INV. R107 3B13

SHVCY-

u FIGURE E17. CHANNEL SEIZURE

-118-

CMPCY+ M NAND R121 3A09

AR1BI- U INV. Rlt/7 3A13

D AR1BI+ AD9- N L ' CMDLV- , P

H NAND Ri21 3A09

D BADI +

f

J NAND R121 3A09

H H INV. F AR2Bi+

SRVCY+ K AR2BI- RI07

3A13 u

BAD I* T NAND RIi3 1A25

CDYl INV. Ri07 1A27

CDJ2 INV. R107 1A27

CDY3 AND (DCD)

FL R205 3A07

CMDLY+

CMO + U V H L f P N M J

BOPI + ^^r D AND (DC:}

CMDLY-

BOBRI-

JF E

S - (INACTIVE GATE)

M NAND R121 3A08

L K INV. RI37 3A13

J BOBR1+ N

CMDCY+ P

CMDLY+

CMO-

BT2A-

RSTCHN

BOPI +

NAND R12I 3A08

CHSRS N

xl AND (DCD}

SRINT- S

BRKSTA T SELI* U SRi/CY* V

K'AND R12I 3A08

SBMA AND (DCD) FL

R2PS 3A07

nL_f INV. R121 3A08

CHSRV+

CHSRV-

n

li FIGURt EI8. COMMAND STORAGE n

119-

n

1

u

Q

CMDCY^ M NAND R12J 3A15

L « Kl INV, R107 3A14

00BI- ̂ 40BI- INV. R107 1A27

40BI +

SRVCY- I

<

J J NAINU R121 3A15

H U T

CHSRV-- P 1 K

00B1 + TSTIO+

SRSTA-

CMDCY- s NAND R121 3A15

c L NAND R BST1 +

SRVCY+ T 1 ■ R:21 I 3A16 !

( U R I

STREQ+ \

i CUBSY-

M NAND R12 i 3A16

L SPSTA- N P H

INV. R1U7 3A14

F SPSTA+

J NAND R121 3A16

10BI- INV. R107 1A27

10BI +

TSTIO- K H S R

FIGURE E19 STATUS

n

-120-

rsTio- P NAND R121 3A12

L CTL09-

SRO + N

CMD.ENu 00BI + M

K NAND R121 3A12

H CTLJI7-

CMO + J CMD.STACK

CMDCY+ S NAND R121 3A12

R CTL08- ADO»- T

INTF.DISC. SEO- U

SRSTA- E NAND RlZl 1B28

CMDCHN NAND R121 1B28

L CTL03-

F D M

CMD.CHAIN SPSTA- N P

SUO+ SRO +

FIGURE E2Ü. COMMAND CYCLE END.

-121.

ADO +

SEL.RST,

INTF.DISC,

SRV.STOP

CTLip-

SERVICE END

SEL1 + -—I INV.

R107 3A14

1B05 JUMPER

CYCSEL

l)ADR09

FIGURE E21. -HTA BREAK

122-

SELi* iyc=0

NAN'O i| ra2i it'

3A11 Tin I INV. R107 3A13

2CTL0

SRO +

SRVCY+

CTL10+

(SRV ' LT)

BOREQ* SEL1 +

:r NAND R121 3A10

PREND+

PREND-

NAND R121 3A10

NAND R121 3A10

NAND R121 3A1JJ

CTL11-

SRV.END

BT1 T

BRKSTA S

NAND R121 1B28

BTÖRK-

R S

1 BTBRK+

FIGURE E22. DATA BREAK,

1, INV.f" R107 1A30

BURST* E NAND R121 3AI6

D 5R0BUR E 1 NAND R121 3AI7

rj RBQi

SR(U . F F

'

S NAND RI21 3A09

R PREND- T SRVCY* U SRINT- V

CTL00- V AND (DCD)

JJ1 FL R2f»5 3BI7

P BRKRQ+ »

SEL1- u AND (DCD)

"'

BRKRQ-

R ADDACP

M !NV- M R107 3A13

ADDAC■ L N

PWCLR-

.:

i

: i L*

■--

= ■ £

1 . i^tf 1

i

r? 1 -:

•-jt i

n

123-

CTL06- CTLI97- CTL08- CTL09-

NAND

3A20

CMINT+

INV. R107 3A14

"MINT-

INTRPT

PDP-8 INTERRUPT

CTL10-

FIGURE H23. SERVICE CYCLE RESET

-174-

SWRST

suo- J NAND R121 1B24

SUOPO AND (DCD)

OPö- K H R

c S

f

SYSRST

SYSTEM RESET

■ t

BOPI + U NAND R113 3A06

v m RSTCHN

1 BURST+ P

NAND R113 3A06

BURBK-

R BRKRO+

Q

CHANNEL SERVICE RESET

CMINT- E NAND R121 3AJ8

D RSTCMD

_L SRO + J

NAND R121 3A18

SCCC

1 K

H

)N EL

L

F CMDCY+ "SS*

S IN

, M

COMMAND CYCLE RESET

FIGURE E24

TACK C IT. S

NAND R121 3A18

CHSRV+ ' ' N CMO + P

SE LECTI RESET

VE

S T NAND

R121 3A18

R OPO- SUO + U

1

'f

if i

1 i I — i

u I

I i 125-

B06 +

Be?-. D NAND M13 1A24

E

896- NAND R113 1A24

897- H

J

FIGURE E2S. BUS OUT PARITY

BB10* NAND R113 1A07

''.ill* H

J

BBI0-

BBJ1-

r.BI2 +

BB!3<

BPn-

S BI 3 -

BBI4 >■

BBI5*

PARIA

NAND Rllj

1A07

♦

HlNV. R107 1A03

(

-126

t-ARIB

PAR ID

fTJNAND R1 ,i 3 uns

PARII r-f—:

J

INV. R107 1A09

PARIJ N L

PARII,

rü1

r-— NAND R113 1A08

NAND R113 IA07

PARIC

NAND R1I3 1A07

xNV. R107 IA|9

iJ i

. J NAND R113 1A08

PAR IE r PARIF INV. R10-" IA0 ' ARIH

BBI4-

BBI5- T NAND R113 1A07

U

PAPIK NAND R113 lAJe

NAND R113 1AI0

M

NAND R113 lAIf)

U^

PARI T-*—

NAND RI13 1A08

INV. R107 1A09

R

BBI6 +

BBI7 +

"BIf

BBI7-

NAND RH3 1A08

PARIG

NAND KIIJ 1AI0

INV. RI07 1A09

J

FIGURE E26. BUS IN PARITY

"

127-

PARO

BOP +

BOP-

BOBR1+

BO-,R2 +

INV. RIß? 1A26

PARO-

NAND R113 1B23

BOPAR

D

NAND R113 JB23

INV. R107 1A21

BOPAR

BUS OUT PARITY CHECK

NAND R113 1B26

NAND R113 1B26

H

CTL04

(CMD PCK)

CTL05-

(SRV PCK)

AR1BI+ E F AND| D BB1P- E

INV. R121 IB24

D BBIP +

AR2BI+ H

• 2B29

AND

OR LB22

BR2BI+ ( , J

AND 00BI+ '

L

AND

BUS IN PARITY

FIGURE E27.

( i N

10BI + r p AND

AND

i

R 4|?BI + 1 S CHECK

( T

CUBSY+ U

AND T

V PARI U

INV. R107 1A09

P\ RI-

-128-

rBojjj-p)

ONLIN-

1SBO(0-P)

OFLIN+

^

BRCV 1B14 1B18

BBQ(^-P) C> I.

NAND R123 1A12 lAi4

NAND R123 1A12 1A15

2B29

BO(0-P) 0

iz X TNVT] K

V 1A17 V 1A18 BO(0-P)+

TAGS >>

TAGS = ADO. CMO, SRO, OPO, SUO

ONLIN+

(BSRO IS DELAYED)

BRCV 1B18 1B21

STAGS

i ^iAGS OFl.IN +

STAG^ = SADO, SCMO, SSRO SOPO. SSUO

NAND R123

^ 1A14 jlA16

|1A22

TAGS- i>

NAND R123 1A15 iA16

d>_ ̂

INV. R107 1A18

TAGS *>

NOTE: BSRO NEEDS A DELAY (0.001 yfd TO GROUND)

* -IBM LOGIC LEVELS

FIGURE E28. BUS-TAGS OUT GATI NG

-129-

!

C ! I {

u

SELOUT

OFLIN-

HLÜ

BRCV 1B20

BRCV lB2i

SSE02fDOWN)

OFLIN+

SSEOl(UP)

BSEO M

** BHLO N

JHLO

NAND R121 1B23

INV. R107 1A22

HLO-

SEO-

NAND R121 1323

SEO +

NAND 1123 1A16

INV. RIJ)? iA22

INV. RH97 1A22

NAND R123 1A16

SEO +

SEO-

* IBM LOGIC LEVELS ** REMOVE AT EC 29 DEC 67

FIGURE 029. SELECT OUT GATING

-150-

iBBI(g-P)* ^ ONLIN+ " V

NANÜ BDRV 1B06 1B10

BI(0-P) •>

|(TAGS)

X BADI + BSTI + BSRI + BREI+ (NO DELAY) BOPI +

ONLIN+

C> NAND BDRV 1B10 1B12

(TAGS) ■N ADI STI SRI REI OPI

V

SPROP+ T}

BDRV 1B13

* SELPRP

OFLIN- H )

SELPRP

*IBM LOGIC LEVELS

(from relay)

FIGURE E30. BUS-TAGS IN GATING n

;:

J,31-

BREI- M ADO- N BOPT- P

OLSW1

(-3v .for on-line)

OLSW2

NAND R121 1A20

RGATE- INV. R107 1A21

RGATE+

(3v for off-1ine)

NAND R121 1A20

OLR-

RGATE+

INV. R107 1A21

OLR +

NAND R121 1A20

OLR + INV. R107 1A21

OLR-

TO RELAY DRIVER

1

«

»1AJ9 «

ONLIN- i E INV. R107 1A22

D ONLIN+

ROM RELAY CONTACTS

ONLIN-

1 ► 1A19

OFLIN- "j * H INV. R107 1A22

F OFLIN*

OFLIN-

FIGURE E31. ON-LINE/OFF-LINE CIRCUITRY

-132-

TEST E NANÜ R121 1A20

D OPTST+

OFLIN- p E

INV. Rlß7 1A21

D OFTST- w • ...

PB4

PBS

PB6

P87

R123 INV. 2B03

NAND R121 1A20 2B04

SWCTL D,F

R123 INV. 2B03

NAND S.T. W501 2B05

Z1PCTL D.F

R123 INV. 2B03

NAND S.T. W501 2B06

PWCIR D.F

M Ri23 INV. 2B03

NAND S.T. W501 2B07

SWRST D.F

FIGURE E32. TEST PANEL PUSH BUTTON BATING

I I I I

= i -: - y

:;

n «

133-

. i

n I i

n

D

(VJ (N fO 2 en to S o

! CQ 3 1 CO < —i M aa i—* t—t H to to

vO 00 O I

in a o a.

00

(O o

o s w

i-< i-< OQ O

o i ! O.

tO Q o a.

OSO r CO <

f-< p—i f->

O

^J ^ Z

-1 to

< a.

H o to to tu

H

ca

rj c/5 2- to U ,,;

PH to to w

H

to •-

n to o tu

tu

H <N CO

O W tu z <

C-J oo o tu

tu

f-

o tu H

aa

CD

< D.

<N 00 ^ tO i fo

-< a JE tO D.

O to

<M tu

^ 00 C 1

i a. to o O IX

™ 00 O i

I cu -I Q o a.

CM oo o to I K}

i a- u. r-i Q 5; c-O CL

O 00 -Tf to I to

t a, u. was IN a.

CO

to

o

w o G.

oe! O

u tu a

o

to to tu

tu

U

T 00 O i

I ex. tO Q O a.

fM 00 (M O ■ o

PH o a o a.

CO

to

134

{AC(0-8j

CABLE FROM

DEVICES W021 5R02

7S>

CABLE TO 8

K CABLE 1 y PDP-8 V^ W021

3A01

D AC00 E AC01

AC02 AC03 AC04 AC 05 AC 06 AC07 AC08 i I

CABLE FROM

DEVICES W021 3B02

V ACJ V

CABLE TO

PDP-8 W021 3B01

D D

E T . H H K - M ' . M P rACCLR P S RUN S

T IVCJ1 1 AC09

AC10

AC 11 SKTp M CABLE TO

MULTIPLEX W021

INTRPT K REQ1 * D

E r 2B30

IJ

O DADR00 F. DADR01 H DhDR02 K DADR03 M DADR04

I3B08

j CAßLE DEVICES

W021 1A04

DATAADD(0-« D CABLE

TOPDP-8 17021 IA03

SEL1-

INV. RI0-

3A1

R SELU

P DADR05

CABLE FROM

DEVICES W021 1B04

V DAJ V

CABLE TO

PDP-8 W021 IB03

S DADR06 T DADR07 V DADR08

D_ D L ^ E H H K T BRKREQ K M ^ N P P S S T MB IN CR T

DADR09

DADR10

DADRU AÜDACP

XFER 1 BHKSTA

I i

i;

FIGURE E34. PDP-8 CABLE CONNECTORS fPage 1 of 3)

u i

-135-

1A22

j MBr4-8)

CABLE DEVICES W021 3A03

MB(P

~7\ CABLE

TO f'DP-8

3A04

D MB00 E MB0i H MB02 K MB03 4 MB04 ? MB05 5 MB06 T MB07 V MB08

.MB09 MBi0 MBli

CYCSEL

CABLE FROM

DEVICES W021 3B03

1A19

CABLE TO

PDP-8 W021 380''

WC = 0

D EAC00 E EAC01 H EAC02 K EAC03 H EAC04 P EAC05 S EAC06 T EAC07 V F.AC08

D EAC09 E EAC10 H EACH

.28

3B28

CABLE DEVICES W021 3A28

CABLE FROM

DEVICES W021 3B28

EAC(0-8) ^

EAC(9-11 ♦ RDENB SKPENB

D BAC00 F. BAC01 H BAC02 K BAC03 M BAC04 P BAC05 S BAC0f T BAC07 V BAC08

3830-29

CABLE DEVICES

W021 3B30

K CABLE TOPDP-8

W021 3B29

J V

i BACf0-8)-

PDP-8 CABLES

FIGURE F.34. PDP-8 CABLE CONNECTORS (Page 2 of 3)

-136-

BBIP + D

W021MJ CAüLE TO

TEST PANT 2B3L

0^10 + E BBI1 + F BBI2 + H BBI3 + J BBI4 + K

BBI5 + L 1B16 + M BBI7 + N CTL,00 + P

CTL0i+ R CTL02+ S

CTL03+ T CTL04+ U CTL05+ V

(ISOLATORS ON ALL LINES)

BOP + D

W021MJ CABL.. TO

TEST PANEL 2B32

BO0 + E

B01 + F B024 H B03 + J B04* K B05 + L B06 + M B07 + N CTL06+ P CTL07+ R CTL08+ S CTL09+ T CTL10+ U CTL11+ V

(ISOLATORS ON ALL LINES)

0

(SWITCH FILTERS ON ALL LINES)

W021MJ CABLE TO

TEST PANEL 2A30

SBOP

SBO0

SB01 SB0 2 SB03 SB04 SB05 SB06

SE07

[1 - *

n u

n [ ;

-.

FIGURE £36. TEST PANEL CONNECTORS (Page 3 of 3)

-137- i i

i I

a ] o

i

WP21 IBM

CABLE 1A01

!=> W021 FBM

CAuJ.E 1A02

Bl(g-P) ^

D F, H K M P S T V

BI0 BI1 BI2 BI3 BI4 BIS BI6 BI7 BIP

D BO0 E B01 li B02 K B03 M B04 P BOS S B06 T B07 V BOP

FIGURE E35. IBM CABLE CONNECTORS

(Page 1 of 2)

W021 IBM

CABLE 1B01

D E H K M SEI P SELOUT S ADO T CMC V sue

OPI . D

W02i IBM

CABLE IB02

STI , ' E ADI - ' H SRI K

M SELPRP p

• s T V

NOTE: ALL LINES CARRY IBM LOGIC LEVEIS

138-

o U5

o a. O

(N

^ M M ^

_ui{x

S trt h-

=1 tu

^ S « ^ i M "^ ^

CQ

o <-j

4. bfl a a- v—-

to ce o

on H -J U ii LU > z tu z -a o

u U l-H tu u -]

o CQ -3 < u s: 03 S M 00

—1

>" BÄ OJl 4

< LO

U rO UJ

c/. LU 01 z as

I

tu H O

i ? ..;

; [ Li

II

-139-

? ■

-

AR10 +

) (ISOLATORS ON

ON A

ARiU - W021M. _ CABLE

TO TEST

■ PANEL - 2A03

AR12+ AR13 + ALL LINES)

AR14 + AR 15 + AR16+ 1 AR17 + N BR10 + s BR11 + P BR12 + R BR13 + C

BF.14 + T BR15 + U BRlo + V

(UNASSIG iED) D

W;02iM-J CABLE TO

TEST PANEu 2A02

(ISOLATORS

BADI + E BSTI + F i.L LINES) BSRI-- H SPPOP+ J BOPI + K BREI + L BRi7 + M OF.ST+ N ADO + P CMO + R STO* S SEO + T OPO + U SUO + V

I

W021MJ . CAB:.?. TO

TEST 1 PANEL " 2B02 -

*

4 -

PB0 PB1

(ISOLATORS ONLY ON*) (SWI.CH FILTERS ON |)

PB2 PB5 PB4 PBS PB6 PB7 OL! 1

0FLIN+ OLSIV2

0NLIN+

SSEO:

FIGURE E36. TEST PANEL CONNECTORS (Page 1 of 3)

-140-

(SWITCM FILTERS ON ALL LINES)

W021MJ CABLE TO

TEST PANEL 2Bßl

TEST

SADO SCMO

S3R0

SSE02 SOPO

SSUO SW()i SW1 +

:w2 +

SW3 + SW4 +

SW5^ SW6-I

SW7 +

f-

AR20 + D

W(521MJ CABLE TO

TEST PANEL 2A31

AR21 + E AR22 + F AR23 + H AR24 + J AR2S + K AR26 + L AR27* M Stl* N CMDCY* P SRVCY* R CUBSY* S CMDLY+ T CHSRV+ U

(ISOLATORS ON ALL LINES)

BR20 + D BR21* E BR22 + F BR23 + H BR?^ T

BR25* K BR26 + L BR27* M CHNRQ+ N PREND+ P BRKRQ+ R INTR8+ S SKIP* T EACENB u

W021MJ

CABLE TO

TEST PANEL 2A3 2

1

{ISOLATORS ON ALL LINES)

J FIGURE E36. TEST PANEL CONNECTORS (Page 2 of 3) n

n -141-

n !

Ü

r i

n 6MB00- E BMB01- M BK5B02- K BMB03- M B''B03 + P bMB04- S BMB04+ T BMB05- V BMB05+

D BMB06- E BMB06+ H BMB07- K BMB0,' + M BME08- P BML^ä+ S BMB09- T BMB10- V BMBU-

CABLE FROM PDP-8 W02I 3B29

CABLE PDP-8 »021 3A31

CABLE PDP-8 W021 3B31

l CABLE TO

DEVICES W021 3830

PWeCLP BT2A

INV. P107 3B10

PWCLR-

BTi

INV. ^107 3A19

BT2A-

D

IOP4

^

CABLE DEVICES W021 3A32

IOP2

IOP1 BACI1-

BAC10-

BAC09-

INV. R107 3A19

IOP4-

INV. R107 3A19

IOP2-

BMB(3-S)+ BMB(0-5) t>

7> CABLE

DEVICES W021 3B32

BMB(6-8)-!- BMB(6-11) t> CABLE POP-8 Wl<'MCR 1A05

D ADREX1 D CABLE DEVICES W021CR 1A06

E \DREX2 E H ADREX3 H K DF0 K M DPI M P DF2 p

i I FIGURE E34. PDP-8 CABLE CONNECTORS (Page 3 of 3)

" I

-142

PANEL 1 IBM INTERFACE BUSS DRIVEF R01 fl02

1 fl03 fi04 R05 R06 fl07 fi08 fl09 RIO Rll R12 R13 R14 fll5 R16 fll7 F

H021CR HOSlCfl W021CR W021Cfl W021CR H021CR R113 RU3 R107 RUB R107 R123 R123 R123 R123 R123 RIO/ R!

BIO DflOROO OflOROO flOREXl fWRtXl 8610- 8814« •PflRIB PflfilF •BBIO« eeoc d804 6806 6CH0 BQPO .600« •(* m bll r^WROi DftDflOS IWPEX2 «JfiEXZ B8U- sets« PflRIH PHRIH 8810- 8801 3805 8807 63R0 9SU0 800- 8 CNlflOl W1HOI GUIROI »1R01 GNtROI GNlBOl «PWIfl •PflBIE •PflfllD •PflRIK •88!!« ONLIN« XL IN« ONLIN« ONLIN« ONLIN« .601« .8 BI2 B!2 DflOfl02 D«»02 KK.X3 B0REX3 8810* 8816- PflfllC PWIE B8I1- «800- .804- «606- «O«- .OPO- 801- 8 WlflOl GNlfiOl OllflOl GKl«! OHlflOt GNKWl BBI1. 8817- •PflBIF PflRIG •8812« •801- .805- •K)7- «SSO- .suo- .602« .H 813 813 DflCftOS DflOflca DFO OFO •Pfinifl .PfifilG PflfilE •PflRIK 8812- 3800 S804 »06 SCHO« SOPO 802-

■c 5HIHG1 GNIHOI GMIR01 GNIROI GNIR01 GNlROt B8I2- 8616« •PflRlH PflRIJ .8813« S801 5805 S807 SSRO« SSUO .803«

BI4 814 t3(«RQ4 t»0fl04 DFl DFl 8813- 8817« PWIG PflRIL 8813- FLlth OFLIN« OFLIN. OFLIN« OFLIN« 803- 0 GNtROt cm «oi

B!5

«IR01 GNIROI GNlflOl CNIROI ■PRRIC »PfiRIG •PflBIJ •PflRI .8814« .600- .604- ■806- «OM- .OPQ- ■804« .9 815 DflOflOS OflOPOS nF2 0F2 8812« PflRIB Pfiflll Pflfill 8814- ■801- .605- ■807- «SRO- .SUO- B04- 9 GNMOl GNIS01 nmnoi GNIROI GMlROt GNlOOl 8813« PflRID •PfWIL PflRIK .8815« 8802 5802 B80P S80P SSE01 •805« •a ate SIB ofionoe Oflonoe BXJl RXJ1 •PRRIC •PBBII PWIK •PflRI 8815- ma S803 BRDO SROO S5E02 B05- a 817 817 oflmo7 Oflono? KXJ2 BXJ2 B8I4- PflRIfl •PflRI- •8816« ONLIN« OFLIN« ONLIN« OFLIN« OFLIN« ■806« mS UNlROt cmwi Wl«01 GMIROI GMIROI GNIS01 8815- PBRIC PHB1 8816- .602- «832- .60)'- •8CP- .SEO- 806- s 8IP BIP MOfiOS

rmxm RXJ3 RXJ3 «PflfliE •PBBII ' .pna- ■803- «flOO- .flOO- .sro«

B01 B02 603 604 605 606 607 608 609 610 611 612 613 B14 615 616 617 E

W)21CR H021CR W021CR W021CR W990 BO BD BD BD BD BD 80 BO W BR BR BR BF

GN1801

DPI 1 OPI OflOffiM DflOROS LOflOBS .810 ■BI2 ■814 ■816 rtIP ■STI .REt .SELFPP

STI I 3TI ORORIO OflOfllO OflWOS ■8800 ■8802 ■8604 .6806

GNlSO'i 1 GNIBO! GNIBOI GNIBOI OflORtO 8810« B8I2« 8814« 6816« 88 IP« BSTI« BREI« SPROP« POO 602 804 606 »01 flDI OflORU OMJflll OflORU BOGflTE BOGflTE BOGflTE BOGflTE BOGflTE BOGflTE BOGflTE BOGflTE

3N1801 GNlMl GNIBOI GNIBOI HlfiORS

SHI t SRI

GNiBOi wieoi

BRXREQ

' GNIBOI

BRKREQ flOREXl

C5NIB01 R0REX2

SEI SEI XFER XFEP HDREXa BOCflTE STAATE BOGRTE BOGflTE BOGflTE BOWTE BOGflTE

GN1BD1 , GNIBOI

SELOUT SFLPRP

GNiBOi GNIBOI 8811« BBI3« 8815« 8817« 3flOI+ BSfll« 80PI« 601 803 805 807 fl OBKSIfl BRKSIfl .8801 ■680? ■ens •8807 .a

GNIBOI 0N1801 .GNIBOI ^ONlioi

flOO flOQ flCOSCP fOORCP

oe cm MBINCR HBINCR ■611 ■813 ■BIS ■617 ■not ■SRI .OPI . GNIBOI I GNIBOI | GNIBOI GNIBOI

SUO 1 SUO I QRJ ORJ

A.

-142-

RIVERS 316 fll7 R!8

AND fll9 fl20

RECEIVERS R21 R22 fl23 fi. • R25 R26 R27 R28 fr ä fl30 R31 R32

123 B1Ö7 R107 W002 R121 R107 R107 RU3 RUS R113 R107 R107 H501 W501 R107 W02iCR H021CR

CNIMl

WO ■BOO« •807« BOP- •orrsT« rtFTST- mOHLlH* 800» BOB» PflROF rfWOB *8I7» SCHO» SSWK • 800 800 3UO 800- 807- flon- Tt;. OFfST» ONLIH- 801» 807. PWOH PHROfi B8I7- 801 uB0l

NLIN- .Bül. «BOP» sno- OFLIN- •RCfirE« ^0F> JN- •PHBOfl ■PflROO ■PWO« •PflROO *»_!• ^CMO» «CSRO» . GXIR31 : QNlR3t PO- BOl- W MB04 ■OLfl- nOfiTE- f QFllV 800- 306- Pfl«OE PHROC BREI- 802 ! 802 JO- •aos* .«00« W05 OLSHl •CLR» •LOftOBS 801- 807- PflBOC «PflROF •SPROP» j.snvE« »IH31 GNIR31

3PO B02- BOO- MB06 TOBTE» OLR- SELl« H ■PflROft «PHROG »OPHOH PflflOE SPROP- P80S2 P8102 BOPI» 803 803 5UO «B03« ■C«0* «07 «RGATE- ■OLR- •WfiOflS 802» pflRoe PfWOJ •PfiBOH «C0Y2 PB092 Pßl02 .SKIP» Gmfl31 i r*lH3l rLIN* 803- cno- «08 BflEI- OLR* SELl- 803» PflBOO PfIROL PflROC C0T1 P8093 P8103 SKIP- 804 : B04 »0- ■804* «SRO» «09 «»- .flOGflIF «SEO* •PflfiOC .P«0! •FBRO •PWOJ rfOY3 PB093 P8103 •SAVE« GN1R31 ; GNiRSi JO- 804- sno- «10 80PI- ONLIN- SEO- 802- PRRCH PflHOI PflfiOI crr? R00+ 805 805 SEOl .805» •OPO» «11 ■OLH-» •aopflft- .SEO-

SEO*

803- P*OC PBROK •PflBOL .1081. P8091 P8101

SSRO

.BTBRK» m\tai SMIRSI

JE« B05- UPO- OPO- f.SW BOPflB «PWOC «PBHOI •PHBO PflROK 1081- SC«0 BTBHK- 806 806 X1H* «eoe« ■SUOt suo- ^RCflTE^j ■PWCLB* •MLO- 804» 304- BflOI» «PHRO- .4061» PB091 "8101 « _ 807 807 .0- d06- SÜC- LONLI>t- PHCLR- BMLO 80S» 805- CMO» PflflO 4081- SCHO SSRO GM1R31 GNIH31

:o+ OFLIN- •ponoE .PflROE •C0Y1 BOP j flOP j

16 817 818 819 820 821 822 823 824 825 826 827 628 829 830 831 832

BR BR BR BR BR R141 R121 R12I R121 R121 R107 R121 R15I H990 I4021CRIH021CR

»11829 i 1 GM831 rfBtP- •BOPRR ■BBJP» .80882» •CrL04- *8I1- moncm 0X1829^ flofiar- SRO SRO

04 dBOfi •BBOP «BCMO rBSEO rtHLO RRIBI» PRRO- B8IP- 808fl2- BOPRR 4081» SRSTR- BCl- 001F CLO CLO 4 806 m cm SELOUT MLO PRHI- 80P» BCBR1» 4811- iPSIR- 801» ^203F GNIS31 »1831

BR2flI» rtOPflfl •SUOPO •8SRI» «CTLOS- CUBST» «SKIP- 800» 405F MTRO HTRO

PRRI- PRRO SUO- SCCSBI BOPRP 4812- cas«» 600- b07F GMtB31 GhlB31

SR2BI» BOP- OPO- SCCS80 808R2» CUBST» «CIEST 802- 809F MTRI mm PRRI- .SEO- 7SCCS8J .SCC580 *oe«2- 4613- rfaos- 802» H08F GN1931 WIB31

ooet» BSEO SRVCY» SRvcr» BSRI» CUBSY» CMKK4 .001F COOF rer BEI i 807 ROO SRO OPO ^■) PflRI- 8HL0 CHSRV» CMSRV» SRO» 4813- suo» .203F E^F GN1B31 GNlS3t

» •B807 &OB .BSRO «BOPO •8SU0 loei» OPLIM- Bl'V.O» ameo» BOPEO» 1061» SRO» «40SF rpflJ IBRJ

PRBI- ■SEO» ■8R28I» .rafi2 «WST- •fSROT» 4TBRK- 407f GM1B31 GN1831

4081» OPLIH- SCCS8I SRVCT» CTLOO» TDTOT- BRKSTH 409F P«INT PMRINT

PflHI- MLO- SRSTR- BOREO» SRKSTR 40PI- BT1 rfXW HLO MLO MSY» SPSTR- CMSRV» SELl» fQPI» mCOOF

B — GM1831 »1831

PRBI- rfOFF OPO OPO

PRNEL 1 18« INIEhrRCE ... 8US3 OBIVEBS RNO RECEIVERS

I I I I 1 I I I

ß.

I 1

J I i

143-

PANEL <L Ota nDDRESS AND BUFFER REGISTERS HOI fl02 fi03 R04 fl05 fl06 fl07 fl08 fl09 RIO fill R12 R13 R14 R15 Rib R17 R

RELAY H028S H028S WSOl W501 N501 H501 B603 rt205 R205 R205 R205 R205 R205 R205 R205 RH1 Rl'

n 8 C GSODl OOO GH2B17

D W10» COO SHHHl SMBRl SWflJ SH8R2 I0P2- PSHflfll PSHWl PSH«11 PSWWU PSHBRl psweai PSHBRl PSHBRl «SR.flR «RRi

E fWl!» BfCf« «flRlflC- «(»10- •WUl- «Hm2- .flB13- «emo- «ami- «BR12- .BR13- RR10« RRI

F ^.LOUT m\2' 8STI. «SWflRl «SH8RI •swnz «SMBR2 POCWl PDCflRl POCflRl PDCflBl PDCWl POCBRl POCBfll P0CBR1 P0CBR1 RR20- BRJ

H flfllSt Bsnit BflCO^- BBC05- Bflcoe- BflCOV- BflC04- Bacos- OflC06- 8SC07- RfllO- RR

J oaiN- flflU«"1 SPflOP. ' PHCLR- .fifilO» «Wll* •flfii2-» •ffU3* •BRlCh «Bftll« ■BR12* .BR13« flKOt RR<

K HR15* 80PN PB02 PB12 PB22 -*&! swmi SMO- SWl- SH2- SH3- SMO- sm- ac- SH3- flfill» RRI

L ONLIN- RR16« BKI« rpeo2 Pfll2 P822 PB32 0FT5T- swo* SMl- SW2* SW3* SHO+ SWl« 3H2* $H3+ flR21- MS r* «17. 8fll7» PB03 PB13 Pe23 PB33 «PSHBfli PHCRRl PfiCRfll P'Cflftl PBCW1 pflcam PBCBfll PHCBfil PHCBR1 HPU- nnt N OFLJN- 8fll(K OFTST. PB03 FB13 P823 PB33 PSHflfil pstwrn PSHflRl PSHflfll PSWBR1 PSK8fll PSWflfll PSHBRl flR2l« flR2

P KHOl BR11» flOO* •HRM« •fifilS* •flRl6« •flfin« ■BRU< »BfllS« «BR15-» •BR17> flfil

R Bfil?» cno-t P901 PBU PB2' P831 [0P4- •«U- .WIS- •W16- •nnn- •8P14- Umis- .5R16- ■8fll7- GN2R17 <m s arioui am 3. sao« P80 PBl P62 PB3 HPIlftC- BHCOS- BflC09- BflClO- aflcn- Bflcoa- BftC09- BBCIO- BflCU- RRI

T Bfll4« seo< PBOl P8U Pe21 PB31 •FPCHRl SH4- SHS- swe- SOT- SH4- SH5- SW6' SH7- GN2R17 BR2

U SELPflP BfllS* OPO* SM4« SH5-. SH6« SH7- SM4« SHS- SU6« SH7«

V OLR« Bfllfrf suo* PflCflfil PRCBR1 PBCflRl pflcflm PflCBftl PflCWl PRCBRl PflCBRl GN2fll7 QN2

BO; 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 81

N028S W028S R123 H5Ö1 W501 W501 H501 R123 R123 R123 R123 R123 R123 R123 R123 R603 R002 RIO

R B C 0 TBT

SROO

PBO SHCTL JTIPCTL PHCLR- sw<sr PH1(K RRll* fiR12. W13« 800- B06- BRll« Ba2« SHSRI RfllO- .ERCi

E Pfll fiRU» RRIS« BRl6t RR17« 801- 807- 8R15« 806« •OFrsr- BR11- EflCl

F SCNO PB2 OFTST- «SHCTl «IIPCTL •PHCLR- .SHRST fWISC» RRIRC» HfllBC* RRIRC« BQRnt* BORRl« BRinr« 8C»Rl« PSHBRl rtRUO «ERCI

H JjflO P93 •P84 •ERCCH- •ERCOS- •EflCOfe- .EfiC07- .BRIO« .RB16« •EfltOS- .BRt2- 8812- EflCl

J 3S£D2 PB4 «PB£ .ERCOB- •ERC09- •ERCIO- •EflCU- .RRU« •flRl7« .ricog- ■BR16- BR13- .ERCI

K SOFO PB5 P842 P852 P862 PB72 RPIO* RRU» nR12« flHt3« 802- BRIO« 601« 3fll3« I0P4- •BRl-O EflCl

L SSUO rpB6 P847 PBS2 P8C2 PB72 RRMt BRIS» HB16+ HR17« 803- BR14« 805« BR17« BRIRC- 8R14- .ERCI

H 3H0» P87 ÜFTST- Pe43 PB53 PB63 PB73 RRIBI« RfllBI« HR1BI- HR1DI« BORRl« BRIRf« B0BR1« BfllHC» .PRCBRl BRIS- EflCl

N ■Jt * OLSHi ■P66 pe43 PB53 PB63 PB73 .8810- MUi- «8812- «8813- •Hfll2« .ERCOI- .BRU- .EflC07- aBRl-0 «EflCl

p .«2» 0LSH2 •P87 •B8I4- .8315- ■8816- •8817- «HR13« rfRCOB- •8R15- •EflCU- 8R16- EflCl

R SH3* OFLIH. P841 PB51 paei PB71 800« 801« 802« 803« 804- 800« 8R12« 803« [0P4- 8817- .EflCl

s SH4« ONLIHt ^84 l^BS fBS PB7 B04« BOS« 806« 807« 805- 804« BRI6« 807« CTLRC- •Bftl-O EACC

r SHb. sseoi P841 PBSl FS61 PB71 aCHR..* BOWl« BORRt« BORRl« BCRRi« B08RI« 8R1RC« 80BR1« rfBRC «rsTi

u 3H6* ■ r^RlO- •Wll- •flRl2- «PR13- ■RR14« .8R10- «ERCOe- «BRIS-

¥ 3t47* ■ «»',14- rtBlS- ■RR16- #«17- .HR15« •BRi4- rfflCtO- .8R17- « 8R1-

A.

143-

5TERC J

fllb R17 R18 fll9 R20 R21 R22 R23 R24 R25 026 R27 R28 R29 R30 R31 R32

R20S R141 R141 R141 R205 R205 R205 R205 R603 R205 R20S R205 R205 R107 wo2es H02BS H028S

GH2fll7

PSMBfil «BR'flR •flR.fW •AR'fln PSHflra PSWW2 PSM«? PSM«2 I0P2- i3HBfi2 PSHBfi2 PSWB«2 PSWBW? «s«o- SBOP «20. «20*

■BR13- fWlOt fiftl2* IWIS* ««20- *«2l- •«22- ««23- ««2flC- .BR20- <««;- «Bfi22- •Bfi23- SHO. S6O0 «21. «21.

PDC8HI neo- WC2- «25- PDC«2 'pocnre POCWG pocmz P0C«2 PDCBftJ F0CBfl2 P0CBR2 P0CBfl2 «SW1- S801 «22. «22.

«23. BfiC07- HBIO- miz- «15- BflC04- BflTOS- 8flC06- 8fiC07- BHSOI- 8K805- B»«06- BW807- SJl* S802 «23.

■BB13. RP2D« flR22» «ttS« •«20f •«21« •«22. ««23. PWCLR- •BR20. *fi2l. •Bfi?2. •Bfl23. •SH2- Sfl03 «24. 8P24.

>3- flflll» HfilS» «16« SHO- sm- SM2- SH3- SWWC SHO- *t- SH2- SH3- SH2. S804 «25. «25«

3H3» «Wl- BR23- SB26- swu SW1* SH2» 3H3. OFTST- SHO. m* SH2. S«3. .SH3- SB05 «26. «26.

PRCBR1 BRU- »13- «16- PSCW2 PHC«2 PfiC«2 PBC«2 «PSWW2 PMB8fl2 PKBSG PMBBRS PKB8R2 SH3. 3806 «27. ' «27.

PSHBfll fiR2U 0*23* «26« PSH«2 PSM«2 pswwa PSHm2 PSH8H2 pswBna PSHW2 PS«8R2 «S-H4- SB07 sa. CMNRO.

■enn« fifil4» mn* ««24* ■«25. •«26. ««27. «BR24. •fiKS. «8826. «8fi27. SM* cwcr. PfltND.

iBRH- GN2fll7 («24- HR27- ■nR24- ««25- •W26- •«27- I0P4- «SR24- dR25- •«26- ■«27- ■SM5- snvcr. «KTO*

BflCU- flftU- «17- BHCW- BflCOS- BfiClO- 8HCU- «2flC- BMB08- BHBOS- BHBIO- sneu- S«5. cuesr. IN'<«.

SH7- GN2fln W24* «27. SH4- SM5- SH6- SH7- .PflC«2 SH4- SWS- SH6- »r- «SH6- CHDLt. SKIP.

SH7* S«4. ae» SH6. SH7. SH4. SH5. SM6. SH7. SH6. CMSHV. EflCENB

PWBR1 G»(2fll7 GN2nn GN2fln PflC«2 PflC«2 PB-qR2 PflC«2 Pfie8B2 PW8R2 PMBBR2 FNBBfla

B16 B17 B18 819 B20 R21 822 823 824 825 826 827 828 829 830 831 B32

«03 H002 R107 R107 R602 R123 R123 R123 R6Ü3

....

R123 R123 R123 R123 W002 W021CR uo2es wo2es

: GN2B20 GN2B24

1 r~^ SHBRl BB10- 'rfficoo. •EBC06. «20« «21. «23. oHöHc «20. ^ «21. «22. BR23. 800- REQl »IP* BÜP+

OFIST- BBU-, EflCOO- EflC06- I0P2- «24. «25. «27. ■OfTST- «24* BR2S. 8825. «27. 601- SEL1- «10. 800.

PSHBfll •BfTl-O' ̂ •EflCOU «EflC07. «IHC- «2nc. «261. «2flC. PSW«2 SELl« SELL SELL SELL 802- 8811« BOL

Bflt2- EflCOl- EflC07- BO«l- ■ERC04- ■8811- «DK07- ■«04 *B05 ÜrfiGo ■MB07 803- «12. 802.

«13- Ut>X:02. «EflCDB- »2820 «EflCQB- ■«15- •Eflca- ■MB08 *B09 •«10 ■HBll 804- |J8I3. LJE?!__ I0P4- m&M-O E«:02- Eficoa- •POC«! «20. «22- «23. BT2R- BR20. mil* «22. «23* BOS- INTHPT P6I4. ^804.

BBUK- ' «14- •EfiCOS. «EflCOS* PHCLR- «24. «26+ «27. «KST-. BB24. BR2&. i «26. 8827+ B06- 8815. 805.

[»ncwi BB15- ERC03- tBC09- «281. «2RC. ' «281. ■PHBBR2 8R2BI. 88281+ msBi* ^"88281. 807- SUSP «16« 806»

«8R1-0 ■EflC04. «EK10. «aeio- ■Eficoe- •«13- <e:o- «8(1- ■8812- •MI3- BOF- «17« 807.

«16- E«;34- EfClO- BT1- «BBI4- ■EK10- .8817- ^J4- «815- ■8816- ■«n- ^810- CTLOO« CTL06.

fOP4- «17- •EflCOS. «EflCtl» 8«ST- RR21. «22. SUOPO 800. 801+ 802. 803* «14- CTLOL CTL07.

"TLflC- •BPt-O EflCOS- EflCU- mi «25. «26. GWB24 804. 805+ 606. 807. 6615- a 02. f CTLOB.

•BflC «TSTIO- ■SH7- GN2B20 «2HC. PR28I. PMCLR. ■SYSRST 80882. 80882. 80682. B0«2. «16- CTLOS.

CTL04.

CTLIM.

SH7. •P0CBR2 ■EflCOS- «ee.'z- •oocr. «620- «R21- ■6822- ■8823- Mf7- CTUO«

• «1-0 PHCLR- «EflCOO- •8616- ■snvcT. SWST *R?4- •8825- «Bfl26- ■BR27- MIP- TTLOS. CTLU«

f«MEL 2 ... flOOHESS MC BUFFER Ht&ISTERS

ß

-144-

PANEL 3 CONTROL REGISTER AND SEQOENC ROl fl02 P03 fl04 R05 PÜ6 R07 fl08 R09 R10 Rll R12 R13 R!4 R15 R16 R17

W021CR H021CR H021CR H021CR R123 mis R205 R121 R121 R121 R121 R121 R107 R107 B121 R121 R121 R

GNWOl GN3fl07

RCOO «00 «BOO M800 EflCOO« BOSfQ- .CH5BS -BROI* .PRENO- •CTL10- «TSTIOt «RRLBI* .CfllNT- .INTRBt •SROaup '\*f/i%i «i

flCOl flCOl «01 MBT' EftCQl» $6.1» «cw.r- CMDEYt RPIBI- PREW+ «00+ T5TIU- HRIBI- CRINU CRINY- BUH5T. St'OBUB 1

GNSflOt CN»01 OOflOt ' GN3fl01 EflCHO iXFEB 80PI* CNO- HR28I- ?CTL0 SRVCYt ■f, VBI-f •3P3tfl+ 5RINr- SRQ-r BHKRO. '

RCO? «02 MB02 mo2 •RCOO £%ENB GN3fi07 ■CHSRVt mSVßBl- ^crm--1 .CTL10- .CTL07- ,Rfl2BI- SPSTR- .4081- «1081- •UC6 «

GN3H01 OOHOl OöflOl GNWOl •HCOl I0P1 .CHOLY+ RSTCHN CMDUY- PREWK SRVCY« CHO* .808«1» .0081» OOB;« SPSTH* PHCIS-

flC03 fiC03 mo: MB03 £flC02» •EfiCflC- S1VCY* CTL10+ 0P0- 0081+ BOBRl- CHSTR- TSTI0-. rsuo- ZIPCTL i

GNSflO! OGHOl GWjflOl GNSflOl EflCOS» HOENB» •SOSfll- «RRIBI- •CILU- «CTLiO- ■CTLOS- ■«OfiC- .CflNRQ» «CMSTR- .SPSTfi- .003 .! fiC04 flCO« «B04 «04 EflCHO lOPl CDT3 Bffll. CMDCY. PRENO» 3RVCT» 008U HOOfiCP CLRCR» CROCY« CMOCY* SYSRST 1

wafloi semi GN3fl01 &smi •flcoa •EfltftC- DlSRS CMOt flOQ- STO* BSRI» SfiOt •PRENn» .CYCSEL SRVCY- SRVCYf PWCLR- I 1

BCOS «OS W05 «05 •«03 81*5 r« «CHSfiVt CMOCY* CMOLY- SIVCY-. CHO+ mio- PRENO- SELl» CMSRV» CH5RV» Z1PCTL 1

aofioi Of«0l »OBOl GNSflOl EflC04' BflWQ« •CHSPV- ■SBHR •swpa- •CTLU- «PREKS3- •CTL08- «BOENB« •StLl« .SRSIR- .BSTIt «DCO M

HCOb BCOS «06 «06 EfCOSt •BURBK- SBMP SR1MT- SHO» BTBRH+ WKr» ROE« SEU- CROCY- CHSIfl- SYSR5T ( flC07 flC07 «07 «07 EflCflO BUPBK-j Gti3fi07 BflKSTfl FREIC- BOREO-f SELlt «M» •EHCHC» «BOP1- SRVCYt SRSTR- PWCLR- ( GN3ffi)l OOflOl GN38Q1 G»(3fl01 •KL04 80PU sat* SttVCYt SELL WC=Q SEO- EHCBC- BOPU CMSRVt SP5TR- CTLO?-

HCOB flC08 MB08 «08 •BCOS «RSTCMN BT2f>- SBVCY* SfttNT- PRENO-r SIREQ» CUR5Y- ZIPCTL

B01 B02 B03 B04 B05 BOB BÖ7 BOB B09 B10 Bll B12 B13 B14 B15 B16 B17

W021CR H021CR H021CR H021CR R123 1

B121 ROOl Rill R121 R107 R121 R121 R107 Rill ROOl R205 R205 fl

GNJBOl »(3817

RC09 acos «09 HB03 EHC06+ röOPI. BOFRR- OPO* tfROPS •OURflOt .OURCM; .0URCM4 .CU85Y» CHDCY» CHNRQ» PBRC PBRC

HCIO fiCIO r«io «10 ERC07. CW3CY- tfXTHOO WO» PROP I OUBRO- CRINT» CKJRCMS CUBSY- RR.RR •CSRC «CTLOQ- .cao?- • (

0*3801 0(3801 oraeoi GN3801 ERCflC« SfiVCY- RDHDT. EXTHOO PH0P2 »SEL. OlIRROt SEL» .BORRl» CSRC STREQ» ZCTCO PHCIR-

BCll RCU «n «li .RC06 .CTLSKP «EXISOC «OURRO- •mm 3EL- .oijRCns .SRVCY- BORfll- .SRVCY- .CSRC SHO- SW2-

ooao: O08ÖI OiSBOl Oi3801 •BCO^ 5«PENB BOKl- OURRD- PRWS .PMCIR- ouRcm SEL» •CHOCY» ftR=BR BRD!» .CTLOO» «CIL.32» .( SW SKIP CYCSEL CYCSEL EflCOB-. CTUC- .EXTHOO OPO» 5E0» PWCtH CUBSY- SRVENB R5TCM0 INTR8» «CSRC BRCOO- BfiCQ2-

GN3B01 GN3801 ÜNjBOl , ocieoi Eflcoa» .PROPl OISHflL HOO- .3EL- . •CUB5Y- iCHOCYt .CfffiCY- CRO» BRCOO- BHC02-

INTRPT iNTRpr «'1 ' «ji EfKRC- BREI- rfXTfCO

CHNRS*

F'TRES PROPi (mm BORRl- CROCY» .CSRC 5WCTL SHCU

»380! r GH3801 Oi3B01 Ghmi «flCOS ffJP,«)- .8F. I- sto* .zcno SELt CHOCY- .SRVCY» .r-TRPT SYCVCO PBRC ROORC-

HCCLR f£CLR «-0 w ■RCOO SEL- .EXTREU BREI PROP? OCO 0URCR4 SRVCY- CMO- «SYCVCl .CTLOl» .BRKRS» «( LWB01 OfSBOl Ofieoi 0(3301

«J2

tfiClOt .EflCErS 80PI- I0P2 8 p' OP- •rCTLS .0URCM3 •BORRl- •SRVCY- SRiNT- SYCVCO .CTL01- ■BRHRQ- . RUN RUN «J2 EflCU* RfllHC- .EXTREQ RCTE3T SEO. 0C3 mflc« CL8SY- SRVCY» BURBRK «CTL02» SHl- GN3B17

RCJ1 fiCJ! «J3 «J3 ERCRC« UfllflC- CTLStSP CTLSK1 PHOf'3 •KTL6 CIURCM4 OURRD» «SRVC»» ' SYCVC1 ZCTLO BHC01- ( GN3801 OO601 GN3801 0(3801 .RCIO RR2flc- «caa^i .SKIP SEL- ÜC6 0UBCR3 R5TSRV «RSTSPV .CTL02» BRC01- SELS-

RCJ2 BCJ2 «J4 «J4 •RCU CTLRC- SEL!- BOPI- SEL» RSISRV sw;rL 1 CTL00- !

A.

-144

SE fll5

R!21

QÜE

fll6 R17

1

fli8

^fllING Q19 R20 R21 fl22 R23 fl24 fl25 R26 fl27 R28 R29 R30 R31 R32

R12J BUI R121 R107 R121 R121 H1S1 RU3 R107 R123 RJ4I PI07 —4

W02ICR W021CR W021CR W021CR W021CR

[_ __ _1_

I W3q28 G»Ofi2? 0N3H26

iINTRS* »SROBUB «HEQl rfSTCKO «BTJfl- «5RINTt •IMNHU. »3fl22 BORl •BQREC- en 30. #CTEST ^ROO» ERCOO- BflCOO- BRCOO- BHBOO- SfBcn-

CHINT- BURST* Sfloa* OIIWT- BT^fl CTLIO- SfiVCY» CTLOl- BOR2 B0BE9. CTLGl' BRCOO* 8«:oo- ERCQl- BRC01- j BRCOl- 3M301- j BWOl-

SfilNI- SROt SRHR«- StCC rtn- CTLU- SRO« CTLOI» rfOPEQ* « cnflc* tHCOO- ■BRCOl» 0!3fl2B W3B2fl j W3R28 | »i3R28 : 9r&& 1408!- •toei- .OC6 j.StCC 811 «BUBBHK •aRCR» CTLWH 8IR1 •EHCOO- BRtOl« 6Hr.0l- EflC02- BSCOZ- i 8flC02- 3*802- R«02-

i_Ci»l3fl2?i oot:* s'srftr PHCLR- I SRO* «I0P4- BUR5T- f PHLLH- cnoo- BIH2 «BURSI- «tflCOl- FRC01- «BRCO?- »J3fl28 0N3R28 | GH3R28 I G»l3fl2«

rsnot rsno- JlPtn i CNOCY» I0P4 BRKRa« cruo- CTLO?- «8IREQ» 1 BURST» CTL02.

CTL03.

BRCOa» eao?- ERC03- ! BflC03- | 8RC02- BHB03» j Bf803. iCMSTS- .5r5TM- •OC3 !«Sctt •japs- i.SYcvca .8K830 CTLOi» STR1 «RRIRC» E,RC02- #«;03. »I3H28 GM3R28 | »ones G*i3R2e 'A )<v»

CHOCT» CMOCT- STSRSr CHOCY-. lQf>2 SRVCY» BM803- • STR^ HRIRC- CTLRC- BRC03. dflC03- ERC04- BRC04- i BftC04- BM803- ; 8H803-

S8VCT- SftVCYt PHCLR- j CtiSRVf oSRlNi- CMSRVt a«B04» ■ «STIKö» iBRlRCf ■eflco?- ERcoa- ri;BC04. GN3R2« 0K-3R2B j GW3fl2« »I3ft28 4 »3fl28

CHiRVt CMSRV» ripen wot SRJNU cm* BUfiQS» «BOR1 STB2 BR1HC- rflRCOJ- BRC04» 8HC04- ERC05- BRCOS- BflCOf.- BHB04» 6*834»

s«srH- •BSTI« •oro «sccc •CTLOZt •CHINI» •SBM ■BORS SUO« •RfiZRC» CTL04-. OiC04- •BflCOS- 0N3R28 (>J3«2e ÖN3R?8 GNSflae ; W3fl28

CflOCY- CM3T«- SYSRST CHOCYt SRIMT^ CIL06- 3HWT- ■8IR1 «OISROL HRiHC- CTLOS- BRC05. BRC05- Eflcoe- 8flC06- | 8flC06- Bt»B04- 1 8*804-

"»UCYt SRSTB- PWCLR- OPQ- «CtLO?- CTL07- BBKSTfl .8 IP? HÖH? «CTLRC» CTlflO ERC05- rfflcoe* LEflC07- BRC07- BflC07- 8*805- ■ B*805»

CHSRV» SPSTS- CTLOZ- suo» ClLOZi- CTL08- SSL1. •STR1 BIR2 CILRC- ■£804- W3H26 | BSC06- »ISflJfl 0N3H28 C*3B2» Gh-3R2e rJ^.^a^s

srwo* CUBST- ZIPCTL CU09- SRVCY- •5TR2 •BURST. rfÄTOS-

^_ ERCOB- BRIOS ; BSCO«- BPB05- j B*BOS-

815 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 831 B32

001 R205 R205 RI'OS H205 R205 R20S R205 R151 H002 R123 ru4i RIO? W021CR K021tRin02iCR |

K021CR|H021CR

QN3B17 CN3B18 0N3826 »3323

::HNRat PBRC PBRC PBRC PlJflC PBRC PBRC PBRC BHB30 ERCOO- CIL06» rfCTFST *PC07. tRC03- BflCQ9- BRCJO- 8*806» 8*80E»

^RC •CTIOO- •CTI.Q2- .CTL06» «CIL03- »CTL05- «CTL08- •CTL 10- BM807- tRCOl- CTL07» BflC06» BflC07- ERCiO- BRCIO- BNUO- 1 3*B06- R^BiJS-

tTREO» ?CTLO PHCLR- SYSRST ZCTL3 ?CTL3 KTL3 ?CTL3 B11B07» EflC02- CTlflC» ERCOfc- .SRC08* W362« 0N3B28 : »3828 i 00628 0»3928 :SflC SHO- SH2- GN3818 ^BRaoe» ERC03 rfRC06- 8«:07» BRCOB- ERCll- BRUi j afli.ll- i 3*607» B*S07»

»01» «CTLOO-» .CTL02» iCTlOb- •CTL03» «CTLOS» •CTLOe» •CTL10» BHB06- ERC04- •£flC07- EflC07- rfRC09. OI3828 aoses ; am» »3B2« : GK3629 1

^RC BRCOO- 8flC02- 8RC06- BRCOS- BRCOS- BHCC8- BRCIO- B^BOfi- ERC05- ' CTL06» BRCOa» 8flC09- i RDENB wi | topi 3*857- »!997-

w BRCOO-^ BRCO?- BRCOb 8fC03- , BRCOS- BfltOS- BRCIO- 8*808+ EflC06- CTl 09» ERCOB- rfflCIO» <X3b28 GN3B2R ; »382« »3828 , »3S28

SRC ^ ÄCTL SHCTL wcn.6 »RRIRC- IHC01- CTLRC» BRC09. SRC 10- SXPENB I»»? : 10P2 3*808» 3*838»

7CVC0 PBRC ROORC- BORf> I"PMC PBRC PBRL PBRC .8R1RC- ERC08- rfflCOB- EflCÖ9- •SflCll» »382« »3828 j »3828 »3928 »3828

■yuc\ »CTLGl» «BRKRQ» •CHNBQ. «CTl 04» «CTLO?» «CTL09» •tTLll» .flR2RC- ERC09- rfflcog- BRCIO. BRC11- I0P4 i lOPi 8*808- ■ 8*858- revco «CTLOl- •BRKRO- .CHNRO- .CTL04- •CTL07- •CTL09- «CTLU- •CTLRC- EBC10- CTLlO» EHC10- •I0P2- GN3828 »3828 »3828 »3828 ; »3828

tLO?» sn- MSBH SBh • EHC11- CTL11* BHCll» j I0P2 BT1 BU x B*B09- : 8*809-

CTLO BflPi'- »3818 BflC04- BfiCO?- BflC09- BRCll- « HCTEST CTLRC» ERCU- .iaP4- 3T2R BT2R 6*810- t 8*B1Q-

TL02» BHCOl- SEL1- 6flC04- BflC07- BaC09- BRCll | R0EN8 •ERCIO- h0N3B26 !0P4 0.3828 »3628 »3828 1 »3828 »3828

. SHCTL CTLOO- BT2ft- • SKPENB *flCU- PMRCl« PHRCLR [sRBll- i 8*811

PANEL 3 ... COHTRCl REOISIER HkD SFOUEKCf CATINC

B.

r r r

n APPENDIX F

MAINTENANCE AND DIAGNOSTIC FACILITIES

r i

i

D 1 D i f

I i

u

'1 hAINTENANCE AND DIACNOSTIC FACILITIES

FI. Tho Test Panel

1

.;

:

T..e Syst.em/36ü interface contains facilities for

seif-checking during its operation and for diagnosing circuit

faults. Maintenance operations can be carried out both on-

and off-line using built-in test controls and indicators.

Precipitous fault conditions can be detected with conventional

perturbation methods using the margin-check power supply of

the PDP-8. The principal test component is the Test Panel,

shown in Figure Fl. The top two rows of indicators on the

left on this panel monitor the contents of the four principal

data registers of the interface: AR1, AR2, BR1 , and BR2.

The next two rows of indicators monitor the status of the

channel interface tag lines and bus lines. The upper row

of these monitors information placed by the interface on the

inbound lines to the channel; the lower row moritors informa-

tion placed by the channel on the outbound lines to the inter-

face. Beneath these indicators is a row of switches used to

simulate the outbound lines in off-line operation. The large

pushbutton at the extreme lower right controls the on/off-

line status of the interface. None of the test controls are

operable when this switch in the on-line position, although

the various indicators continue to monitor the state of the

circuitry. When the equipment is in the off-line or test

condition the signals to the channel lines are deactivated

in such a way that servicing operations and power up/down

sequencing can be conducted without in any way affecting the

operations by the channel with other control units. To the

right of the block of indicators just described is a block

of 24 indicators which monitor the status of mos': of the

control flip-flops of the interface. These can be roughly

grouped as follows: If one of the top row of indicators is

lit, then the interface is actively communicating with the

-147-

148-

o >■ <

LU

<

00

l I

I

i

P

f i | |

-

1 J

1 1

ü u

149-

channel. During various parts of a channel - interface opera-

tion, the next row of indicator;', may be lit. A service

cycle (data or status} will result in alternate operation

of the CH" REQ and BRK REQ indicators. The last two rows

of indicators represent the contents of the CTL icgister

exactly as indicated to the resident PDP-8 program.

] 11

F2. Diagnostic Procedures

In rormal system operations the interface is on-

line to the System/3'. J as indicated by the illuminated push-

button swtch at the lower right of the test panel. Alter-

nate deprcsinns of this pushbutton s:itch the interface

fren the on-line, to the off-line state and vice versa. In

the cff-line st.te the interface is logically disconnected

from the Sys'cem/36ü channel - cont rol unit lines and may be

tf-'ted independently of the System/360 using the manual

ontrols on the test panel ar.l certain PDP-S test programs

constructed for this purpose and described below.

In some situations it is desirable to activate

the manual controls on the test panel when the interface

is on-line to the Systeni/360. A special override switch

(TEST) is provided fvT this purpose. The lamp above this

switch indicates, when lit, that the manual controls are

operat ive.

The interface contains special circuitry which

prevents transitions to and from the on-line state when

channel operations are pending at the interface. There-

fore servicing operations involving such transitions can

proceed without disturbing the System/360. Following is a

description v-. diagnostic utilities intended to ferret out

most component failures.

360 INTERFACE REGISlcR TUST

Purpose

Program tests ARI, BR1, AR2, and CTL gating with

the AC, aad in addition tests BR2 gating with the MB. Read,

Clear, and Write operations are tested with ARI. BR1, and

AR2. Read, test-under-mask and invert under-mask operations

are tested with CTL. The interrupt facility is tested in

ccijunction with CTL; and the 3-cycle data break facility

is tested in conjunction with BR2.

DIRECTIONS FOR USE

a. Switch interface off-line.

b. START program at 200. Program will stop at 214.

c. Using manual controls, loaii all ones (577 octal) ir.to

ARI, BR1, and AR2. Press CONTINUE.

d. Program will loop through all tests in about 3 seconds

Error stops are documented in program listing.

360 INTERFACE ECHO TEST

Purpose

Program tests all channel interface circuitry

except bus drivers, receivers and on-line/off-line circuitry.

Channel interface sequencer are simulated with the manual

controls.

DIRECTIONS FOR USE

a.

b.

Switch interface off-line. Raise OPL OUT and BUS OUT

(P) swi iches.

Load program. START at 0200. Lower SR switches.

Program will loop.

System Reset, Lower OPL OUT switch. Program will stop

at 221. AC will contain 0040 and SYS RST lamp will be

on in CTL. Raise OPL OUT; press CONTINUE.

-150-

-151

/5YSTEM/360 IN'TERFACE DIAGNOSTIC ROUTINES PAGE 1 /

/* * /a SYSTEM/360 INTERFACE DIAGNOSTIC ROUTINES * /* «

/ /INTERFACE REGISTER DEFINITIONS / RD=1 /IÜP READ CLR=2 /IÜP CLEAR TST=2 /IOP TFST WR=4 /lOP WRITE 1NV-4 /IOP INVERT ARl=630Ö /ADDRESS REGISTER 1 BR1=6310 /BUFFER REGISTER 1 AR2=6320 /ADDRESS REGISTER 2 CTL=6330 /CONTROL REGISTER / /INTERFACE CONTROL REGISTER BIT DEFINITIONS

STREQ=7000 BIREQ=<.000 BÜRE0=2000 CMOCHN-OAOO CM0PCK=0200 SRVPCK=0100 CM0RST=0040 CMDSTK=0020 CM0HLT=0010 CM0EN0=0004 SRVHLT=0002 SRVEND^OOOl / /SYS7EM/360 STATUS BYTE / UNCHCK=002 DEVEN0=G04 CHNEN0=010 / *1 /

OOOl 5^20 JMP I INTRPT BR2BLK,*.f2 / *10 AXRl, *.+l / *20

0020 0100 INTRPT,INTX 0021 0001 BR20BP,BR2BLK-1 0022 0035 BR2CA, TMP3-1 0023 0002 XSRHLT,SRVHLT 002A 2000 XBOREO.BOREO 0025 ^000 XBIRE0,BIRE0 0026 0377 K0377, 0377 0027 0777 ;0777, 0777 0030 7000 K7000, 7000 0031 7400 K7400, 7400

/STATUS REQUEST /BUS-INBOUND SERVICE REQUEST /BUS-OUTBOUND SERVICE REOUEST /COMMAND CHAIN 'BUS-OUT PARITY CHECK ON COMMAND BYT 'BUS~OUT PARITY CHECK ON DATA BYTE /SYSTEM OR SELECTIVE RESET /STACK STATUS ON INITIAL SELECTION /HALT I/O /COMMAND ACCEPT /SERVICE STOP /PDP-8 WC=0

DEFINITIONS

/02 UNIT CHECK /GA DEVICE END /Oft CHANNEL END

]S2-

/SYSTEM/360 INTERFACE DIAGNOSTIC ROUTINES

0032 7767 K776.■', 7767 0033 7772 K7772, 7772

TMP1, ♦.+! TMP2, *.+! TMP3, *.+! AC, *.+l / «100 / / /INTERRUPT ROUTINE /

0100 3037 INTX, DCA AC 0101 6042 TCF 0102 603i: KCC 0103 6331 CTL RD 0104 0027 AND K0777 0105 7640 SZA CLA 0106 2000 ISZ 0 0107 1037 TAD AC 0110 5400 JMP I 0

/START USING START KEY / *200 / /TEST AR1, BR1, AR2 REGISTERS / START, AR1 RD

SZA

PAGE

0200 0201 0202 0203 0204 0205 0206 0207 0210 0211 0212 0213 0214

6301 74^0 7402 7200 6311 7440 7402 7200 6321 "'440 7402 7200 7402

HLT CLA BR1 RD SZA HLT CLA AR2 RD SZA HLT CLA HIT

/AR1-AC GATES PICKED UP A BIT (AC»

/BRl-AC GATES PICKED UP A BIT (AC)

/BR2-AC GATES FAILED A BIT (AC)

/OPERATOR ACTION PAUSE

/LOAD ONES INTO AR1, BR1, AND BR2 USING MANUAL /CONTROLS. RESTART USING CONTINUE KEY /

/AR1-AC GATES DROPPED A BIT (AC)

0215 10:;1 AR1T1, TAD K740C 02'6 6301 AR1 RD 0217 7040 CMA 0220 7440 SZA 0221 7402 HLT 0222 7200 CLA 0223 6302 AR1 CLR 02 2 A 6301 AR1 RD 0225 7440 SZA 0226 7402 HLT 0227 7240 STA 0230 6304 AR1 MR 0231 0031 AND K7400

/CLEAR API GATES FAILED A BIT (AC)

ml

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-153-

/SYSTEM/360 INTERFACE DIAGNOSTIC ROUTINES /

•AGE

0232 6301 AR1 RO 0233 7040 CMA 023<» 7440 SZA 0235 7402 HIT 0236 7200 CLA 0237 6304 AR1 WR 02M) 1031 TAD K7400 0241 6301 AR1 RD 0^2 7040 CMA 0243 7440 SZA 0244 7402 HLT 0245 7200 CLA

/ BR1T1, TAD K7400 0246 1031

0247 6311 BR1 RD 0250 7040 CMA 0251 7440 SZA 0252 7402 HLT 0253 7200 CLA 0254 6312 BR1 CLR 0255 6311 BR1 RD 0256 7440 SZA 0257 7402 HLT 0260 7240 STA 0261 6314 6R1 WR 0262 0031 AND K7400 0263 6311 BR1 RD 0264 7040 CMA 0265 7440 SZA 0266 7402 HLT 0267 7200 CLA 0270 6314 BR1 WR 0271 1031 IAO K7400 0272 6311 BR1 RO 0273 7040 CMA 0274 7440 SZA 0275 7402 HLT 027 6 7200 CLA

/ AR2T1, TAD K74Ü0 0277 J031

0300 6321 AR2 RD 0301 7040 CMA 0302 7440 SZA 0303 7402 HLT 0304 7200 CLA 0305 6322 AR2 CLR 0306 6321 AR2 RD 0307 7440 SZA 031C 7402 HLT 0311 7240 STA 0312 6324 AR2 WR 0313 0031 AND X7400 0314 6321 AR2 RO 0315 7040 CMA 0316 7440 SZA 0317 7402 HLT 0320 7200 CLA 0321 6324 AR2 WR

/AC-AR1 GATES DROPPED A BIT <AC»

/AC-AR1 GTES INVERTED A BIT (AC)

/BR1-AC GATES DROPPED \ BIT ,AC)

/CLEAK BRl GATES FAILED A BIT (AC)

/AC-BR1 GATES DROPPED A BIT (AC)

/AC-BR1 GATES INVERTED A BIT (AC)

/AR2-AC GATES DROPPED A BIT (AC»

/CLEAR AR2 GATES FAILED A BIT (AC)

/AC-AR2 GATES DROPPED A BIT (AC)

-154-

/SYSTeM/360 INTERFACE DIAGNOSTIC ROUTINES PAGE 0322 1031 TAD K7400 0323 6321 AP2 RD 0324 7040 CMA 032S 7^0 SZA 0326 7402 HLT 0327 7200

/ CLA

0330 5731 JMP I .+1 0331 0400

I «400

AR1T2

/ /TEST / AR1T2

AR1, BR1, Al

0400 3034 , DCA TMPJ 0401 1034 TAO TMP1 0402 6306 AR1 CLR+WR 0403 0031 AND K7400 0404 6301 AR1 RO 0405 3035 OCA TMP2 0406 1035 TAD TMP2 0407 7040 CMA 0410 0034 AND TMP1 0411 7440 SZA 0412 7402 HLT 0413 7200 CLA 0414 1034 TAO TMP1 0415 7040 CMA 0416 0035 AND TMP2 0417 7440 SZA 0420 7402 HLT 0421 7200 CLA 0422 2034 ISZ TMRl 0413 5201

/ BR1T2,

JMP AR1T2+1

0424 3034 OCA TMP1 0425 103A TAD TMP1

1 0426 6316 SRI CLR+WR 0427 0031 AND K7400 0430 6311 BR1 RD

1 0431 3035 OCA TMP2 0432 1035 TAD TMP2 0433 7040 CMA 0434 0034 AND TMP1 0435 7440 SZA 0436 7402 HIT 0437 7200 CLA 0440 1034 TAO TMP1 0441 7040 CMA 0442 0035 AND TMP2 0443 7440 SZA 0444 7402 HLT 0445 7200 CLA 044 6 2054 ISZ TMP1 0447 5225

I AR2T2,

JMP BR1T2-».

0450 3034 DCA TMP1 0451 1034 TAO TMP1

/AC-AR2 GATES INVERTED A BIT (AC)

AR2 REGISTERS

/AR1 ECHO OROPPEn A BIT (AC)

/AR1 ECHO PICKED UP A BIT (AC)

I 1 I I

/BR1 ECHO DROPPED A BIT (AC)

/BRl ECHO PICKED UP A BIT (AC) rf Si

w

n U

155-

/SYSTEM/360 INTERFACE DIAGNOSTIC ROUTINES /

OA5? 6326 AR2 CLR+WR 0453 0031 AND K7400 0454 6321 AR2 RD 0455 3035 OCA TMP2 0456 1035 TAD TMP2 0457 7040 CMA 0460 0034 AND TMP1 0461 7440 SZA 0462 7402 HLT 0463 7200 CLA 0464 1034 TAD TMP1 0465 7040 CMA 0466 0035 AND TMP2 0467 7440 SZA 0470 7402 HLT 0471 7200 CLA 0472 2034 ISZ TMP1 0473 5251 JMP AR2T2+1

PAGE

/AR2 ECHO DROPPED A BIT (AC)

/AR2 ECHO PICKED UP A BIT (AC)

0474 5675 0475 0600

0600 0601 0602 0603 0604 0605 0606 0607 0610 0611 0612 0613 0614 0615 0616 0617 0620 0621 0622 0623

0624 0625 0626 0627 0630 0631 0632 0633 0634 0635 0636

6331 7440 7402 7200 1027 6334 7200 1030 6331 7040 7440 7402 7200 1027 6334 7200 6331 7440 7402 7200

3034 1034 6334 7200 6331 3035 1035 7040 0034 7440 7402

JMP I .+1 CTLT1

/ *600 / /TEST CONTROL REGISTER GATING / CTLT1, CTL RO

SZA HLT CLA TAD K0777 CTL INV CLA TAD K7000 CTL RD CMA SZA HLT CLA TAD K0777 CTL INV CLA CTL RO SZA HLT CLA

CTLT2f DCA TMPi TAD TMPI CTL INV CLA CTL RD DCA TMP2 TAD TMP2 CMA AND TMPI SZA HLT

/CTL-AC GATES PICKED UP A BIT (AC)

/CTL-AC GATES DROPPED A BIT (AC)

/CTL FAILED TO INVERT A BIT (AC)

/CTL ECHO DROPPED A HIT (AC)

-156-

/SYSTEM/360 IfTERFACE DIAGNOSTIC ROUTINES PAGE

0637 7200 CLA 0640 1034 TAD TM> C641 7040 CMA 06A2 0G35 AND TMP2 0643 7440 S2A 0644 7402 HLT 0645 7200 CI.A 064 6 1034 TAD TMP1 0647 6334 CTL INV 0650 7200 CLA 0651 6331 CTL RO 0652 7440 SZA 0653 7402 HLT 0654 7200 CLA 0655 1034 TAD TMPl 0656 7001 I AC 0657 0027 AND K, 777 0 660 7440 SZA 0661 5224

/ CTLT3,

JMP CTLT2

0662 1032 TAD K7767 0663 3034 OCA TMPl 0664 7120 STL 0665 6334 CTLT3Ü tCTL INV 0666 6232 CTL TST 0667 7402 HLT 0670 7040 CMA 0671 6332 CTL TS: 0672 7410 SKP 0673 7402 HLT 0674 7040 CMA 0675 6334 CTL INV 0676 7004 RAL 0677 2034 ISZ TMPl 0700 5265 JMP CTLT3A 0701 7200

1 CTLT4,

CLA

0702 3034 OCA TMPl 0703 1034 TAD TMPl 0704 6334 CTL INV 0705 7200 CLA 0706 3035 CTL4C, OCA THP2 0707 1035 TAD TMP2 0710 0034 AND TMPl 0711 7041 CIA 0712 1035 TAD TMP2 0713 7640 SZA CLA 0714 5321 JMP CTL4A 0715 1035 TAD TMP2 0716 6332 CTL TST 0717 7402 HLT 0720 5325

/ CTL4A,

JMP CTL4B

0721 1035 TAD TMP2 0722 6332 CTL TST 0723 7410 SKP 0724 7^02 HLT 0725 7001 CTI 4B, I AC

/CTL ECHO PICKED UP A BIT (AC)

/CTL FAILED TO INVERT A BIT (AC)

/CTL TST FAILED TJ SKIP

/CTL TST SKIPPED IN ERROR

1

/CTL TST FAILED TO SKIP

/CTL TST SKIPPED IN fc■ ^R

«I 5 I

11

-157-

/SYST6M/360 INTER J

0726 7440 i

SZA 0727 5 306 JMP CTL4C 0730 6335 CTL RD+INV 0731 7104 CLL RAL 0732 0027 AND K0777 0733 7440 SZA 073^ 530^

1 CTLT5

JMP CTLT4

0735 1033 . TAD K7772 0736 3035 DC A TMP2 0737 7120 STL 0740 7004 CTLT5A.RAI 0741 6334 CTL INV 0742 6001 ION 0743 7000 NOP 0744 7402 HLT 0745 6334 CTL INV 0746 6001 ION 0747 7000 NOP 0750 7410 SKP 0751 7402 HLT 0752 6002 IOF 0753 2035 ISZ TMP2 0754 5340 JMP CTLT5A 0755 7200 CLA

0756 5757 /

JMP 1 . + 1 0757 1000

/ «1000 / /TEST / BR2T1,

BR2T1

BR2 AND DATA

1000 3034 DC A TMPl 1001 1034 TAD TMP1 1002 3036 OCA TMP3 1003 1021 TAO BR'DBP 1004 3010 DC A AXR1 1005 7240 STA 1006 3410 OCA I AXR1 1007 1022 TAD BR2CA 1010 3410 DC A I AXR1 ion 1025 TAO X6IR50 1012 6334 CTL INV 1013 7200 CLA 1014 3035 OCA TMP2 1015 1021 BR2T1E ,TAO BR20BP 1016 3010 DC A 4XR1 1017 1410 TAO I AXR1 1020 7650 SNA < ",LA 1021 5225 JMP 3R2T1A 1022 2035 ISZ rMP2 1023 5215 JMP JR2TIE 1024 7402 HLT 1025 1022 BR2TIA »TAD i 5R2CA 1026 7040 CMA 1027 1410 TAD I AXR1 1030 7440 SZA

PAGE

/CTL FAILED TO INTERRUPT

/CTL INTERRUPTED IN ERROR

/DB WORD COUNT FAILED TO DECREMENT

-158.

/SYSTEM. 360 INTERFACE DIAGNOSTIC ROUUNES PAGE

1031 7402 HLT 1032 7200 CLA 1033 103* TAD TMP1 1Ü3A 7041 CIA 1035 1036 TAD TMP3 1036 7440 SZA 1037 7402 HLT 1040 7200 CLA 1041 1023 TAD XSRHLT 1042 6335 CTL RD+INV 1043 7200 CLA 1044 6335 CTL RD+INV 1045 7200 CLA 1046 3036 DC A TMP3 1047 1021 TAD BR2DBP 1050 3010 DC A AXR1 1051 7240 STA 1052 3410 OCA I AXR1 1053 1022 TAD 8R2CA 1054 3410 DC A I AXR1 1055 1024 TAD XBOREO 1056 6334 CTL INV 1057 1025 TAD XBIRED 1060 6334 CTL INV 1061 633f CTL INV 1062 7200 CLA 1063 3035 OCA TMP2 1064 1021 0R2TlDtTA0 BR20BP 1065 3010 DC A AXR1 1066 1410 TAD I AXR1 1067 7650 SNA CLA 1070 5274 JMP BR2T1C 1071 2035 ISZ TMP2 1072 5264 JMP BR2T1D 1073 7402 HLT 1074 1022 BR2T1C,TA0 BR2CA 1075 7040 CMA 1076 1410 TAD I AXR1 1077 7440 SZA 1100 7402 HLT 1101 7300 CLA 1102 1023 TAD XSRHLT 1103 6335 CTL RD+INV 1104 7200 CLA 1105 6335 CTL RD+INV 1106 7200 CLA 1107 1036 TAD TMP3 1110 0031 AND K7400 Uli 7440 SZA 1112 7402 HLT 1113 7200 CLA 1114 1034 TAD TMP1 1115 0031 AND K7400 1116 1036 TAD TMP3 1117 3036 DCA TMP3 1120 1034 TAD TMP1 1121 7040 CMA 1122 0036 AND TMP3

/OB CURRENT ADDRESS FAILED TO INCREM

/DB TRANSFER DIRECTION SENSE WRONG

/(RATHER UNORTHODOX SEQUENCE)

/DB WORD COUNT FAILED TO DECREMENT

/DB CURRENT ADDRESS FAILED TO INCREM

/DB PICKED UP BITS Iiv! POS 0-3

159-

/SYSTEM/360 INTERFACE DIAGNOSTIC ROUTINES

/BR2 ECHO FAILED

PAGE

1123 7440 SZA 112^ 7402 HLT 1125 7200 CLA 1126 1036 TAD TMP3 1127 7040 CMA 1130 0034 AND TMP1 1131 7440 SZA 1132 7402 HIT 1133 7200 CLA 1134 2034 ISZ TMP1 1135 5201

5737

JMP BR2T1+1

1136 JMP I „+1 1137 0215

/ 0037

AR1T1

AC AR1 6300 ARIT1 0215 AR1T2 0400 ÄR2 6320 AR2T1 0277 AR2T2 0450 AXR1 0010 BIP.EO 4000 BOREO 2000 BR1 6310 BR1T1 0246 BR1T2 0424 6R2BLK 0002 BR2CA 0022 BR2DBP 0021 8R2T1 1000 BP2riA 1025 BR2T1C 1074 BR2T1D 1064 BR2T1E 1015 CHNEND 0010 CLR 0002 CMOCHN 0400 CMDEND 0004 CMDHLT 0010 CMOPCK 0200 CMORST 0040 CMDSTK 0020 CTL 6330 CTLT1 0600 CTLT2 0624 CTLT3 0662 CTLT3A 0665 CTLU 0702 CTLT5 0735 CTLT5A 0740 CTL4A 0721 CTL4e 0725 CTL4C 0706 OEVENO 0004 INTRFT 0020 INTX 0100

/8R2 ECHO FAILED

160-

INV OOOA K0377 0026 K0777 0027 K7000 0030 K7400 0031 K7767 0032 K7772 0033 RD 0001 SRVEND 0001 SRVHLT 0002 SRVPCK 0100 START 0200 STREO 7000 TMP1 003^ TMP2 0035 TMP3 0036 1ST 0002 UNCHCK 0002 WR 0004 X8IRE0 0025 XBOREO 0024 XSRHLT 00 ^ 3

-161-

Test 1/0. Perfürm the following sequence.

1. Place valid device address recognized by interface on

BUS OUT switches.

2. Riise ADR OUT.

3. Raise SEL OUT. Interface will respond with GPL IN,

store BUS OUT in AR1 and clear BR1, CU SEL and CMD

CYC lamps will go on.

4. Lower ADR OUT. Interface will respond with ADR IN

and place AR1 on BUS IN. CU SEL lamp will go off.

5. Raise BUS OUT (P). Lower ali other BUS UT switches.

Raise CMD OUT. Interface will respond by dropping

ADR IN. CMD DLY lamp will go on.

6. Drop CMD OUT. Interface will respond with STA IN

and place the status modifier bit (position 2) on

BUS IN. CHL SRV lanp will come on.

7. Raise SRV OUT. Interface will drop all inbound

signals and disconnect. CMD CYC, CMD DLY, and CHL

SRV lamps will ?il go off.

Start I/O. Perform the abovo sequence except Step S.

At Step 5 place a valid (non zero) channel command on

BUS OUT and ra^e CMD OUT. Interface will respond by

dropping \DR IN. CMD DLY lamp will go on. At Step 6

the interface will place an all-zero status byte on BUS

IN. Before Step 7 press STOP on PDP-8. After Step 7

the CMD END lamp will go on CTL. Press CONTINUE; the

CMD END bit will go off and the CHN REQ lamp will go on

together with one or more bits in the order field of

the CTL. The PDP-8 will continue running.

Service cycle sequences. Perform a Start I/O operation

with a char.nrl command specifying channel - inbound service

(e.g., octal 2). The CHL REQ nd CTL (0) lamps will go

on. Th^ RLQ IN tap line lamp will also go on. Perform

the following procedure.

1. Load a nonzero device address in AR2.

162-

2. Raise SEL OUT. Interface will respond by placing

AR2 on BUS IN and raising ADR IN and OPL IN. REQ IN

will be dropped. CÜ SEL and SRV CYC lamps will go

on.

3. Lower SEL OUT. CU SEL lamp will go out.

4. Raise CMD OUT. Interface will respond by dropping

ADR IN. CMD DLY lamp will go on.

5. Drop CMD OUT. Interface will respond by raising

SRV IN. CHL SRV lamp will go on.

6. Stop PDP-8. Raise SRV OUT. Interface will drop

all inbound tags and disconnect. SRV CYC, CMD DLY,

and CHL SRV lamps will go out. BRK REQ limp will

go on.

7. Start PDP-8. The cycle will recommence at Step 2

and may be continued until either PDP-8 word count

decrements to zero or until at Step 6 CMD OUT is

raised instead of SRV OUT. In these cases the ap-

propriate bits are set m CTL. (See interface des-

cription. )

-163-

/SYSTEM/360 INTERFACE ECHO TEST ROUTINES PAGE l /

I* + /* SYf.TEM/360 INTERFACE ECHO TEST ROUTINES » /* Dr. - HOW TO GET ALONG H TH THE 2870 ALWSl * /* *

I /ASSEMBLY PARAMETERS / ßUFSIZ=4000 /MAXIMUM SIZE OF DATA BUFFER / /INTERFACE RC6ISTER DEFINITIONS / «0=1 /IOP READ CLR=2 /IOP CLEAF! TST=2 /IOP TEST WR=4 /lop WRITE INV=4 /lop INVERT AR1=6300 /ADDRtSS REGISTER 1 BR1=6310 /BUFFER REGISTER 1 AR2=6320 /AOORESS REGISTER 2 CTL=6330 /CONTROL REGISTER / /INTERFACE CONTROL REGISTER BIT DEFINITIONS / STREO=?000 /STATUS REQUEST BtRE0=4000 /BUS-INBOUND SERVICE REQUEST B0RE0=2000 /BUS-0'JTBOUNÜ SERVICE REQUEST CMDCHN=OAOO /COMMAND CHAIe CM0PCK=0200 /BUS-OUT PARITY CHECK ON COMMAND BYT SRVPCK=0100 /BUS-OUT PARITY CHECK ON DATA BYTE CM0RST=0040 /SYSTEM OR SELECTIVE RESET CM0STK=0020 /STACK STATUS ON INITIAL SELECTION CMDHLT=0010 /HALT I/O CM0EN0=0004 /COMMAND ACCEPT SRVHLT=0a02 /SERVICE STOP SRVENDvQOOl /PDP-8 WC=0 / /SYSlEM/360 STATUS BYTE DEFINITIONS

0200 0201 0202 0203 0204 0205 0206 0207

^246 1320 7450 5200 7110 7620 5213 1317

UNCHCK=002 OEVEND=00'« CHNEND=010 / *2 / BLKXFRt*.+2 / *200 / TEST, JMS DELAY

TAD ACTIVE SNA JMP TEST CLL RAR SNL CI.A JMP TST2 TAO BUFLNG

/02 UNIT CHECK /04 DEVICE END /08 CHANNEL END

/3-CYCLE DATA BREAK BLOCK

/WAIT FOR CHANNEL SERVICE /DID CHANNEL STORE COMMAND

/NO. KEEP TRYING /YES. IS OUTBOUND SERVICE REQUESTED

/NO. CONTINUE /GET BUFFER S1U-

164-

/SYSTEM/360 INTERFACE ECHO TEST ROUTINES /

0210 Aii77 0211 2000 0212 5216

0213 1317 0214 ^277 0215 4000 0216 4232 0217 0004 0220 5200

0221 0222 0223 0224 •)225 0226 0227 0230 0231

0232 0233 0234 0235 0236 0237 0240 0241 0242 0243 0244 02^5

7402 6334 760* 7450 5200 3230 4232 0000 5200

0000 4246 1312 3322 1632 2232 3323 3320 1311 4277 7000 5632

/ TST2,

TST3,

JMS XMT BORfcO JMP TST3

TAO BUFLNG JMS XMT BIREO JMS STATUS OEVEND JMP TEST

PAGE

/YES. REQUEST OUTBOUND SERVICE

ERROR, HLT CTL INV LAS SNA JMP TEST OCA .+2 JMS STATUS 0 JMP TEST

/GET BUFFER SIZE /REQUEST INBOUND SERVICE

/TRANSMIT ENDING STATUS

/E0UIPMEN1/PR0GRAM CHECK /RESET INTEPCACE /SR-ENOING STATUS

/TRANSMIT ENDING STATUS

/RETURN TO WAIT LOOP

/TRANSMIT STATUS TO CHANNEL / STATUStO

JMS DELAY TAO ENOCHN DCA BUF TAD I STATUS ISZ STATUS DCA BUF+1 DCA ACTIVE TAD K7776 JMS XMT STREO JMP I STATUS

/NORMAL ENTRY /WAIT FOR CHANNEL SERVICE /IST BYTE - CHAMEL END

/ARGUMeNT=2ND BY It - DEVICE-END STAT

/RESET CHANNEL COMMAND

/STATUS REQUEST

/NORMAL EXIT

/DELAY FOR CHANNEL OPERATION /

0246 0000 DELAY, 0 0247 6331 CTL RD 0250 3321 OCA TMP 0251 1321 TAO TMP 0252 0310 AND K7000 0253 7640 SZA CLA 0254 5247 JMP DELAY+1 0255 1321 TAO TMP 0256 0315 AND CMOBIT 0257 7650 SNA CLA 0260 5266 JMP DELI 0261 6301 API RD 0262 6326 AR2 CLR+WR 0263 7200 fl4 0264 6311 BR1 RD 0265 3320 DCA ACTIVE 0266 1321 DFL1, TAD TMP 0267 0314 AND RSTBIT 0270 633f CTL INV 0271 7200 CLA

/NORMAL ENTRY /READ INTERFACE STATUS

/IS INTERFACE BUSY

/YES. CONTINUE IN WAIT LOOP /NO. HAS DEVICE ADDRESS BEEN STORED

/NO. CONTINUE /YES. COPY AR1 IN AR2

/STORE CHANNEL COMMAND

/RESET INTERFACE

if

U

-?

m

m

-16S.

0272 0273 027^ 0275 0276

1321 0313 7A50 56^6 5221

/SYSTBM/360 /

TAD AND SNA JMP JMP

INTERFACE cCH„ TEST ROUTINES PAGE

TMP BADB1T

I DELAY ERROR

/ARE ANY UNUSUAL-ENO BITS SET

/NO, NORMAL EXIT /YES. ABORT

0277 0300 0301 0302 0303 03J4 0305 J306 ^307

0310 0311 0312 0313 0314 0315 0316 0317 0320

/TRANSMIT /

BYTES ON MULTIPLEX CHANNEL

0000 3002 1316 3003 1677 2277 6334 7200 5677

7000 7776 0010 0370 0407 0034 0321 4000 0000

XMT, 0 OCA TAD DC A TAD ISZ CTL CLA JMP

7000 7776

BLKXFR PTR BLKXFR+1 1 XMT XMT INV

1 XMT

/ENTRY. AC-'^C

/ARGUMENT=CTL BITS

/START OPERATION

/NORMAL EXIT

K7000, K7776, ENDCHNtCHNEND BADBIT.CMDRST+CMDSTK+CMOHLT+CMOPCK+SRVPCK RSTBIT.CMOENO+SRVENO+SRVHLT+CMDCHN CMDBIT,CM0STK+CMOHLT+CMDEND PTR, BUF-1 /POINTER FOR DATA BREAK BUFLNÜL-ßUFSIZ /BUFFER SIZE ACTIVE.O /CHANNEL COMMAND TMP, *.+l /TEMPORARY Bl'F, *.+BUFSIZ /BUFFER /

ACTIVE 0320 AR1 6300 AR2 6J20 BADBIT 0313 BIREO 4000 BI.KXFR 0002 BOREC 2000 BR1 6310 BUF 0^22 BUFLNG 03 J 7 BUFSIZ <.000 CHNENO 0010 CLR 0002 CMDBIT 0?15 CMOCHM 0*00 CMDENO 0004 CMDHLT 0010 CMDPCK 0200 CM0R5.T 0040 CMDSTK 0020 CTL 6330 DELAY 0246 DELI 0266 DEVEND 0004 ENDCHN 0312 ERROR 0221 INV 0004 K7000 0310

-166-

K7776 03 i I PTR 0316 RD 0001 RSTBIT 0314 SRVEND 0001 SRVHLT 000? SRVPCK 0100 STATUS 0232 STREO 7000 TEST 0200 TMP 0321 TST 0002 TST2 0213 TST3 0216 UNCHCK 0002 WR OOOA XMT 0277

UNCLASSIFIED ■167- SfCurily Classification

DOCUMENT CONTROL DATA R&D (Security clmssilUation ol f/lfe, body nf nbxftmct and mdrxinjl «nnotttion muy^ftg »nfrgrf whun th* gvwrmlt rvpott la ct*»»lli9d)

2«. ^ t ORIGINATING AC Tt V! T Y fCüfpofai» «ufft<2f;

THE UNIVERSITY OF MICHIGAN CONCOMP PROJECT

2«. ^tPOWT »ECURITY CLASSIFICATION

Unclassified 2b. 6BOUP

3 HEPOBT TITLE

SYSTEM/360 INTERFACE ENGINEERING REPORT

4 DESCniPTive NOTKS (Typ* ol repen and Inclutivt daita)

Memorandum 13 i. AutHORlSI (Fits* nmme, middle initial, ta*t nnwrj

MILLS, DAVID

6 REPORT DATE

March, 1968 M, CONTRACT OR GRANT NO

DA-49-083 OSA-3050 b. PROJECT NO.

7«. lOTAi. NO OF PASES

166 9«. ORIGINATOR'S REPORT NUMSERISI

76. NO OF «EFS

ncne

Memorandum 13

9t. OTHER REPORT NO(S) (Any olhrr numbers thai may be masigned Ibis report)

12 DISTRIBUTION SI ATEMENT

Qualified requesters may obtain copies of this report from DDC

II SUPPLEMENT »RY NOTES li. SPONSORING MILI T ART ACTIVITY

13 ABSTRAC T

An interface which connects a smali special-pur-pose digital computer to a large general-purpose '1: -'♦-■• .ata processing system is described in this report, 'x. _ ^tiall computer is the Digital Equipment Corporation PDP-8 which itself is a component of a data collection and distribution system called the Data Concentrator. The large data processing system is the IBM System/360 Model 67, which is the principal computing element at The University of Michigan Computing Center. The interface is designed to be attached to the multiplexor channel of the Model 67 alcng with other input-output components such as card readers, line printers, and communications equipment, and satisfies all IBM standards and interface conventions established for this type of attachment. The interface provides a bidirectional data transfer between the two machines of up to 80 thousand bytes (characters) per second using cycle-steal techniques in which data are transferred directJy between the Model 67 multiplexor channel and the PDP-8 core mamory without explicit program intervention.

DD iFNr.,1473 Unclassified Security Classificilion

-168- Security Classification

KEY «ORDS U IN K JB

interface, multiplexor channel, cycle-steal, control unit, PDP-8, Systein/360, Model 67, data transmission.

Security Ciassifi-ition