design and experimental validation of a multiphase vrm controllermazumder/12.pdf · 2009-01-25 ·...

Design and experimental validation of amultiphase VRM controller

S.K. Mazumder and S.L. Kamisetty

Abstract: By combining the concepts of multiple-sliding-surface and integral-variable-structurecontrols, one can develop a robust controller for a multiphase 9V VRM, which comprises fourparallel DC–DC synchronous buck convertors operating at 300kHz. The advantages of thecontrol scheme are its simplicity in design, good dynamic response, robustness, ability to nullify thebus-voltage error and the error between the load currents of the convertor modules, and ability toreduce the impact of high-frequency dynamics due to parasitics on the closed-loop control system.Unlike a conventional variable-structure controller (VSC), which achieves superior transientperformance by optimising (and hence, by varying) the switching frequency, the novel controlleris able to retain the excellent dynamic performance of a conventional VSC and yet maintain aconstant-frequency operation of a PWM controller under ‘steady-state’ condition. The latter isachieved by obtaining a duty-ratio signal; however, unlike a PWM controller, the new controllercalculates the duty ratio based on Lyapunov’s stability crietrion. Thus, the new controller alsopermits interleaved operation of the VRM modules.

1 Introduction

The power requirement for microprocessors doublesapproximately every 36 months. Future power-deliverysystems for microprocessors need to provide high currentsat very low noise margins [1]. In addition, transient responsespecifications are also becoming more stringent. Forinstance, the design requirements specified by Intel forVRM 9.0 are shown in Table 1 [2]. Designing VRMs tomeet this continually increasing power requirement at lowvoltages and high currents remains challenging. To achievethe specified transient-load response a single buck convertorwould require a very high output-filter capacitance, whichwould increase the size of the VRM and make itimpractical.

Paralleling a number of DC–DC synchronous-buck-convertor (SBC) modules (as shown in Fig. 1) usinginterleaving technique solves this problem [3, 4], therebyincreasing the output ripple frequency and reducing the sizeof the output-filter capacitance. The multiphase VRM,comprising parallel DC–DC SBCs, operates under closed-loop feedback control to regulate the bus voltage and toachieve a uniform current distribution among the inter-leaved modules. The interaction among the convertormodules is a major source of nonlinearity, in addition tothe switching nonlinearity. However, there are few studieson the nonlinear control of parallel DC–DC convertorswhere, unlike the stand-alone convertors, there is a strong

interaction among the convertor modules apart from thefeed-forward and feedback disturbances.

In [5], a fuzzy-logic compensator is proposed for themaster–slave control of a parallel DC–DC convertor. Thecontroller uses a proportional-integral-derivative (PID)expert to derive the fuzzy-inference rules; it shows improvedrobustness compared with linear controllers. However, thecontrol design is purely heuristic and the stability of theoverall system has not been proven. In [6], a VSC has beendeveloped for a buck convertor using interleaving. How-ever, the interleaving scheme works only for three parallelmodules. Besides, that paper does not give any detailsregarding the existence and stability of the slidingmanifolds.

In this paper, we implement a hybrid nonlinear controllerfor parallel SBCs and demonstrate experimentally that thesteady-state and transient performances of the closed-loopparallel SBC satisfies Intel’s VRM 9.0 design specifications(as shown in Table 1). The controller uses the concepts of

Table 1: VRM 9.0 design guidelines [2]

Electrical specifications Intel VRM 9.0 design guidelines

Output voltage 1.408–1.5V (our nominal reference:1.45V)

Output current 60A

No-load operation Outputs must not exceed 110% of themaximum value

Overshoot at turn-onor turn-off

Must be within 2% of the nominaloutput voltage set by VID code

Slew rate 50A/ms

Current sharing Should be accurate within 10% of therated output current, except duringinitial power-up and transient re-sponses

S.K. Mazumder is with Laboratory for Energy and Switching-ElectronicsSystems, Department of Electrical and Computer Engineering, University ofIllinois, 851 S Morgan St, M/C 154, 1020 SEO, Chicago, IL 60607, USA

S.L. Kamisetty is with Servo Tech Inc., 1747 W. Roosevelt Road, Suite 110,Chicago, IL 60680, USA

E-mail: [email protected]

r IEE, 2005

IEE Proceedings online no. 20045165

doi:10.1049/ip-epa:20045165

Paper first received 23rd September 2004 and in final revised form 10thFebruary 2005

1076 IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005

Authorized licensed use limited to: IEEE Xplore. Downloaded on January 25, 2009 at 15:07 from IEEE Xplore. Restrictions apply.

integral-variable-structure- and multiple-sliding-surface-control (i.e. IVSC and MSSC) schemes [7]. The IVSCretains all of the properties of a VSC, i.e. simplicity indesign, good dynamic response and robustness. In addition,the integral action of the IVSC eliminates the bus-voltageerror and the error between the load currents of theconvertor modules under steady-state conditions, and itreduces the impact of very high-frequency dynamics due toparasitics on the closed-loop system. Finally, when the error

trajectories are inside the boundary layer we are able, bymodifying the control using the concepts of MSSC [8, 9] orthe block-control principle [10, 11], to reject mismatcheddisturbances [12, 13] and keep the steady-state switchingfrequency constant.

2 Nonlinear-control scheme

The control scheme for the convertor has two modes ofoperation: one when the error trajectories are outside theboundary layer and the other when they are inside theboundary layer. The block diagram of the overall controlscheme is shown in Fig. 2 for N parallel SBC modules. Theboundary layer, which is time-varying, is formed by a rampsignal with a frequency fs (¼ 1/Ts). The limits of thisboundary layer correspond to the maximum and minimumvalues of the ramp. At the beginning of each switchingcycle, we determine whether the error trajectories (as shownin Fig. 3), which govern the regulation of the multiphase

u S11

SN1

SN2

LN rLN

CN VCN

iLN iNO

S12C1

L1

iL1

VC1 VCRload

rL1

i10 i0Vinductor _

_

+

+

_

+

Fig. 1 N-module multiphase VRM comprising N parallel SBCs

Vr 1

PWM signal

σk

LN

CN vCN−SN2

SN1

i0

i10

vC1

S11

L1

S12

+rL1C

1−

rLN +

iN0

−

+

+

−

Vm

driver

differentialamplifier

differential amplifier

power stage hybrid controller

u

innercontrol

outercontrol

iLN

iL1

iL1

F

F

fv 1vC 1

fv 1vC 1

F

Fig. 2 Illustration of the hybrid nonlinear control scheme for the ‘first’ SBC module of an N-module SBCThe control schemes for the other N1 modules are the same. The outer and inner controls are described in Section 2. The block ‘F’ represents alowpass filter, which eliminates all harmonic components including and above the switching frequency. The block ‘differential amplifier’ represents adifferential amplifier used to sense the inductor current

Vrk

k

−

+

+_ +

+

+

Ckvk vf

Gk 2O

N

j =1LjijN

1 if

Lkik if

+

+

−

Gk1O

Gk 3O∑

∫

∫

Fig. 3 Block diagram showing the determination of sk

IEE Proc.-Electr. Power Appl., Vol. 152, No. 5, September 2005 1077


VRM and are given by

sk ¼ Gk1O Vr fvkvckð Þ þ Gk2O

ZVrk fvkvckð Þdt

þGk3O

Z1

N

XN

j¼1fijiLj fikiLk

!dt fikiLk ð1Þ

are within the limits of the time-varying ramp, and based onthat, determine what is the mode of operation. In (1), theconstants Gk1O, Gk2O and Gk3O are the controller gains(selection process described in [7]), fvk and fik are thefeedback-sensor gains for the output voltage and inductorcurrents, Vr is the reference of the output bus voltage, and1N

PNj¼1 fijiLj represents the average of all inductor currents.

The first two terms in (1) minimise voltage error while thethird term ensures equal distribution of load current amongthe various modules. The last term improves the dynamicresponse of the system. The derivatives in a conventionalVSC are replaced by integrals in (1). This is desirablebecause the integrators filter out the impacts of the high-frequency parasitic dynamics of the switching convertors. Ifsk is above the boundary, the control signal to the high-sideswitch of a SBC is a constant high while if it is below theboundary, the switch is turned off till the error trajectoryfalls within the boundary. The conditions under whichcontrol saturation outside the boundary layer guaranteesthat the error trajectories will reach the boundary layer arederived in [2, 7].

To derive the control law within the boundary layer, first,using Fig. 1 and a state–space-averaged model, we definethe dynamics of the parallel DC–DC SBC as:

diLk

dt¼ 1

LkrLkiLk þ vCk dku

dvCk

dt¼ 1

CkiLk iko

; k ¼ 1; 2 . . . N ð2Þ

where, dk is the duty ratio, iLk and vCk are the averagedvalues of the inductor currents and capacitor voltages, andiko are the load current of individual convertor. Next, wedefine the following sliding surfaces/error trajectories insidethe boundary layer (computation of s1k and s2k illustratedin Fig. 4):

s1k ¼ Gk1I e1k þ Gk2I e2k þ Gk3I e3k ð3Þ

s2k ¼ iLkd iLk ð4Þwhere

e1k ¼ Vrk fvkvCk ð5Þ

e2k ¼Z

Vrk fvkvCkð Þdt ð6Þ

e3k ¼Z

1

N

XN

j¼1fijiLj fikiLk

!dt ð7Þ

Gk1I, Gk2I and Gk3I are the controller gains (selection processdescribed in [7]). The sliding surfaces (3) and (4) are derivedas follows. First, we define s1k, which ensures regulation ofthe output voltage by incorporating the first two terms in(3), while the third term in (3) ensures equal current sharingamong the parallel convertor modules. The sliding surfaces2k ensures that the inductor current (iLk) of each modulefollows a desired current reference (iLkd). The choice of iLkdin (11), is made such that stable convergence on the slidingsurface s1k is guaranteed, as proven later in this Section.Stable convergence on the sliding surface s2k is achieved byappropriate selection of control dk as derived in (17). Thus,

the overall control concept can be summarised as follows:first, guarantee rapid convergence of error trajectories onthe sliding s2k using dk (by suitable choice of a1k), whichensures that iLkd is following iLk very closely; and then, usingiLkd as a fictitious control, stabilise the error trajectories onthe sliding surface s1k.

We now derive iLkd and dk that ensures existenceand stability of the dynamics on the two sliding surfacesas well as the stability of the dynamics on the hyperplaneformed by s1k and s2k. First, we differentiate s1k, toobtain

_s1k ¼ Gk1I _e1k þ Gk2I _e2k þ Gk3I _e3k ð8ÞSubstituting (2) in (8) yields

_s1k ¼Gk1I fvk

CkiLk iko

þ Gk2I _e2k þ Gk3I _e3k ð9Þ

Substituting for iLk from (4) into (9) we obtain

_s1k ¼Gk1I fvk

Ckiko þ s2k iLkd

þ Gk2I _e2k þ Gk3I _e3k ð10Þ

We let

iLkd ¼ b1ks1k þ b2ksign s1kð Þ þ b3k_e2k þ b4k

_e3k ð11Þ

Vrk1k

+

+

+

+

+

++

−

_

_

_++

+

+

+

++

Ckvk vf

Lkik if

Gk1I

Gk2I

e2k

Gk3I

1k

sign(.)

iLk

iLkd

1k 2k

N

j =1LjijN

1 if∑

e2k

1

2

3

4

e3k

e3k

∫

∫

a

b

•

•

•

•

Fig. 4 Block diagram showing the determination of s1k and s2k

a s1k

b s2k

Fig. 5 Top layer of the experimental prototype board



where b1k, b2k, b3k and b4k are constants, in (11) and obtain

_s1k ¼Gk1I fvk

Ckb1ks1k þ b2ksign s1kð Þ iko s2k

Gk1I fvkb3k

Ck Gk2I

_e2k

Gk1I fvkb4k

Ck Gk3I

_e3k

ð12Þ

Choosing b3k ¼CkGk2Ið ÞfvkGk1Ið Þ and b4k ¼

CkGk2Ið ÞfvkGk1Ið Þ reduces (12) to

_s1k ¼Gk1I fvk

Ckb1ks1k þ b2ksign s1kð Þ iko s2k

ð13Þ

Equation (13) shows that, when s2k ¼ 0, the dynamics ons1k ¼ 0 are convergent (for sk40, or s1ko0) provided thatb2k4ikOmax. We assume that s2k ¼ 0 and design thecontrol such that the rate of convergence of dynamics ons2k ¼ 0 are much faster than on s1k ¼ 0.

Next, we differentiate s2k in (4) and set it equal to s1kLk

s2k (where a1k are positive constants) to guaranteeconvergence of the dynamics on s2k ¼ 0 (this is because,

for stability, s2k _s2ko0 and this condition is guaranteed by

the choice of _s2k in (14)); the result is

_s2k ¼ _iLkd _iLk ¼ _iLkd þrLk

LkiLk

þ 1

LkvCk

1

Lkdku ¼ a1k

Lks2k ð14Þ

Next, using the Lyapunov function

V s1k; s2kð Þ ¼ 1

2s1k

2 þ s2k2

ð15Þ

and (13) and (14), we can show that

_V ¼ s1k _s1k þ s2k _s2k

¼ s1k Gk1I fvk

Ckb1ks1k þ b2ksign s1kð Þ iko s2kf g

þ s2ka1k

Lks2k

Gk1I fvk

Ckb1ks1k

2 þ a1k

Lks2k

2

þ Gk1I fvk

Cks1k s2k ¼

Gk1I fvk

Ckb1k

rs1k

1

2

Gk1I fvk

Ckb1k

rs2k

2

a1k

Lk 1

4

Gk1I fvk

Ckb1k

s2k

2 ð16Þ

is less than zero provided that

a1kCkb1kð ÞLkGkI1fvk

41

4

From (14), by equating _iLkd þ rLkLk

iLk þ 1Lk

vCk 1Lk

dku ¼ a1k

Lks2k

we obtain

dk ¼1

ua1ks2k þ Lk

_iLkd þ rLkiLk þ vCk

ð17Þ

which ensures that, for the above choice of control dk, thestability of the sliding surface s2k is guaranteed. We alsonote that, in (17), the term a1k s2k compensates for anyparametric uncertainty in rLk. (Typically, such variationsdue to manufacturing tolerances are within 5%.) Forinstance, if rLk is slightly higher than its nominal value, thena slightly higher iLk is required to regulate the outputvoltage at the reference value. This compensation isachieved (due to slight adjustment in dk) owing to slightvariation in s2k that depends on iLkd , which in turn dependson s1k; the latter accounts for error in the output voltage.Using the error signal vek, which is obtained from the duty

ratio dk using vek¼Vm dk, and the fixed-frequency rampsignals, we can operate N parallel DC–DC SBCs insynchroncity or in interleaving.

3 Experimental results

Figures 5 and 6 show the experimental prototype of theoverall multiphase VRM and the circuitry for one powermodule, respectively. The experimental printed-circuitboard (PCB) has four layers to reduce the impact of noiseand enable operation at a high switching frequency. Theparameters for the VRM are tabulated in Table 2, while thecontrol specifications are outlined in Table 1. The VRMcomprises four phases of the power stage (i.e. parallelDC–DC SBCs) and the nonlinear controller, outlined inSection 2, using analogue circuits. The complete detailsof the experimental VRM implementation are providedin [2].

The four modules of the VRM operate at 300kHz andare interleaved. The interleaving technique is implementedby phase shifting the drive signals of the paralleled modulesby 3601/N, where N is the number of parallel SBCs. Becausewe have four modules, we have phase-shifted the drivesignals by a quarter of a switching cycle. This is ratified inFig. 7, which shows the gate signals of the high- and low-side power MOSFETs (FDP6035L and FDP8030L,respectively), under steady-state conditions.

Rg11

Rg12

Q11

Q12

Q21

C21 C

22Q

22

Q31

Q41

Q32

Q42

C11 C

12iL1

iL2

VC

gate11

gate12

Rg21

Rg22

gate21

gate22

Rg31

Rg32

Rs11

Rs14

Rs12

Rs13

Rs21

Rs24

Rs22 Rs

23

L3

L4

gate31

gate32

Rg41

Rg42

gate41

gate42

15

–15

–15

C31 C32

iL3

Rs31

Rs34

Rs32 Rs33–15

15

C41 C42iL3

Rs41

Rs44

Rs42 Rs43–15

15

15

a

L1

L2

Rsense1

Rsense2

Rsense3

Rsense4

Fig. 6 Schematics of the nonlinear controller for one phase of thefour-phase VRM [2] shown in Figs. 3 and 4a. In (b), S1 representss1, S11 bar and S2 bar represent s11 and s21, respectively



Fig. 6 Continued



Figure 8 shows the output voltages and the inductorcurrents of the four modules of the VRM, under steady-state conditions. The four inductor currents are interleaved,i.e. they differ in phase by 901. The high-side switches in thefour modules of the VRM are turned on at time intervalsthat are a quarter of a switching-time period apart fromeach other. Therefore, the inductor currents do not rise andfall at the same time, but, are phase shifted by a quarter of aswitching cycle.

Figure 9 shows the load current and the output voltageof the VRM during a step-down load transient of 60A to20A at a slew rate of 50A/ms. During the severe loadtransient, the output voltage stays within the 2% limit, asspecified by Intel VRM specifications in Table 1. Theinductor currents of the four phases also respondsatisfactorily and maintain an even distribution of theload current among the modules during the transientconditions. The performance of the VRM remainsexcellent even during a step-up load transient of 20A to60A (at a slew rate of 50A/ms). This is illustrated in Fig. 10.Once again, the output voltage satisfied the Intel VRMspecifications and the current sharing was maintained

Table 2: Nominal parameters for the four-phase VRM

Parameter Nominal value

rDS (on) of MOSFET 0.0056O

rLk 0.024O

Lk 1mH

Ck 2200 mF

Vr 1.45V

U 12V

fik 0.02

fvk 1

Switching frequency 300kHz

DC offset of the ramps 1.5V

Height of the ramps 3.0V

Gk1O 5

Gk2O 1.5105

Gk3O 500

Gk1I 10

Gk2I 1.5105

Gk3I 500

Ch1Ch3

5.0V5.0V

Ch1Ch3

5.0V5.0V A Ch2

M 2.0µs 125MS/s2.8V

8.0ns/pt

Ch1

4

3

2

3

2

1

Ch320.0V20.0V

Ch2Ch4

20.0V20.0V A Ch2

M 2.0µs 125MS/s8.8V

8.0ns/pt

4

1

a

b

Fig. 7 Gate signals of the four VRM modulesa Low-side power MOSFETsb High-side power MOSFETs

Ch1Ch3

a

b

1.0V5.0A Ω Ch4 10.0mV A Ch3

M 2.0µs 125MS/s0.0A

8.0ns/pt1

4

Ch1Ch3

1.0V5.0A Ω Ch4 10.0mV A Ch3

M 2.0µs 125MS/s0.0A

8.0ns/pt1

4

Fig. 8 Interleaved inductor currents in the four modules of theVRM and the output voltageCurrently the project has access to only two current amplifiers, so onlytwo current waveforms can be recorded at once; this applies also toFigs. 9–12a Inductor currents (5A/division) for modules 1 and 3b Inductor currents (5A/division) for modules 2 and 4



during the dynamic condition in spite of a rapid change inthe load. Finally, Figs. 11 and 12 show the error-trajectorywaveforms s1k and s2k during the load transients.

4 Summary and conclusions

Using the concepts of integral-variable-structure and multi-ple-sliding-surface controls (i.e. IVSC and MSSC), we haveimplemented a robust nonlinear controller for a four-phaseVRM, operating at 300kHz. The power stage of each phasecomprises a synchronous buck convertor, the input to all ofwhich is 12V; the output voltage of the VRM is set at1.45V. We demonstrate the excellent performances of themultiphase VRM under steady-state and severe dynamic

conditions. The controller is able to retain the ‘transient’performance of a conventional sliding-mode/min–maxcontroller (SMC/MMC) and yet maintain a constant-frequency operation of a PWM controller under ‘steady-state’ conditions. The latter are achieved by obtaining aduty-ratio signal; however, unlike a conventional PWMcontroller, the new controller calculates the duty ratio basedon Lyapunov’s stability criterion. The robust controllernullifies the bus-voltage and the load-current errors, exhibitsgood current sharing under steady-state and dynamicconditions, and, by using IVSC (which uses integrators inthe control instead of the differentiators in a conventionalSMC/MMC), filters out any impacts of the high-frequencyparasitic dynamics in the system. An added advantage of

Ch3 1.0VCh2 10.0mV

a

b

c

A Ch2M 1.0ms 250kS/s

20.6mV4.0µs/pt

2

4

Ch3 10.0mVCh2 1.0V


10.4A4.0µs/pt

2

3

Ω

Ch3 10.0mVCh2 1.0VCh4 10.0A

Ch4 10.0A


10.4A4.0µs/pt

2

3

4

Ω

4

Fig. 9 Performance of the VRM during a step-up load transienta Load current (20 A/division) and output voltage of the VRMb VRM output voltage and the inductor currents (10A/division) ofmodules 1 and 3c VRM output voltage and the inductor currents (10A/division) ofmodules 2 and 4

Ch3 1.0VCh2 10.0mV

aA Ch2M 1.0ms 250kS/s

20.0mV4.0µs/pt

2

Ch3 10.0mVCh2 1.0VCh4 10.0A A Ch4

M 2.0ms 250kS/s10.4A

4.0µs/pt

4

3

Ω

Ch3 10.0mVCh2 1.0VCh4 10.0A A Ch4

M 2.0ms 250kS/s10.4A

4.0µs/pt

4

3

Ω

b

c

Fig. 10 Performance of the VRM during a step-down loadtransienta Load current (20A/division) and output voltage of the VRMb VRM output voltage and the inductor currents (10A/division) ofmodules 1 and 3c VRM output voltage and the inductor currents (10 A/division) ofmodules 2 and 4



Ch32.0VCh12.0V Ch2 2.0V

Ch4 10.0A

a

A Ch4M 1.0ms125kS/s

10.0A8.0µs/pt

3

2

2 2

1

1

1

3

1

4

3

4

4

3

2

4

Ω Ch3 2.0VCh1 2.0V Ch2 2.0V

Ch4 10.0A

c

b d


10.0A8.0µs/pt

Ω

Ch32.0VCh12.0V Ch2 2.0mV

Ch4 10.0AM 2.0ms250kS/sA Ch4 10.0A

8.0µs/ptΩ Ch3 2.0V

Ch1 2.0V Ch2 2.0VCh4 10.0A

M 2.0ms 125kS/sA Ch4 10.0A

8.0µs/ptΩ

Fig. 11 Inductor current for module 1 and error signals (s1k) for SBC modules 1–4 during step-down and step-up load transientsTop trace: inductor currenta Step-down, experimental results for SBC modules 1 and 3b Step-down, experimental results for SBC modules 2 and 4c Step-up, experimental results for SBC modules 1 and 3d Step-up, experimental results for SBC modules 2 and 4

Ch3 1.0VCh1 1.0V Ch2 1.0V

Ch4 10.0Aa c

A Ch4M 2.0ms125kS/s

10.0A8.0µs/pt

3

3

22

4 4

3

2

1

4

3

2

4

Ω Ch3 1.0VCh1 1.0V Ch2 1.0V

Ch4 10.0A A Ch4M 2.0ms125kS/s

10.0A8.0µs/pt

Ω

Ch3 1.0VCh1 1.0V Ch2 1.0V

Ch4 10.0A

b

A Ch4M 2.0ms125kS/s

10.0A8.0µs/pt

Ωd

Ch3 1.0VCh1 1.0V Ch2 1.0V

Ch4 10.0A A Ch4M 2.0ms125kS/s

10.0A8.0µs/pt

Ω

1

1

1

Fig. 12 Inductor current for module 1 and error signals (s2k) for SBC modules 1–4Top trace: inductor currenta Step-down, experimental results for SBC modules 1 and 3b Step-down, experimental results for SBC modules 2 and 4c Step-up, experimental results for SBC modules 1 and 3d Step-up, experimental results for SBC modules 2 and 4



the control is that it enables the modules to be interleavedwhich reduces the output-capacitor size and makes thewhole system more compact.

5 Acknowledgment

This work is supported in part by the National ScienceFoundation CAREER Award received by Prof. Mazumderin 2003 under Award 0239131. However, any opinions,findings, conclusions, or recommendations expressed hereinare those of the authors and do not necessarily reflect theviews of the NSF. Prof. Mazumder thanks EdwardStanford and Shamala Chickamenahalli, both at Intel, fortheir discussions during the course of this work.

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