VLSI PROJECTS LIST-2013PROCESSOR ARCHITECTURE:-

1.Design and implementation of two variable multiplier using KCM and Vedic mathematics

2 .Design and implementation of a high performance multiplier using HDL-

3. FPGA implementation of binary coded Decimal digit adders and multipliers-

4. High speed modified booth encoder multiplier for signed and unsigned numbers-

5. High speed signed Multiplier for Digital Signal Processing applications-

6. Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials (IEEE TRANSCATION)

7. Binary floating-point FMA unit design with SIMD support-(IEEE TRANSCATION)

8. An efficient implementation of floating point multiplier-

9. A Novel Low Power and High Speed Wallace Tree Multiplier for RISC Processor

10. High speed and low space complexity FPGA based ECC processor-

11. High speed Asic design of Complex multiplier using vedic mathematics-

12. A new reversible design of BCD adder-

13. Parallel architecture of hierarchical optical flow estimation-

14. Design and characterization of parallel prefix adder using FPGA-

15. Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing (IEEE TRANSCATION)

SIGNAL , IMAGE & VIDEO PROCESSING:-

1. Implementation of hybrid wave-pipelined 2D DWT using ASIC-

2. Design of plural-multiplier based on cordic algorithm for FFT application-

3. Viterbi-based Efficient Test Data Compression- (IEEE TRANSCATION)

4. A feature-based Robust Digital Image Water marking Scheme-

5. Digital Image Water marking based on Super Resolution image reconstruction-

6. Water marking mobile phone color images with reed solomon error correcting code-

7. An efficient VLSI architecture for lifting-based Discrete Wavelet Transform- (IEEE TRANSCATION) 8.Hardware Implementation of High Throughput RC4 Algorithm

9. Design for image segment using gabor filter for disease detection-

10. Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm (IEEE TRANSCATION)

11. Hardware implementation of a digital water marking system for video Authentication- (IEEE TRANSCATION)- 12. Design and implementation of Area-optimized AES based FPGA-

13. A multi channel water marking scheme based on DCT-DWT-

14. An implementation of a 2D FIR filter using the signed-digit number system-

15. FPGA based FFT algorithm implementation in Wi-Max communications system-

16. FPGA design of AES core architecture for portable hard disk-

17. image encryption based on AES key Expansion-

18. Feature extraction of digital aerial images by FPGA based implementation of edge detection algorithms-

19. An efficient architecture design for VGA monitor controller-

20. Curve fitting algorithm FPGA implementation-

21. FPGA implementation of AES algorithm-

22. Design and implementation of an FPGA-based real-time face recoganization system-

23. A High-Speed Low-Complexity Modified Radix-2^5 FFT Processor for Gigabit WPAN

Applications

24. Efficient VLSI architecture for Discrete wavelet transform-

25. Construction of optimim Composite Field Architecture for Compact High-Throughput AES S-Boxes (IEEE TRANSCATION)

26. A High-Speed Low-Complexity Modified Radix-2^5 FFT Processor for Gigabit WPAN Applications

COMMUNICATION & BUS PROTOCOLS:-

1. High-Speed Low-Power Viterbi Decoder Design for TCM Decoders (IEEE TRANSCATION)

2. VHDL implementation of UART with Status register-

3. VLSI Based Robust Router Architecture

4. Design and simulation of UART serial communication module based on VHDL-

5. FPGA implementation of RS232 to universal serial bus converter(USB)-

6. Design of Serial Communication interface based on FPGA-

7. Design of Building an AMBA AHB compliant Memory Controller

8. Implementation of a Self-Motivated Arbitration Scheme for the Multilayer AHB Bus matrix (IEEE TRANSCATION) 9. Design and Implementation of Multi-Serials to Ethernet Gate way -

10. Design and implemention of acqusition and tracking of Satillite id-

11. Design and implementation of Universal asynchronous communication protocol- (IEEE TRANSCATION)

LOW POWER:-

1. Design of 64-bit low power parallel prefix VLSI adder for high speed Arithmetic Circuits

2. Design of low power high speed vlsi adder sub system-

3. A hybrid low power adder for high-performance processor (HICPA)-

4. Low power and area efficient carry select adder- (IEEE TRANSCATION)

5. Design of low-power and high performance Radix-4 multiplier-

6. Design of low power TPG using LP-LFSR-

7. Design of low power and high speed configurable booth multiplier-

8. Design and implementation of low power digital FIR filter based on low power multipliers and adders on Xilinx FPGA

9. A very fast and low power carry select adder circuit-

10. Design of low power column bypass multiplier using FPGA

BIST ALGORITHMS:-1. Accumulator based 3-weight pattern generation-(IEEE TRANSCATION)

2. Nonlinear Multi-Error Correction Codes for Reliable MLC NAND Flash Memories (IEEE TRANSCATION)

3. Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code (IEEE TRANSCATION) 4. Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error correction (IEEE TRANSCATION) 5. Direct Compare of Information Coded With Error-Correcting Codes (IEEE TRANSCATION) 6. A Non-binary LDPC Decoder Architecture With Adaptive Message Control (IEEE TRANSCATION) 7. Product Code Schemes for Error Correction in MLC NAND Flash Memories (IEEE TRANSCATION) 8. Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications (IEEE TRANSCATION) 9. Low-Complexity Reliability-Based Message-Passing Decoder Architectures for Non-Binary LDPC Codes (IEEE TRANSCATION) 10.VHDL design and FPGA implementation of weighted majority logic decoders

11. Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication (IEEE TRANSCATION)