design and implementation of sigma-delta analog to digital

7/29/2019 Design and Implementation of Sigma-Delta Analog to Digital

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Design and implementation of Sigma-Delta

Analog to Digital converter


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Contents:-

1. Introduction to ADC.

2. Types of A/D Converters.

3. SIGMA-DELTA ADC KEY CONCEPTS.

4. Circuit Description.

5. Integrator.6. Comparator

7. Decimation.

8. Sigma Delta - Merits & Demerits.

9. Applications.

10. Conclusion.

11. My Future Work.

12. References.


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Introduction to ADC:-

1. Digital system require discret digital data

2. Uses a circuit that converts an analog signal

at its input to a digital code.

3. Generates a 2n-bit binary code for any given

input voltage.

Digital System?Analog Digital


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Types of A/D Converters:-


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SIGMA-DELTA ADC KEY CONCEPTS:-

1. Noise Shaping:-

Distributing the converter quantization error or noise such that it is

very low in the band of interest.

2. Oversampling:-

Oversampling simply refers to sampling the signal at a ratesignificantly higher than the Nyquist Frequency.

3. Digital Filtering:-

It is used to filter the attenuate signals and noise that are outside the

band of interest.

4. Decimation:-

Decimation is the act of reducing the data rate down from the

oversampling rate without losing information


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Circuit Description:-

First order Sigma-Delta modulator Top Level Design:-

Integrator

Digital

low-pass

filter

Sample

decimatorVin +

-

+

1-bit

DAC

-

Over sampler

Serial output


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Integrator:-

It is used as noise shaping filter in ADC to

distributes the converter quantization error or noise

such that it is very low in the band of interest.

Vi

C1

C2

Vo

1

2

1

2


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Comparator:-

1. The comparator is widely used in the process of converting analog

signal to digital signals.

2. The comparator is a circuit that compares an analog signal with

another analog signal or reference and outputs a binary signal

based on the comparison. In its simplest form, the comparator can

be considered as a 1-bit analog-to-digital converter.

3. Hence, in the first order sigma-delta modulator, the comparator i.e.

1-bit analog-to-digital converter acts as the quantizer.

+

-


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Digital Filter:-

1. Everything is in Digital domain : Low pass filter + Down sampler.

2. Acts as a low pass filter and removes the high frequency

quantization noise and other remains of high frequency

components.

3. Averages the stream of one bits

4. Finally reduction to original sampling rate Fs from over sampled

rate Fs

5. Higher bit resolution is also achieved


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Decimation:-

SIGMA DELTABLOCK

DECIMATIONFILTER

Analog input 1100000110000011 Avg.= (6/16 )= 0.375

0110

16 - one bit stream

One 4 - bit representation

16:1 Decimation

Over sampledat 16 times


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Sigma Delta - Merits & Demerits:-

1. Merits:-

1. High resolution at Low cost

2. Very efficient noise handling

3. Less stringent Anti-aliasing filter requirements

2. Demerits:-

1. Several clock cycles settling time or latency due to delays in

digital filtering stage

2. Longer conversion time, typically 100000 samples/s for 16-

bit resolution and 1000 samples/s for 24-bit resolution


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Applications:-

1. Process applications

1. Precision data acquisition and measurement

2. Medical instrumentation

2. Temperature measurements

3. Digital Audio CD system applications

4. Latency is the major issue which keeps theprotection industry away from sigma delta ADC


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Conclusion:-

1. Referred More than 5 IEEE papers.

2. ADC.

1. Noise shaping.

2. Achieving High resolution.

3. Low cost, high quality.

4. Fine time resolution.


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My Future Work:-

1. Designing the 8 bit ADC in cadence tool

with following specification.

2. Designing with 90nm technology

3. Positive and Negative rails of 5V and -5V

4. 8-bits of digital resolution.


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References:-

1. Eshraghi, A. & Fiez, T. A comparative analysis of parallel delta-sigma

ADC architectures Circuits and Systems I: Regular Papers, IEEE

Transactions on,2004, 51, 450-458.

2. Arnold R. Feldman, Bernhard E. Boser, and Paul R. Gray. A 13-Bit, 1.4-

MS/s SigmaDelta Modulator for RF Baseband Channel Applications:

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 10,

OCTOBER 1998.

3. B. K. Thandri and J. Silva-Martinez, A 63 dB, 75-mWbandpass RF ADC

at 950 MHz using 3. 8-GHz clock in 0. 25-m SiGe BiCMOS technology,

IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 269279, Feb. 2007.

4. R. Schreier and G. C. Temes, Understanding Delta-Sigma Data

Converters. New York: Wiley-Interscience, 2005.


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design and implementation of sigma-delta analog to digital

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