design and performance analysis of low power digital
DESCRIPTION
GDITRANSCRIPT
-
5/26/2018 Design and Performance Analysis of Low Power Digital
1/16
DESIGN AND PERFORMANCE ANALYSIS OF LOW
POWER DIGITAL CIRCUITS USING GDI
SUBMITTED BY:
POOJA VERMA
ROLL NO -1270679
M.TECH- VLSI DESIGN
CHANDIGARH GROUP OF COLLEGES,LANDRAN
PUNJAB TECHNICAL UNIVERSITY
-
5/26/2018 Design and Performance Analysis of Low Power Digital
2/16
-
5/26/2018 Design and Performance Analysis of Low Power Digital
3/16
Outline
Introduction
Role of VLSI In digital circuits
Gaps in present Study
Objectives
Methodology
3
-
5/26/2018 Design and Performance Analysis of Low Power Digital
4/16
INTRODUCTION
GATE DIFFUSION INPUT (GDI)
It is a new technique of low power digital combinational circuit design.
This technique allows reducing power consumption, propagation delay, area of digital circuits while
maintaining low complexity design .
GDI allows implementation of wide range of complex logic functions using only two transistors.
Basic GDI cell:
-
5/26/2018 Design and Performance Analysis of Low Power Digital
5/16
Advantages of GDI OVER CMOS
Low power circuit design
Allows reducing power consumption.
Reducing propagation delay.
Reducing area of digital circuit.
Maintaining low complexity of logic design.
-
5/26/2018 Design and Performance Analysis of Low Power Digital
6/16
WHY LOW POWER?
Power dissipation limitations come in two ways:-
1.The first is related to cooling considerations when implementing highperformance systems. High-speed circuits dissipate large amounts of energy in a
short amount of time , generating a great deal of heat. This heat needs to be
removed by the package on which integrated circuits are mounted.
2.The second failure of high-power circuits relates to the increasing popularity of
portable electronic devices. Laptop computers, portable video players and
cellular phones all use batteries as a power source. To extend the battery life,
low power operation is desirable in integrated circuits.
-
5/26/2018 Design and Performance Analysis of Low Power Digital
7/16
MODIFIED GATE DIFFUSION
INPUT TECHNIQUE
Mod-GDI CELL
Modified GDI cell contains
a low voltage terminal SP configured to be connected to high constant
voltage (i.e. supply voltage)
a high voltage terminal SN configured to be connected to a low constantvoltage(i.e. ground).
Including terminals these ensures that the Mod-GDI cell can be implemented
with all current CMOS technologies
-
5/26/2018 Design and Performance Analysis of Low Power Digital
8/16
FULL SWING GATE DIFFUSION
INPUT LOGIC TECHNIQUE
This technique is used to implement digital circuits by using GDI full swing
F1 and F2 gates , which are counter parts of standard CMOS NAND and
NOR gate.
The Full Swing GDI technique utilizes a single swing restoration(SR)transistors to improve the output swing of F1 and F2 GDI gates.
Full swing GDI cells are shown below:
-
5/26/2018 Design and Performance Analysis of Low Power Digital
9/16
Logic cell
Switching
Delay(ns)
GDI
Switching
Delay(ns)
Mod-GDI
Switching
Delay(ns)
CMOS
Transistor
count for
GDI cell
Transistor
count for
Mod-GDI
cell
Transistor
count for
CMOS cell
Power
(w)
GDI
Power
(w)
Mod-GDI
Power
(w)
CMOS
OR .200 1.01 1.77 2 2 6 1.286 17.80 25.00
AND .500 1.10 1.54 2 2 6 1.30 17.90 25.00
F1 .280 1.59 2.17 2 2 6 1.35 25.00 48.23
F2 .53 .40 1.70 2 2 6 1.39 25.00 42.27
MUX .50 .50 1.69 2 2 12 1.45 25.00 54.64
NAND .520 .242 .280 4 4 4 .657 .54 .64
NOR .540 .280 .300 4 4 4 .680 .654 .75
XOR .545 .362 .567 4 3 16 1.48 1.23 1.5
XNOR .540 .363 .567 4 3 16 1.50 1.23 1.5
Comparison of GDI techniques and
CMOS from Literature survey
-
5/26/2018 Design and Performance Analysis of Low Power Digital
10/16
Role of VLSI in Digital Circuits
Very large scale integration (VLSI) is the field which involves
packing more and more logic devices into smaller and smaller
areas.
Power dissipation LOW POWER
AREA- GDI instead of CMOS
-
5/26/2018 Design and Performance Analysis of Low Power Digital
11/16
GAPS IN THE PRESENT STUDY
Less work has been carried out for sequential circuits design using GDI
technique.
There has been very less effort done to improve output voltage swings of digital
circuits.
Compatibility of GDI with twin-well CMOS process have not been studied.
Advanced design metrics of GDI cells, such as minimum energy point (MEP)
operation & minimum leakage vector (MLV) are less discussed.
-
5/26/2018 Design and Performance Analysis of Low Power Digital
12/16
OBJECTIVES
1. To design an area efficient and low power digital circuit by using GDI
technique.
2. To design logic gates that that has less transistor count and consume less power.
3. To design radix 4 booth multiplier using these gates .
4. To achieve low power dissipation and less delay for high performance of system.
5. To achieve reduction in sub threshold and gate leakage current of designed
circuit.
-
5/26/2018 Design and Performance Analysis of Low Power Digital
13/16
METHODOLOGY
1. Study of GDI techniques for the design of a low power digital circuit.
2. Comparison between these techniques is done and best technique is selected
which is MGDI.
3. Logic gates are designed using MGDI technique.
4. Radix 4 booth multiplier is designed using MGDI.
4. Various parameters like area count, power dissipation and delay of gates and
multiplier are calculated.
5. Design and simulation of all the circuits have been performed by TANNER
using TSMC BSIM .180m technologies.
-
5/26/2018 Design and Performance Analysis of Low Power Digital
14/16
Publication
I have written a review paper on COMPARATIVE PERFORMANCE
ANALYSIS OF VARIOUS LOW POWER GDI TECHNIQUES FOR DIGITAL
CIRCUITS
-
5/26/2018 Design and Performance Analysis of Low Power Digital
15/16
REFERENCES
[1] N. Weste and K. Eshraghian,Principles of CMOS digital design. Reading, MA: Addison-Wesley, pp. 304307.
[2] J. P. Uyemura,Fundamentals of MOS Digital Integrated Circuits,Reading, Addison-Wesley, pp. 136-137.
[3] Basic VLSI Design by Douglas A.Pucknell Kamran Eshraghian, 3rd edition, 2005 Prentice-Hall India.
[4] Basic Low Power Digital Design; P.R. Panda et al., Power-efficient System Design, DOI 10.1007/978-1-4419-6388-8 2, Springer
Science+Business Media, LLC 2010.[5] Kunal and Nidhi Kedia GDI:" A POWER EFFICIENT METHOD FOR DIGITAL CIRCUITS" ISSN Volume-1, Issue-3, 2012.
[6] Arkadiy Morgenshtein, Viacheslav Yuzhaninov, Alexey Kovshilovsky, Alexander Fish," Full-Swing Gate Diffusion Input logic
Case-study of low-power CLA adder design" INTEGRATION, the VLSI journal ,2013
[7] Pankaj Verma , Ruchi Singh and Y. K. Mishra ,"Modified GDITechnique - A Power EfficientMethod For Digital Circuit Design"
IJECSE,2012.
[8] A. Morgenshtein, I. Shwartz, A. Fish, GateDiffusion Input (GDI) Logic in Standard CMOS Nanoscale Process,2010 IEEE 26th
Convention of Electrical and Engineers in Israel.
[9] Arkadiy Morgenshtein, Alexander Fish, and Israel A. Wagner," Gate-Diffusion Input (GDI): A Power-Efficient Method for Digital
Combinatorial Circuits" ieee transactions on very large scale integration (vlsi) systems, vol. 10, no. 5, october 2002
[10] Soolmaz Abbasalizadeh, Behjat Forouzandeh," Full Adder Design with GDI Cell and Independent Double Gate Transistor"
IEEE,2012.
[11] E.J. Priyanka, S. Vanitha, P.C.Rupa, "Design of GDI based 4-Bit Multiplier using Low Power Adder Cells"International Journal of
Computer Applications (09758887) ,National conference on VSLI and Embedded systems 2013
[12] Kannan, P.M.Prathyusha, K."Implementation of low power RAM in GDI technique with full swing" IEEE,2011.
[13] Moradi. F.Wisland, Mahmoodi, H.,Aunet, S.,Tuan Vu Cao,"ULTRA LOW POWER FULL ADDER TOPOLOGIES" IEEE,2009.
[14] Samiappa Sakthikumaran1, S. Salivahanan, V. S. Kanchana Bhaaskaran2, V. Kavinilavu," A Very Fast and Low Power Carry Select
Adder Circuit" IEEE,2011
[15] Nishad, A.K., Chandel, R." ANALYSIS OF LOW POWER HIGH PERFORMANCE XOR GATE USING GDI
TECHNIQUE."IEEE 2011[16] Sakurai, T,"LOW POWER DIGITAL CIRCUIT DESIGN" Solid-State Circuits Conference, IEEE,2004
[17] Samiappa Sakthikumaran1, S. Salivahanan, V. S. Kanchana Bhaaskaran2, V. Kavinilavu, B. Brindha and C. Vinoth," A Very Fast
and Low Power Carry Select Adder Circuit"IEEE,2011
[18] Hermentha.S,Dhawan, A."Multi-threshold CMOS design for low power digital circuits"IEEE,2008
[19] Dan Wang, Maofeng Yang, Wu Cheng, Xuguang Guan, Zhangming Zhu, Yintang Yang, "Novel Low Power Full Adder Cells in
180nmCMOS Technology" IEEE,2009.
[20] Balasubramanian.P,John, J."Low power digital design using modified GDI method" Design and Test of Integrated Systems in Nano-
scale Technology,2006
http://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Kannan,%20P.M..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Prathyusha,%20K..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Mahmoodi,%20H..QT.&searchWithin=p_Author_Ids:37274843900&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Aunet,%20S..QT.&searchWithin=p_Author_Ids:37282984800&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Tuan%20Vu%20Cao.QT.&searchWithin=p_Author_Ids:37410409200&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Chandel,%20R..QT.&searchWithin=p_Author_Ids:37395023500&newsearch=truehttp://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9372http://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Dhawan,%20A..QT.&searchWithin=p_Author_Ids:37936222000&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.John,%20J..QT.&newsearch=truehttp://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=11202http://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.John,%20J..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.John,%20J..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.John,%20J..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.John,%20J..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.John,%20J..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Dhawan,%20A..QT.&searchWithin=p_Author_Ids:37936222000&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Dhawan,%20A..QT.&searchWithin=p_Author_Ids:37936222000&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Dhawan,%20A..QT.&searchWithin=p_Author_Ids:37936222000&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Dhawan,%20A..QT.&searchWithin=p_Author_Ids:37936222000&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Dhawan,%20A..QT.&searchWithin=p_Author_Ids:37936222000&newsearch=truehttp://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9372http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9372http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9372http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9372http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9372http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9372http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9372http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9372http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9372http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9372http://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Chandel,%20R..QT.&searchWithin=p_Author_Ids:37395023500&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Chandel,%20R..QT.&searchWithin=p_Author_Ids:37395023500&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Chandel,%20R..QT.&searchWithin=p_Author_Ids:37395023500&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Chandel,%20R..QT.&searchWithin=p_Author_Ids:37395023500&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Chandel,%20R..QT.&searchWithin=p_Author_Ids:37395023500&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Tuan%20Vu%20Cao.QT.&searchWithin=p_Author_Ids:37410409200&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Tuan%20Vu%20Cao.QT.&searchWithin=p_Author_Ids:37410409200&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Tuan%20Vu%20Cao.QT.&searchWithin=p_Author_Ids:37410409200&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Tuan%20Vu%20Cao.QT.&searchWithin=p_Author_Ids:37410409200&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Tuan%20Vu%20Cao.QT.&searchWithin=p_Author_Ids:37410409200&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Aunet,%20S..QT.&searchWithin=p_Author_Ids:37282984800&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Aunet,%20S..QT.&searchWithin=p_Author_Ids:37282984800&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Aunet,%20S..QT.&searchWithin=p_Author_Ids:37282984800&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Aunet,%20S..QT.&searchWithin=p_Author_Ids:37282984800&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Aunet,%20S..QT.&searchWithin=p_Author_Ids:37282984800&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Mahmoodi,%20H..QT.&searchWithin=p_Author_Ids:37274843900&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Mahmoodi,%20H..QT.&searchWithin=p_Author_Ids:37274843900&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Mahmoodi,%20H..QT.&searchWithin=p_Author_Ids:37274843900&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Mahmoodi,%20H..QT.&searchWithin=p_Author_Ids:37274843900&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Mahmoodi,%20H..QT.&searchWithin=p_Author_Ids:37274843900&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Prathyusha,%20K..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Prathyusha,%20K..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Prathyusha,%20K..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Prathyusha,%20K..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Prathyusha,%20K..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Kannan,%20P.M..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Kannan,%20P.M..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Kannan,%20P.M..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Kannan,%20P.M..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Kannan,%20P.M..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Kannan,%20P.M..QT.&newsearch=truehttp://ieeexplore.ieee.org/search/searchresult.jsp?searchWithin=p_Authors:.QT.Kannan,%20P.M..QT.&newsearch=true -
5/26/2018 Design and Performance Analysis of Low Power Digital
16/16