design example binary multiplier. block diagram asm chart
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Design exampleDesign example
Binary MultiplierBinary Multiplier
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Block diagramBlock diagram
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ASM chartASM chart
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Numerical example Numerical example
Multiplicand B = 1011
C A Q P
Multiplier Q 0 00000 10011 101
Q0 = 1 ; 加 B 10111
First partial product 0 10111 100
Shift right CAQ 0 01011 11001
Q0 = 1 ; add B 10111
Second partial product 1 00010 011
Shift right CAQ 0 10001 01100
Q0 = 0 ; shift right CAQ 0 01000 10110 010
Q0 = 0 ; shift right CAQ 0 00100 01011 001
Q0 = 1 ; add B 10111
Fifth partial product 0 11011
Shift right CAQ 0 01101 10101 000
Final product in AQ = 0110110101
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Control logicControl logic
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Control blockControl block
• L is required for loading the sum into register A if Q0=1 while in state T2
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State assignmentState assignment
Table 8-5 State assignment for control
Btate Binary Gray code One-hot
T0 00 00 0001
T1 01 01 0010
T2 10 11 0100
T3 11 10 1000
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State table for control circuitState table for control circuit
Present
state
Input Next state Output
G1 G0 S Z G1 G0 T0 T1 T2 T3
0 0 0 X 0 0 1 0 0 0
0 0 1 X 0 1 0 1 0 0
0 1 X X 1 0 0 0 1 0
1 0 X X 1 1 0 0 0 1
1 1 X 0 1 0 0 0 1 0
1 1 X 1 0 0 1 0 0 0
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Logic diagram of controlLogic diagram of control
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One F.F. per stateOne F.F. per state
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HDL descriptionHDL descriptionmodule mltp(S,CLK,Clr,Binput.Qinput,C,A,Q,P) ; input S,CLK,Cir; input [4:01 Binput.Qinput; //Data inputs output C; output [4:0] A,Q; output [2:0] P;reg C; reg [4:0] A,Q,B; reg [2:0] P; reg [1:0] pstate, nstate; //control register parameter T0=2'b00, Tl=2'b01, T2=2'bl0, T3=2'bll;
wire Z; assign Z = ~|P; //Check for zero
always @(negedge CLK or negedgo Cir) if (~Clr) pstate = T0; else pstate <= nstate; always @(S or Z or pstate) case (pstate) T0: if (S) nstate = Tl; else nstate = T0; Tl: nstate = T2; T2: nstate = T3 ; T3: if (Z) nstate = TO; else nstate = T2; endcase
HDL Example 8-5
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always @(negedge CLK)case (pstate)TO: B <= Binput; //Input multiplicandTl: beginA <= 5'b00000;C <= 1'b0;P <= 3~b101; //Initialize counter to n=5Q <= Qinput; //Input multiplierendT2: beginP <= P - 3'bOOl; //Decrement counterif (Q[0]) {C,A} <= A + B; //Add multiplicandendT3: beginC <= 1'b0; //Clear CA <= {C,A[4:1]}; //Shift right AQ <= {A[0],Q[4:l]}; //Shift right Qendendcaseendnodule
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HDL Example 8-6 module test_mltp; reg S,CLK,Clr; reg [4:0] Binput,Qinput;
wire C; wire [4:0] A,Q; wire [2:0] P;
mitp mp(S,CLK,Clr,Binput,Qinput,C,A,Q,P), initiAl begin S=0; CLK=0; Clr=0; #5 S=l; Clr=l; Binput = 5'b10111; Qinput = 5'b10011; #15 S = 0; end initial begin repeat (26) #5 CLK = ~CLK; end
always @(negedge CLK) $strobe("C=%b A=%b Q=%b P=%b time=%0d",C,A,Q,P,$time) endmodule
Test bench