multiplication discussion 11.2. multiplier binary multiplication 4 x 4 multiplier

Multiplication

Discussion 11.2

Multiplier

• Binary Multiplication

• 4 x 4 Multiplier

Binary Multiplication

Table 10.8Binary Multiplication Table

0 10 0 01 0 1

Binary Multiplication

13x 12 26 13 156

1101 1100 0000 0000 1101 110110011100

9 C = 156

Table 10.9Hexadecimal Multiplication Table

0 1 2 3 4 5 6 7 8 9 A B C D E F0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 1 2 3 4 5 6 7 8 9 A B C D E F2 4 6 8 A C E 10 12 14 16 18 1A 1C 1E3 9 C F 12 15 18 1B 1E 21 24 27 2A 2D4 10 14 18 1C 20 24 28 2C 30 34 38 3C5 19 1E 23 28 2D 32 37 3C 41 46 4B6 24 2A 30 36 3C 42 48 4E 54 5A7 31 38 3F 46 4D 54 5B 62 698 40 48 50 58 60 68 70 789 51 5A 63 6C 75 7E 87A 64 6E 78 82 8C 96B 79 84 8F 9A A5C 90 9C A8 B4D A9 B6 C3E C4 D2F E1

Hex Multiplication

Hex MultiplicationTable 10.9

Hexadecimal Multiplication Table0 1 2 3 4 5 6 7 8 9 A B C D E F

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01 1 2 3 4 5 6 7 8 9 A B C D E F2 4 6 8 A C E 10 12 14 16 18 1A 1C 1E3 9 C F 12 15 18 1B 1E 21 24 27 2A 2D4 10 14 18 1C 20 24 28 2C 30 34 38 3C5 19 1E 23 28 2D 32 37 3C 41 46 4B6 24 2A 30 36 3C 42 48 4E 54 5A7 31 38 3F 46 4D 54 5B 62 698 40 48 50 58 60 68 70 789 51 5A 63 6C 75 7E 87A 64 6E 78 82 8C 96B 79 84 8F 9A A5C 90 9C A8 B4D A9 B6 C3E C4 D2F E1

61x 905490

3D x 5A 262 A x D = 82, A x 3 = 1E + 8 = 26 131 5 x D = 41, 5 x 3 = F + 4 = 13 157216 = 549010

Dec Hex

Multiplication

13x11 1313 143 = 8Fh

1101 x1011 1101 1101 100111 0000 100111 1101 10001111

library IEEE;use IEEE.std_logic_1164.all;package std_logic_arith is type UNSIGNED is array (NATURAL range <>) of STD_LOGIC; type SIGNED is array (NATURAL range <>) of STD_LOGIC; subtype SMALL_INT is INTEGER range 0 to 1;

function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED; function "*"(L: SIGNED; R: SIGNED) return SIGNED; function "*"(L: SIGNED; R: UNSIGNED) return SIGNED; function "*"(L: UNSIGNED; R: SIGNED) return SIGNED; function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR; function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR; function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR; function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;

std_logic_arith.vhd

function mult(A,B: UNSIGNED) return UNSIGNED is constant msb: integer:=A'length+B'length-1; variable BA: UNSIGNED(msb downto 0); variable PA: UNSIGNED(msb downto 0);

begin if (A(A'left) = 'X' or B(B'left) = 'X') then

PA := (others => 'X'); return(PA);

end if; PA := (others => '0'); BA := CONV_UNSIGNED(B,(A'length+B'length)); for i in 0 to A'length-1 loop

if A(i) = '1' then PA := PA+BA; end if;

for j in msb downto 1 loop BA(j):=BA(j-1);

end loop; BA(0) := '0'; end loop; return(PA); end;

1101 x1011 1101 1101 100111 0000 100111 1101 10001111

function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is

begin return mult(CONV_UNSIGNED(L, L'length), CONV_UNSIGNED(R, R'length));

end;

library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;

std_logic_unsigned.vhd

package STD_LOGIC_UNSIGNED is

function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;

function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is

constant length: INTEGER := maximum(L'length, R'length); variable result :

STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0); begin

result := UNSIGNED(L) * UNSIGNED(R);

return std_logic_vector(result); end;

library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;package body STD_LOGIC_UNSIGNED is

std_logic_unsigned.vhd (cont.)

Testing the * operator

Use BTN(0) to load SWinto Ra and Rb and thendisplay product in Rp

Control signals:aloadbloadploaddmselm2sel(1:0) x7segb

clr

cclk

x

*B A

P

16p

bs

Raregc

aload

8

8

ain

as

clr

clkRbregc

bload

8

8

bin

SW(7:0)

clr

clk

0 & as

U5 (mux4g)

U1 (dmux2g)

Rpregc

ploadclr

clk

8

0 & bs

16 1616

AN(3:0) AtoG(6:0)

16

a16 b16

pout

dmsel

m2sel(1:0)

Three consecutivepushings of BTN(0)

Control signals:aloadbloadploaddmselm2sel(1:0)

sA

sB

sC

sD

sE

sF

Wait for BTN(0) up

BTN(0)’

Wait for BTN(0) down

BTN(0)

Wait for BTN(0) up

Wait for BTN(0) up



BTN(0)

BTN(0)

BTN(0)

BTN(0)

BTN(0)

BTN(0)’

BTN(0)’

BTN(0)’

BTN(0)’

BTN(0)’

VHDLCanonical Sequential Network

Sta

te R

egis

ter

Com

bina

tion

alN

etw

ork

x(t)

s(t+1) s(t)

z(t)clk

init

present state

present input

nextstate

present output

process(clk, init)

process(present_state, x)

-- Title: Mult Control Unit

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity mult_control is

port (

clr: in STD_LOGIC;

clk: in STD_LOGIC;

BTN0: in STD_LOGIC;

m2sel: out STD_LOGIC_VECTOR (1 downto 0);

aload, bload, dmsel: out STD_LOGIC;

pload: out STD_LOGIC

);

end mult_control;

architecture mult_control_arch of mult_control is

type state_type is (sA, sB, sC, sD, sE, sF);

signal current_state, next_state: state_type;

begin

C1: process(current_state, BTN0)

begin

-- Initialize all outputs

pload <= '0';

dmsel <= '0';

aload <= '0';

bload <= '0';

m2sel <= "00";

mult_control.vhd

case current_state is

when sA => --wait for BTN0 up

if BTN0 = '1' then

next_state <= sA;

m2sel <= "11";

else

next_state <= sB;

end if;

when sB => --wait for BTN0 down

if BTN0 = '1' then

next_state <= sC;

aload <= '1'; -- A <- SW

m2sel <= "00";

else

next_state <= sB;

m2sel <= "11";

end if;

sA

sB

sC

sD

sE

sF

Wait for BTN(0) up

BTN(0)’


BTN(0)

Wait for BTN(0) up

Wait for BTN(0) up



BTN(0)

BTN(0)

BTN(0)

BTN(0)

BTN(0)

BTN(0)’

BTN(0)’

BTN(0)’

BTN(0)’

BTN(0)’

when sC => --wait for BTN0 up

if BTN0 = '1' then

next_state <= sC;

m2sel <= "00";

else

next_state <= sD;

end if;

when sD => --wait for BTN0 down

if BTN0 = '1' then

next_state <= sE;

dmsel <= '1';

bload <= '1'; -- B <- SW

m2sel <= "01";

else

next_state <= sD;

m2sel <= "00";

end if;

sA

sB

sC

sD

sE

sF

Wait for BTN(0) up

BTN(0)’


BTN(0)

Wait for BTN(0) up

Wait for BTN(0) up



BTN(0)

BTN(0)

BTN(0)

BTN(0)

BTN(0)

BTN(0)’

BTN(0)’

BTN(0)’

BTN(0)’

BTN(0)’

when sE => --wait for BTN0 up

if BTN0 = '1' then

next_state <= sE;

m2sel <= "01";

else

next_state <= sF;

end if;

when sF => --wait for BTN0 down

if BTN0 = '1' then

next_state <= sA;

pload <= '1';

m2sel <= "11";

else

next_state <= sF;

m2sel <= "01";

end if;

end case;

end process C1;

sA

sB

sC

sD

sE

sF

Wait for BTN(0) up

BTN(0)’


BTN(0)

Wait for BTN(0) up

Wait for BTN(0) up



BTN(0)

BTN(0)

BTN(0)

BTN(0)

BTN(0)

BTN(0)’

BTN(0)’

BTN(0)’

BTN(0)’

BTN(0)’

statereg: process(clk, clr) -- the state register

begin

if clr = '1' then

current_state <= sA;

elsif (clk'event and clk = '1') then

current_state <= next_state;

end if;

end process statereg;

end mult_control_arch;

-- Title: Multiply Test

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.std_logic_unsigned.all;

use work.mult_components.all;

entity mult is

port(

mclk : in STD_LOGIC;

SW : in STD_LOGIC_VECTOR(7 downto 0);

BTN: in STD_LOGIC_VECTOR(3 downto 0);

LD: out STD_LOGIC_VECTOR(7 downto 0);

AtoG : out STD_LOGIC_VECTOR(6 downto 0);

AN : out STD_LOGIC_VECTOR(3 downto 0)

);

end mult;

mult.vhd

architecture mult_arch of mult is

signal r, p, pout, x, b16, a16: std_logic_vector(15 downto 0);

signal as, bs, ain, bin: std_logic_vector(7 downto 0);

signal clr, clk, cclk, bnbuf: std_logic;

signal clkdiv: std_logic_vector(23 downto 0);

signal aload, bload, pload, dmsel: STD_LOGIC;

signal m2sel: STD_LOGIC_VECTOR (1 downto 0);

constant bus_width8: positive := 8;

constant bus_width16: positive := 16;

x7segbclr

cclk

x

*B A

P

16p

bs

Raregc

aload

8

8

ain

as

clr

clkRbregc

bload

8

8

bin

SW(7:0)

clr

clk

0 & as

U5 (mux4g)

U1 (dmux2g)

Rpregc

ploadclr

clk

8

0 & bs

16 1616

AN(3:0) AtoG(6:0)

16

a16 b16

pout

dmsel

m2sel(1:0)

begin

clr <= BTN(3);

-- Divide the master clock (50Mhz)

process (mclk)

begin

if mclk = '1' and mclk'Event then

clkdiv <= clkdiv + 1;

end if;

end process;

clk <= clkdiv(0); -- 25 MHz

cclk <= clkdiv(17); -- 190 Hz

a16 <= "00000000" & as;

b16 <= "00000000" & bs;

p <= as * bs;

U1: dmux2g generic map(width => bus_width8) port map

(y => SW, a => ain, b => bin, sel => dmsel);

U2a: reg generic map(width => bus_width8) port map

(d => ain, load => aload, clr => clr, clk =>clk, q => as);

U3b: reg generic map(width => bus_width8) port map

(d => bin, load => bload, clr => clr, clk =>clk, q => bs);

U4p: reg generic map(width => bus_width16) port map

(d => p, load => pload, clr => clr, clk =>clk, q => pout);

U5: mux4g generic map(width => bus_width16) port map

(a => a16, b => b16, c => pout, d => pout, sel => m2sel,

y => x);

U7: x7segb port map

(x => x, cclk => cclk, clr => clr, AtoG => AtoG, AN => AN);

U8: mult_control port map

(clr => clr, clk => clk, BTN0 => BTN(0), m2sel => m2sel,

aload => aload, bload => bload, dmsel => dmsel,

pload => pload);

LD <= SW;

end mult_arch;

multiplication discussion 11.2. multiplier binary multiplication 4 x 4 multiplier

Documents

unsigned return std

vector slide

logic type

logic pload

package std

logic btn0

logic clk

logic end mult