design for nanomanufacturing at uc berkeley - a chip-scale … · 2013. 10. 27. · a chip-scale...

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A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists and resist-stamp boundary conditions 23 October 2013 Hayden Taylor* and Niswan Dhakal Nanyang Technological University, Singapore Joel Yang and Zhu Di Institute for Materials Research and Engineering, Singapore * [email protected]

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Page 1: Design for Nanomanufacturing at UC Berkeley - A chip-scale … · 2013. 10. 27. · A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists

A chip-scale imprinter with integrated optical

interference for calibrating models of NIL

resists and resist-stamp boundary conditions

23 October 2013

Hayden Taylor* and Niswan Dhakal

Nanyang Technological University, Singapore

Joel Yang and Zhu Di

Institute for Materials Research and Engineering, Singapore

* [email protected]

Page 2: Design for Nanomanufacturing at UC Berkeley - A chip-scale … · 2013. 10. 27. · A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists

Outline

2

• Resist model calibration by fitting

simulations to imprint experiments

• The need for new tools to characterise

resist–stamp material combinations

• Real-time optical monitoring of imprint

• Potential RLT sensing enhancements:

• Plasmonic

• Ellipsometric

• Potential applications of real-time

optical imprint monitoring:

• Endpoint detection

• Process control

• Defect detection (including non-fill)

Page 3: Design for Nanomanufacturing at UC Berkeley - A chip-scale … · 2013. 10. 27. · A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists

1 Taylor NNT 2009, 2011; 2 Taylor SPIE 7641 2010; 3 Boning et al. NNT 2010

0

0.5

1

Pattern abstraction

De

ns

ity

Stamp

Resist

Wafer

Stamp deflections

Residual thickness (RLT) nonuniformity

Incomplete cavity filling

Lateral resist flow RLT homogenization

Stamp’s load response (bending, indentation)

Resist

Stamp

Resist surface’s impulse response

Resist

Substrate

Example questions:

Does changing stamp material affect

residual layer uniformity? 1,2

Can ‘dummy fill’ accelerate stamp cavity filling? 3

92

99

10

165

Elastomer Silicon

(nm)

Simulations need to be highly scalable

At least 103 times

faster than FEM Can trade off spatial

resolution and speed

101

102

103

104

102

103

104

Simulation size, N

~O(N2logN)

101

N

Tim

e (

s)

1

2

3

4

3

Our existing simulation technique quickly finds RLT and cavity-filling distributions

Page 4: Design for Nanomanufacturing at UC Berkeley - A chip-scale … · 2013. 10. 27. · A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists

A

B

C

D

E

F

G

H

The NIL simulation technique has been experimentally validated

1 mm

Silicon test stamp:

Cavities

(~500 nm deep)

Protrusions

C

A

E

G

D

B

F

H

5

Page 5: Design for Nanomanufacturing at UC Berkeley - A chip-scale … · 2013. 10. 27. · A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists

The technique has been validated for five thermoplastic materials

8 8

Page 6: Design for Nanomanufacturing at UC Berkeley - A chip-scale … · 2013. 10. 27. · A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists

Nanoscale experiments may involve substantial slip between resist and stamp

9 9

Assuming no slip between resist and

stamp or substrate

Page 7: Design for Nanomanufacturing at UC Berkeley - A chip-scale … · 2013. 10. 27. · A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists

The imprinting rate will depend strongly on any slip between resist and stamp/substrate

10

d𝑟

d𝑡= −

𝑟3𝑝0

4𝑘𝜂0𝑎02 1 − 2𝛿 +

𝑟

𝑎0

2

1 + 2𝛿

−1

Laun, J. Non-Newtonian Fluid

Mechanics 81 (1999) 1-15 10

Page 8: Design for Nanomanufacturing at UC Berkeley - A chip-scale … · 2013. 10. 27. · A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists

Real-time observation of evolving RLT could accelerate material/stamp characterisation

100 µm

Page 9: Design for Nanomanufacturing at UC Berkeley - A chip-scale … · 2013. 10. 27. · A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists

Real-time observation of evolving RLT could accelerate material/stamp characterisation

Simulations

Page 10: Design for Nanomanufacturing at UC Berkeley - A chip-scale … · 2013. 10. 27. · A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists

RLT–colour relationships are calibrated using a known stamp topography

13

Radius = 3.1 mm

Silicon

150 µm

Resist

Stamp

Intensity gradient

> 1/nm

Page 11: Design for Nanomanufacturing at UC Berkeley - A chip-scale … · 2013. 10. 27. · A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists

Videos of the imprinting process allow the temporal response of resist to be extracted

14

• Material:

MRT mr-UVCur-21

• Stamp-average

pressure 20 kPa

• Consistent with

viscosity ~ 7 Pa.s

100 µm

Page 12: Design for Nanomanufacturing at UC Berkeley - A chip-scale … · 2013. 10. 27. · A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists

If features are sub-wavelength, plasmonic effects could enhance RLT detection

Large features

25 nm-pitch dot array

D

h

g

h

RLT

h = D = 16 nm

g = 9 nm

Silicon

Resist, n = 1.52

Quartz, n = 1.45

10 nm gold Simulated

reflectivity

spectra

RLT

E-field

intensity

(Joel Yang + Zhu Di)

Page 13: Design for Nanomanufacturing at UC Berkeley - A chip-scale … · 2013. 10. 27. · A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists

An anti-reflective stamp coating and light polarisation could enhance RLT contrast

16

DLC: diamond-like carbon (n ~ 2.09). “Polarised” means with crossed polarisers

Contrast: relative change in intensity for a 1 nm change in RLT about a given RLT

Substrate-enhanced ellipsometric contrast: Ausserré, Optics Express, 15 8329 (2007)

Page 14: Design for Nanomanufacturing at UC Berkeley - A chip-scale … · 2013. 10. 27. · A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists

Potential applications include endpoint detection and cavity filling monitoring

17

• Endpoint detection

• Feedback control in R2R processing

• Cavity filling

• Stamp inspection/defect detection

• Probing of complex fluids (e.g. biological samples)

100 µm

Partially

filled

cavity

100 µm

Resist

residue

Page 15: Design for Nanomanufacturing at UC Berkeley - A chip-scale … · 2013. 10. 27. · A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists

Conclusions and outlook

18

• Resist rheological behaviour can be extracted

from nanoscale imprint experiments

• Resist-stamp boundary conditions are critical

and require characterising

• Real-time measurement of RLT can be

accomplished interferometrically using simple

white light microscopy

• Optical RLT measurement sensitivity can be

tuned using plasmonic or ellipsometric

approaches

• Real-time RLT measurement could be applied to

improve NIL yield and throughput

Page 16: Design for Nanomanufacturing at UC Berkeley - A chip-scale … · 2013. 10. 27. · A chip-scale imprinter with integrated optical interference for calibrating models of NIL resists

Collaborators and acknowledgements

19

• AMO, Germany • Christian Moormann

• Ulrich Plachetka

• Microresist Technology, Germany • Arne Schleunitz

• Marko Vogler

• Freimut Reuther

• IMRE, Singapore • Goh Wei Peng

• NTU, Singapore • Tan Boon Hwee

• IBN, Singapore • Ciprian Iliescu

• Trinity College Dublin • Graham Cross