Design Index ：16bit

Which is the optimal ADC ?

Incremental Data Converter

Date ： 2013.03.30TJIC Design Center Battery Management

Reporter ： Sihai Chen

Contents

Introduction1

Incremental data converter2

Extensions of First-order Converter3

Properties of IDC4

Design Example5

Introduction

ADC is extensively used.

ApplicationRequirements

Resolution Bandwidth Power-Consumption

Microcontrollers Low ~ Med Low ~ Med Low ~ Med

LF Measurement High Low ~ Med Low ~ Med

Sensor( - arrays) High Low ~ Med Low

Audio High Med N/A or Low

Control Med ~ High Low ~ Med N/A

Video Med ~ High High N/A

HF, microwave Med High N/ATelecommunication Med High N/A or Low

Table 1.1 A/D converter requirements of different applications

Introduction

• Application requirements ： high resolution high speed simple hardware low power- and area-consumption insensitivity of environmental effects

• High resolution limitations analog elements matching switching-noise

Introduction

ApplicationArchitecture

Nyquist-rate Oversampling

Microcontroller Successive approx, Algorithmic/Cyclic N/A

dc, LF Measurement, Biomedical app

Dual-slope, Voltage-to- frequency IDC

Sensor(-arrays) Dual-slope IDCAudio Successive approx Simple oversampling ΣΔ

Control Successive approx, Algorithmic/ Cyclic N/A

Video Flash, Pipelined Low-OSR ΣΔ

HF, microwave Flash, Pipelined Bandpass ΣΔ

Telecommunication Flash, Successive approx ΣΔ

Table 1.2 Classification of different A/D converter architecture

Introduction

• Characteristics of IDC Converter speed to resolution Insensitivity of analog elements matching High resolution Low~Med bandwidth Various architectures to make trade-off Good performance for dc measurements sensitive to offset, linearity, stability

Incremental Data Converter

• 1978, Plassche introduced the structure of first-order incremental data converter for the first time.

• 1985, Robert and Valencic introduced a similar structure with more theoretical details in a low-voltage CMOS environment, naming the converter “incremental A/D converter”.

• 2004, Markus introduced the modified IDC, and clearly explained the theory and applications of IDC, naming “incremental ΔΣ converter”.

Incremental Data Converter

• First-order incremental A/D converterA hybrid between dual-slope converter and ΔΣ one

Figure2.1 Block diagram of the Dual-Slope converter

Incremental Data Converter

• First-order incremental A/D converterA hybrid between dual-slope converter and ΔΣ one

Figure2.2 Block diagram of the first-order ΔΣ converter

ADCu V∫-

DAC

Incremental Data Converter

• First-order incremental A/D converterA hybrid between dual-slope converter and ΔΣ one

Figure2.3 Block diagram of the Dual-Slope converter

Incremental Data Converter

• How dual-slope A/D worksTwo-cycle mode:a) First-cycle

b) Second-cycle

So, there is

0inV V NT

0refV V nT

+in refnV VN N

Note:bit

bit

bit

2

2

2

n

n

n

N

n

error

Question1 ： How to enhance the resolution of Dual-slope A/D converter ？（ Clue: ε=? ）

Incremental Data Converter

• How First-order IDC worksAt the (N+1)th sampling,

Obviously ，After ,

Vin∈(0, Vref), -Vref=0; Vin (-∈ Vref, Vref), -Vref= -Vref To be easily understand, - Vref=0.

[ 1] in out refV N N V N V *[ ] ,ref in refV V N V V N

bit2nN

[ 1] [ 1,1]2 ( ) ,ref

bitnout in ref V N VN V V (*)

Incremental Data Converter

• In an ideal A/D converter,

• Rearranging Eq.(*),

• That is,

( ), ( 0.5,0.5]in lsb outV V D q q

[ 1]( ( ))2 bit

refin outn

ref

V V NV NV

2

[ 1]

bit

reflsb n

out out

ref

VV

D NV Nq

V

Conclusion:bit

bit

2[ 1]

2

n

n

NV Nerror

Question2 ： How to enhance the resolution of incremental A/D converter ？

Incremental Data Converter

• For the Bipolar operation, (Vin (-∈ Vref,Vref), -Vref= -Vref)

• after N cycles,

• and ,

1

1 [ 1]N

in i refi

V d V V N NN

1

21

[ 1]

bit

reflsb n

N

out ii

ref

VV

D dN

V NqV

bit

bit

2[ 1]

2

n

n

NV Nerror

Extensions of First-order Converter

• The key requirements of extensions:a) Fastb) High resolution

• Actually, it means:

2 bitnN b 0 1, 0, 0b

(3-1)

Extensions of First-order Converter

• Depending on the Eq.(3-1),a) α=1, β>0,b>0;

Refining the Quantization Noise (or extended counting conversion)

b) 0<α< 1, β=0,b=0;① Different Architecture② High-order Modulators

Extensions of First-order Converter

• Refining the Quantization Noise First-order IDC

Refine the residual signal

1

[ 1]Nref

in ii ref

V V NV dN V

bitbit

[ 1]22

nn

V NN error ，

[ 1] 12 R R Rn

ref

V N N qV

2

12 2 2

nbit

bit bit R bit R

ref ref ref Rin i Rn n n n n

i

V V V qV d N

High nbit bit Low nR bit error

Extensions of First-order Converter

Optimal ArchitectureFirst-order IDC(3~5bit) + Cyclic(8~10bit)

2 IDCncycles

Extensions of First-order Converter

Optimal ArchitectureFirst-order IDC(3~5bit) + Cyclic(8~10bit)

2 IDCncycliccycles n

Extensions of First-order Converter

Other Architecturesa) Multi-bit ADC

Refine the quantization in every cycleb) Two-steps algorithmic conversion

First step: MSB nbit/2Second step: LSB nbit/2Total cycles: 22 2

nbit

Extensions of First-order Converter

• Refine the Quantization NoiseFirst-order IDCCIFF High-order IDCDual-slope converterSingle-slope converterCyclic converter SAR converter Flash(Pipeline) converter

12 2

2

bit R

bit R

in out R Rn n

Rn n

VV D D q

Verror q

Extensions of First-order Converter

• Refine the Quantization Noise

ADC Residue ADC Multiplexing Cycles

IDCFirst-order Cyclic A

M-order Cyclic N/A

Dual-slope Cyclic A

Sing-slope Cyclic A

Cyclic Flash A

2 MSBnLSBn

/2 MSBn mLSBn

2 2 MSBnLSBn

2 MSBnLSBn

2 LSBnMSBn

Extensions of First-order Converter

• Different ArchitectureMASH(multi-stage noise shaping)

1z-1

-U

V

ADC1z-1

2

DAC

1z-1

-ADC1

z-1

2

DAC

1H (z)

2H (z)

Extensions of First-order Converter

• High-order ModulatorTo be easily understand, here is a simple

architecture.Low-distortion CIFF second-order IDC

u dout比较器

Reset

1

11z

z

积分器

Reset

1

11z

z

积分器

Reset

2

1

11 z

滤波器

Reset

1

11 z

滤波器

diV1 V2

Extensions of First-order Converter

• How it worksGiven the reset signal,V1[0]= V2[0]=0.

u比较器

1

11z

z

积分器

Reset

1

11z

z

积分器

Reset

2

diV1 V2

1 1 0 0

1 1 1

10 0 0

2 1 2 1

2 1 2 1 1

1

2 10

[1] [0] [0] = [0]1 1

[ ] [ ] = ( [ ] )1 1

[1] [0] [0] [0][2] [1] [1] [1] [0]

[ ] [ ] ( [ ] )1

ref refin in

N N Nref ref

in i in ii i i

Nref

in ik i

V VV V V d V d

l l

V VV N V i d V i d

l l

V V V VV V V V V

VV N V k V i d

l

1 1

0 0

N k

k

Time-DomainZ-Domain

Extensions of First-order Converter

• How it works

Vin is a constant,

That is,

u比较器

1

11z

z

积分器

Reset

1

11z

z

积分器

Reset

2

diV1 V21 1

20 0

[ ] ( [ ] )1

N kref

in ik i

VV N V i d

l

1 1

20 0

( 1)[ ]2! 1

N kref

in ik i

VN NV N V dl

1 12

0 0

1

1

2 [ ]=( 1)

N k

in ik i

ref

ref

Vl

Vl

V NV dN N

Extensions of First-order Converter

• How it works

The bondage of Vin is ±Vmax , so the Vlsb:

Rearranging,

1 12

0 0

1

1

2 [ ]=( 1)

N k

in ik i

ref

ref

Vl

Vl

V NV dN N

max2

2 2 ( 1) ( 1)bit

reflsbn

VV Vl N N

/2max

maxmax

2 2 ,( 1)

bitn

ref

VN UVU l

Extensions of First-order Converter

• High-order Modulators

Where La is the order, generally La ≤ 3.max

2 !( 1) 2

bitn

LaLa LaN

U l

max

maxref

VUV

Extensions of First-order Converter

• Depending on the Eq.• nbit=16, Umax=0.5, l=2• N=92

• Actually, Nactual>>N=92

Properties of IDC

a) “Dead-Zones”b) Vmax

c) Stabilityd) Offsete) Line frequency noisef) Decimation filter

Properties of IDC

a) “Dead-Zones”b) Vmax

Properties of IDC

• Stability*

The higher the order is, the more instability the modulator is.

There is few paper discussing about the stability of modulator, especially incremental ΔΣ modulator, which is extremely significant.

Generally, scaling of the coefficients makes sure that the modulator is stable.

[ ] in refV N V V ， 1, 1

Properties of IDC

• Offset Extremely sensitive to offset

Voffset remains constant, but Vinj is difficult to evaluate.

Methodsa) Auto-zeroingb) Choppingc) CDSd) Fractal sequencing

int

soffset inj

cV V V

c

offset lsbV V

Properties of IDC

a) Line frequency noise S/H and the error of S/H Periodic noise

b) Decimation filter CoI filter Sinc filter Optimal filter Canceling periodic noise

Properties of IDC

Design Example

• Design index12bitVin [-0.3,5]∈VDD=5VCycles<1000

• Optimal preferencesArchitecture: low-distortion CIFF

second-order 1-bit modulatorBipolar inputSC fully-differential circuitsFractal sequencingVDD=5VVcm=2.5V>13bitVin+ [1.175, 3.825]∈Vref=5, -Vref=0Scaling of coefficients

Design Example

• Depending on the preferences:

• Cycles: N=256• Output swing of OTA: 0.3~4.7V, the key

limitation of stable.

/2 6.5

max

2 2 2 2= =176( 1) 0.53 1

bitn

NU l

maxmax

1.325= =0.532.5ref

VUV

max[ ] 2.2 3.825ref inV N V V

Design Example

• Model of second-order modulator:

Design Example

• Architecture circuits

Design Example

• Simulate results: offset=0

-1 0 1 2 3 4 5 6

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

The Quantization Error of Battery Voltage With Incremental ΣΔADC

error of Vlsberror distribution

Battery Voltage /V

Error of

Vlsb/1

Error Distribution

/mV

Note:Given the data symmetrically dis-tributed at 2.35, the data below 2.35 is calculated from the other side . The -0.1 and -1.15 points are simulated to prove the symme-try.

Vref+=5V,Vref-=0V;offset=0;cycles=256 (ideal bit=14)

Design bit=13,Vlsb=0.75mV

-1 0 1 2 3 4 5 6

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5

0.6

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0.5The Quantization Error of Battery Voltage With Incremental ΣΔADC

error of Vlsberror distribution

Battery Voltage /V

Error of

Vlsb/1

Error Distribution

/mV

Note:All the points in the illustration are simulated.

Vref+=5V,Vref-=0V;offset=10mV;cycles=256 (ideal bit=14)

Design bit=13,Vlsb=0.75mV

Design Example

• Simulate results: offset=10mV

Thank you for your attentions.

The End