“design of a debug module for mips processor”

8/14/2019 Design of a Debug Module for Mips Processor.

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Design of a

Debug Module

for Mips

Processor.

Abstract:

This project describes about the design

and application of a functional verification

methodology to MIPS-LITE processor.

The processor is a simplified version of

MIPS architecture, with single-cycle

instructions. The instruction set of the

processor specified as input to this

project. The data path and control units

of the processor are defined to realize all

the five steps of instruction fetch,

decode, operand fetch, executes, and

store. The verification will be done

concurrently along with the design of the

various modules of the processor. A

Debug module will be designed to test

the processor on single instruction

entered through a keyboard in machine

language. The cache and external

peripherals such as PWM and TIMER

will be added to the system to increase

the functionality..

2.00 Introduction

2.10 Purpose

The purpose of doing this project is to

study and design a debug module for

the MIPS-LITE processor.

2.20 Scope

The scope of the project is to analyze

the instruction format and set of the

MIPS-LITE processor and feed the

values such as Opcode, Source and

Destination operands by the Debug

module and display the Processor

result in the LCD display.

Top Level Block diagram

The hardware block diagram is

shown below. The pin description is

shown in following table.

Processor module: The processor is

a simple version of MIPS processor.

The detail design of this single cycle

MIPS processor is explained in

Reference-1.The signals of the

processor module is given in Table-1.


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3.0 PROCESSOR MODULE PIN

DESCRIPTION

S.NO NAME I/O WIDTH DESCRIPTION

1. RST EXT I 1 ACTIVE LOW RESET

2. MASTERCLOCK

I 1 CLOCK

3. HALTPROC

I 1 PRCOESSOREXCEPTION HALT,ACTIVE HIGH

4. WAIT I 1 PROCESSOR WAIT,ACTIVE LOW

5. BUSY O 1 PROCESSOR BUSY,ACTIVE HIGH

6. ADD_IM O 10 ADDRESS OFINSTRUCTION ROM

7. DATA_IM I 37 DATA OFINSTRUCTION ROM

8. ADD_DM O 16 ADDRESS OUTPUTFOR DATA MEMORY

9. DATA_DM O 16 DATA OUTPUT FORDATA MEMORY

10. READ_DM O 1 READ CONTROLSIGNAL OF DATAMEMORY

11. WRITE_DM

O 1 WRITE CONTROLSIGNAL OF DATAMEMORY

12. SFR_ENABLE

I 1 SPECIAL FUNCTIONREGISTER ENABLE

13. SFR_READ

I 1 SPECIAL FUNCTIONREGISTER READ

14. SFR_DATA O 16 SPECIAL FUNCTIONREGISTER DATA

15. OPCODEREAD

O 1 READ SIGNAL OF EXT.INSTRUCTION ROM

16. ADDRESSCOUNTER

O 10 PROCESSOR BUSY,ACTIVE HIGH

17. PWM_OUT O 1 PWM OUTPUT

Debug Module: The Debug module

is used to feed instruction to the

instruction ROM as well as in single

instruction format to the processor.

The instruction machine code is

keyed in through the keyboard. The

result of the processor ALU available

in special function register is

displayed on a LCD module. The

signals of the debug module are

shown in Table-2.

DEBUG MODULE PINDESCRIPTION

S.NO

NAME I/O

WIDTH

DESCRIPTION

1 RST EXT I 1 ACTIVE LOW RESET

2 MASTERCLOCK

I 1 CLOCK

3 HALT PROC O 1 PRCOESSOR EXCEPTION HALTACTIVE HIGH

4 WAIT O 1 PROCESSOR WAIT, ACTIVE LOW5 BUSY I 1 PROCESSOR BUSY, ACTIVE HIGH

6 SFR_ENABLE

O 1 SPECIAL FUNCTION REGISTERENABLE

7 SFR_READ O 1 SPECIAL FUNCTION REGISTERREAD

8 SFR_DATA I 16 SPECIAL FUNCTION REGISTERDATA

9 IR MEMORYDATA

O 37 INSTRUCTION MEMORY DATA

10 IR MEMORYWRITE

O 1 INSTRUCTION MEMORY WRITE

11 IR MEMORYADDRESS

O 10 INSTRUCTION MEMORY ADDRESS

12 LCD_EN O 1 LCD ENABLE

13 LCD_RS O 1 LCD COMMAND-DATA CONTROL

14 LCD_DATA O 8 LCD DATA

15 KBD_CLK I 1 KEYBOARD CLOCK

16 KBD_DATA I 1 KEYBOARD DATA17 ADDRESS

COUNTERO 1 KEYBOARD DATA


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Program Memory Module: The

program memory stores the

instruction to be used by the

processor. The debug module loads

the instruction. The instruction is

keyed in by the user using a

keyboard unit.

PROGRAM MEMORY MODULE

S.NO

NAME I/O

WIDTH

DESCRIPTION

1. MEMORYWRITE

I 1 MEMORY WRITE SIGNALOF DEBUG MOD

2. IR MEMORYDATA

I 37 INSTRUCTION MEMORYDATA FROM DEBUG

3. OPCODE Read I 1 OPCODE READ FROMPROCESSOR

4. IR MEMORYADDRESS

I 1O PROCESSOR ADDRESS


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Major components

identification

Keyboard Unit

The input signals for keyboard are

keyboard clock, keyboard data,

keyboard enable signal from the

control unit and a system clock (10

times keyboard clock). When

keyboard enable signal is low the

keyboard data 1 or 0 keyed in by

the user is stored and forwarded tothe following unit. The keyed data is

latched in the following unit by a

trigger signal.

Temporary Register

This register is used to store the data

coming from the keyboard unit and

when enable signal from control unit

is high, then data in it is latched to the

respective fields. First, opcode is

latched to opcode decoder when

buffer signal is high.

Opcode Decoder

The data latched from register is

decoded and one of the eight

categories is selected based on

which the next field signals are

selected. When reset from control

unit becomes high, the decoder is

resetted.

Control Unit

This is the important block in the

module. This controls the keyboard

unit using buffer signal whether the

data is to be transferred or not. It also

controls the temporary register using

the enable signal to latch the data to

respective fields. Based on the

category signal generated by the

decoder unit, the state signals i.e.,

the next fields to be selected are

generated.

Field Selector

When the field signals are generated

from the control unit, then field

selector generates the enable signal

in order to select respective field

where data is to be written. This field

selector block interfaces the

keyboard unit with the LCD unit.

When the opcode is decoded then

depending on categories selected,


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the next field to be displayed is

decided by this block.

LCD Unit

It displays every data entered throughthe keyboard and the data from fieldselector. The data from temporaryregister is connected to LCD unit.

Description:

The Control unit is the brain of the

system. It senses the Complete

signal generated by the Opcode

temp register and asserts the Latch

decoder signal to latch data into the

Opcode Decoder. It then senses the

Category Signal and asserts the A,

B, C, D signals as required for the

opcode (entered) and the WR signal

to latch data into the internal registers

of the Opcode temp register. The

ABCD signals decide which internal

register the data will be written to. It

then asserts the Clear signal to

clear the Temp latch inside the

Opcode temp register. This process

goes on till all the relevant data (for

e.g. SRC1 addr., SRC2 addr. , Target

addr. or IMMD data) has been taken

and stored in the internal registers of

the Opcode temp register. Then the

Control Unit asserts the Memory

Write signal to write the contents of

the internal registers of the Opcode

temp register into the program

memory. It also increments the

contents of the Address counter,

generates the INTrst to reset all the

blocks for the next opcode entry and

then re-initializes itself. This is for

data entry into the system.

When data or result has to be

retrieved from the SFRs (special

function registers) then the Control

unit will first sense the Busy signal

coming from the processor. This

signal tells the Control unit the state

of the processor. When the Control

unit senses that the processor has

executed the opcodes and stored the

results into the SFR, it enables the

SFR read signal along with the

SFR en signal to read the data from

the SFRs. These signals tell the LCD

unit that it has to take data from the

SFRs.

Input parameters

RST Ext

The power ON system reset signals

the beginning of the control

operation.

System ClockThe system clock is 10 MHz. This is

the operating clock of the control unit.

Complete


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Indicates that the 6 bit OPCODE

keyed in by the user is ready in the

Opcode temp register.

Category

The category signal indicates the

types of Instructions. From the set of

21 instructions the category are as

follows.

Cat1 =NOP, Ret, End, Cat2 =

ALU R_type, Cat3 = Conditional

branch , Cat4 = R_Type Store,

Cat5 = Memory Load, Cat6

=Memory store, Cat7 = R_type store,

Cat8 = PWM, Cat9 =

Busy

Indicates that the processor is busy

executing the instruction. The

dissertation of the busy signal by the

processor indicates that the SFR data

as a result of the last instruction is

ready for display.

Output parameters

Latch Decoder

Indicates that the Opcode Decoder

will latch the OPCODE data collected

by the Opcode temp register.

A, B, C, D

The ABCD signals decide which

internal register the data keyed in will

be written to. The A, B, C, D signals

means Enter Src1, Enter Src2,

Enter Tar and Enter Imm

respectively.

WR

Signal to latch data into the internal

registers (Opcode, Src1, Src2, Tar

and Imm field of the Instruction

register) in Opcode temp register.

Clear

The clear signal clears the registers

(Src1, Src2, Tar and Imm field of the

Instruction register) in Opcode temp

register at the end of instruction

execution before a fresh Instruction is

entered.

Memory Write

The Memory Write signal is used to

write the contents of the internal

registers of the Opcode temp

register into the program memory.

INCRaddr

The signal is used to increment the

contents of the Address Counter

which is used as the Memory addressof program memory.

RSTint


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INTrst is used to reset all the blocks

of the debug module for the next

opcode entry and to re-initialize itself.

SFR read, SFR en

SFR read signal along with the SFR

en signal are used to read the data

from the SFRs. These signals are

also used in the LCD unit to take

data from the SFRs and display.

Proc Halt

The control unit asserts the Proc Halt

to halt the processor.

Wait

The control unit asserts the Wait

signal in following the execution of

the instruction and keying in of new

instruction by the user.


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Description

In the design only data and command

in binary form is given as input.

Hence only two keys of keyboard unit

that are 0 & 1. Whenever any key is

pressed on keyboard, keyboard unit

get data in the form of scan code

(PS2 keyboard). That means for 0

key keyboard sends 01101001(69h)

serially on Kbd_data input because

01101001 is scan code of 0.

Similarly 01110000 is scan code of

1.

Keyboard unit fetch the scan code on

system clock frequency. Keyboard

unit checks the fetch scan code is of

0 or 1 according to that it assert data

signal high (for 1) or low (for 0)

respectively. Keyboard unit also

generate one trigger pulse (Trig) to

indicate that valid data is on the data

line. Trigger pulse is as long as one

keyboard clock cycle. If RST_int or


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RST_ext is high then unit goes into

reset state.

There are two state machines for

operation of keyboard unit. First state

machine operate on system clock

and use to check start bit of scan

code. Second machine operate on

keyboard clock, which actually fetch

the data and assert data signal. Both

FSM generate interdependent signals

like reset, start, break etc.

Input parameters

RST Ext


the beginning of the total system

operation.

RST Int

RST Int is used to reset all the blocks



KBD clock


the beginning of the total system

operation.

KBD data

INTrst is used to reset all the blocks



System clock

The system clock is 10 MHz. This is

the operating clock of the keyboard

controller unit.

Output parameters

Trigger

Keyboard unit generate trigger pulse

to indicate that valid data is on the

data line. Trigger pulse is as long as

one keyboard clock cycle.

Data

When only two keys of keyboard unit,

that are 0 & 1 are pressed, keyboard

sends the scan code

01101001(69h) and scan code

01110000(70h) respectively serially

on Kbd_data. The keyboard unit

decodes these scan code and sends

only high (1) and low (0) for key 1

and 0 respectively.


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A References:

[1] Bezarra, E. A. Gough, M.P. A

Guide to Migrating from

Microprocessor to FPGA Coping

the Support Tool Limitations,

ELSEVIER Microprocessor and

Microsystems 23,1999, pp.

561-572.

[2] Herman, H. S., Srihari, C.,

Matthew, M., Pipeline

Reconfigurable FPGAs,Journal of VLSI Signal

Processing Systems,2000,

pp. 24, 129-146.

[3] Borgatti, M., Lertora, F., Foret,

B., Cali L., A Reconfigurable

System Featuring

Dynamically Extensible

Embedded Microprocessor,FPGA and Customizable I/O,

IEEE Custom Integrated

Circuits Conference, 2002,

pp. 13-16.


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[4] Janiszewski, I., Baraniecki,

R., Siekierska, K. A reusable

microcontroller cores design,

IEEE, VHDL International

Users Forum Fall Workshop

(VIUF 99), 1999, pp. 14-21.

[5] Jurado-Carmona, F.J.,

Tombs, J., Aguirre, M.A.,

Torralba, A., Implementation

of a fully pipelined ARM

compatible microprocessor

core XVII Design on Circuits

and Integrated Systems

Conference, 2002, pp. 559-

563.

[6] Davidson, J. FPGA

Implementation of a

Reconfigurable

Microprocessor IEEE

Custom Integrated Circuits

Conference, 1993, pp. 3.2.1-

3.2.4

[7] Sueyoshi, T., Kuga, M., and

Shibamura, H., KITE

Microprocessor and CAE for

Computer Science, Systems

and Computers in Japan, Vol.

33, No. 8, 2002, pp.64-74.

[8] Pastor, J. S., Gonzalez, I.,Lopez, J., Arribas, F.G,

Martinez, J. A Remote

Laboratory for Debugging

FPGA-Based Microprocessor

Prototypes, Proceedings of

the IEEE International

Conference on Advanced

Learning Technologies

(ICALT04),2004.

[9] Alaer, E., Tangel, A., Yakut,

M. "MIB-16 FPGA based

Design and Implementation of

a 16 Bit Microprocessor for

Educational Use", 6th

WSEAS International Conf.

on Circuits, Systems,

Electronics, Control&Signal

processing, Cairo-Egypt,

2007, pp. 284-288.

[10] Cakroglu, M. Gerek

Zaman Sayma Birimi Iceren

SAU80C51 Mikro

denetleyicisinin FPGA

Mimarileri Kullanilarak

Gelitirilmesi, MsC Thesis,

Sakarya University, Turkey,

pp. 29-32, (2003).

WSEAS TRANSACTIONS on

ADVANCES in ENGINEERING

EDUCATION

Esma Alaer, Ali Tangel and Mehmet

Yakut

ISSN: 1790-pplication binary

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“design of a debug module for mips processor”

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