Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs

Abstract:

Increased functional density with shrinking technology could result in escalating power supply noise (PSN)-induced failures in the field. Furthermore, the low correlation between system-level functional test and production test is making it difficult to better screen parts that would fail in the field due to PSN. To address these issues, in this paper, we present a fully digital on-chip distributed sensor network to continuously monitor the PSN profile across the chip and generate a trace for diagnosis of any noise-induced failure at silicon validation, structural test, system test, and functional operation phases of system on chips (SoCs). The sensors capture PSN at a fine granularity and store the SoC’s critical status bits. The sensor offers easy access and control with the aid of scan chains. The sensor network has been designed in the 28-nm standard cell library, and its performance is demonstrated in the physical design of OpenSPARCT1 multicore processor SoC. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.

Enhancement of the project:

Existing System:

For the case of a noise waveform that is periodic and synchronized to a single frequency, the method of equivalent time sampling or sub sampling may be applicable. This flow operates by using a time-base generator to sweep a sample point from the beginning to the end of the noise cycle, thus tracing out the entire noise waveform. However, because of the random nature of chip workload and environment condition, during the normal operation of a chip, the noise variation profile may not be fully periodic. As a result the dynamics of any non-repetitive or asynchronous portion of noise is lost, and only the distribution of noise at each equivalent time point is known in these types of measurements. To overcome these issues, Alon et al. modeled noise as a cyclo-stationary random process and extracted the autocorrelation for estimation of the power spectral density (PSD) from the Fourier transform of the extracted autocorrelation sequence. This flow works on the theory that a time-average PSD can be measured simply by taking the autocorrelation samples uniformly within the noise period. The measurement hardware consists of two on-chip low throughput sampler with a voltage-controlled oscillator (VCO)-based ADC, a comparator-based sampler, and so on. Sufficient number samples are averaged to get the autocorrelation.

In, a digital PSN analyzer is described that incorporates a digital random phase-noise accumulator to measure a power spectrum without requiring a separate, uncorrelated time-base clock. It requires a low-resolution VCO-based ADC. To obtain 1-mV accuracy, 32 million cycles are averaged. Although it achieves a high bandwidth and detection resolution, the substantial implementation complexity and area overhead as would deter it from multiple deployments across the chip layout to observe a spatial noise profile. To test and debug the effects of voltage transients, Petersen et al. enable the voltage transient detection, as well as a capability to induce voltage transients in controlled manner.

The shortcoming of the existing on-chip monitors are as follows.

1) Often the monitors incur high area overhead due to the presence of analog blocks or customized operations.

2) The sensors monitor the noise events dynamically at each clock cycle; as a result the worst case scenario is often masked.

3) It would be an over-design to extract the PSN distribution or the exact waveform, since circuit performance is mainly impacted by the average noise over a clock cycle.

4) The sensors cannot map the noise events to the SoC’s architectural states or the executing workload.

Disadvantages:

Noise level is high

Proposed System:

The typical PSN observed at the chip level can be characterized by three different resonant droop events, as shown in Fig. 1and explained below. These voltage droops are determined by the supply impedance of the power delivery network at different frequencies.

Fig. 1. PSN profile.

SENSOR NETWORK ARCHITECTURE:

The sensor network would be designed in such a way that each local sensor node would monitor its neighboring power supply and store the detected worst case PSN event. At each worst case observation, the respective sensor IP would generate a pulse trigger to initiate the recording of a snapshot of the chip’s key status bits or count the clock cycle number where the event occurred. Fig. 2 shows the block diagram of our target sensor network.

Fig. 2. Sensor network architecture. It includes K sensor blocks distributed in a chip layout.

Local Sensor Block:

The circuit diagram of the local sensor block is shown in Fig. 3. The input and output ports of the sensor are annotated on the left and right boundaries, respectively.

Fig. 3. Circuit diagram of the PSN sensor IP.

Global Control and Debug Unit

The task of the global control unit is to accept the trigger pulses from all the local sensor modules corresponding to the respective worst droops and generate the global debug pulse T _Debug. We can add some specially designed debugging blocks to this module, as shown in Fig. 4.

Fig. 4. Global control and debug unit.

Sensor Access and Control

For each sensor, the control vectors and the PSN results are stored in registers and connected in a scan chain. The scan chains of the individual sensors are connected in a dedicated global scan chain for the sensor network. From a SoC point of view, this PSN sensor network’s scan chain can be accessed with the aid of JTAG features. In Fig. 5, the use of the existing JTAG in accessing our PSN sensor network is explained.

Fig. 5. Sensor access with JTAG

DEBUG UNIT

The design-for-debug (DfD) feature has become an indispensable part of modern SoCs as the first-silicon prototype is rarely bug-free. The embedded DfD modules identify any electrical or functional bug that may exist in the prototype product and allows the designers to resolve those bugs in the next commercial release.

In the first feature, as shown in Fig. 6, a set of important signals that reflects the internal micro architectural and the instruction status is continuously traced. At each global trigger pulse, the traced signals are stored as footprints in a register file called CSR. In Fig. 8, at each clock cycle, the signals are traced successively by Storage Register 1 and Storage Register 2. The second register—Storage Register 2—is used to account for the delay, δ, between the actual PSN event and the generation of a pulse at T _Debug.

Fig. 6. CSR unit.

Advantages:

Reduce the noise level

Software implementation:

Modelsim Xilinx ISE