Design of a Power Amplifier using MESFET at 2.7GHz ~ 3.1 GHz

Li Junsheng1, a, #, Tang Jian1, b, #, Jiang Yunhui 1, c and Yu Fei 2, d, * 1School of New Energy and Electronic Engineering, Yancheng Teachers University, Yancheng

224007, China 2School of Electronics and Communication Engineering, Shenzhen Polytechnic, Shenzhen,

518055, China ajunsheng_li@163.com, bjtang1982@163.com, c3096247628@qq.com,

dyufei198275@szpt.edu.cn

# These authors contributed equally to this work

* Corresponding author

Keywords: power amplifier; S parameter method; Load line method; MESFET Abstract. In this paper, a linear power amplifier with MESFET tube is simulated and optimized by the application of ADS software and S parameter method. The MESFET tube is a kind of low distortion power FET provided by the company of Excelics and its tag is EFC480C. After optimizing，the size of the power amplifier proposed is 15mm×20 mm which is rather small among the similar designs. The gain of the amplifier proposed is over 11 dB at the 2.7GHz ~ 3.1GHz, and the output power (sat) of the amplifier is over 30 dBm. The power fluctuation of the amplifier proposed is less than 1 dB, and the input/output in VSWR is less than 2. The performance of the proposed amplifier is outstanding proved by simulation and testing.

Introduction Using MESFET in the production of microwave hybrid integrated circuit not only makes the volume of the devices smaller than shell packaging devices, but also eliminates the harmful effects of the packaging parameters.

The Class A amplifier has the significant linearity. Static IV curve of the device is usually used to determine the large signal load line impedance (RL), and the class A amplifier is designed with small signal S parameter method [1]. Specific steps are as follows: choose the appropriate MESFET, determine the operating quiescent point and the best output load impedance, design output and input matching circuit network according to the output circuit in the input plane mapping.

Circuit Design and Experiment

Indicators of the Power Amplifier. The indicators of the power amplifier includes: operating frequency ranges from 2.7GHz to 3.1 GHz; gain more than or equal to 11 dB; output power P (sat) more than or equal 30 dBm; power fluctuations less than or equal 1 dB; input and output VSWR less than or equal 2 and the size is 15mm × 20 mm. Selection of the Tube Core. The first step is to select the right tube core, GaAs chips typically need to to be soldered on the carrier with gold-tin alloy[2,3]. For this, the back of the chips need to be metalized and contacts should be compatible with the thermo-compression bonding process. In reference of the audit objectives, a GaAs FET tube core has been chosen. The tube core is low distortion Power FET EFC480C produced by Excelics, whose gate width is 4.8mm.When the tube core is working in the typical conditions, Vds equals 8V and Ids equals 500 mA. The gain is 18 dB in the frequency of 2GHz. While the power is 1 dB, the compression point presents 32dBm. The source of the core tube without ground connection will need to connect source to ground by gold bonding. Determine the Static Operating Point and the Load Impedance. Determine the static working point with the work type of amplifier [4]: According to the requirements of linear power amplifier, the

5th International Conference on Measurement, Instrumentation and Automation (ICMIA 2016)

© 2016. The authors - Published by Atlantis Press 14

tube bias should be in the CPI. Static drain current Id is about half the saturated drain current Idss, drain bias voltage Vd is 8V and the gate bias Vg is about -1V. Quiescent point can be adjusted according to actual situation.

Determine the load impedance through load line method: the optimal output impedance real part is determined in accordance with the calculated requirements of the tube output load impedance line[5]. The formula for the line load is RL = (Vb-Vs) 2 / (2Pout), wherein Vb is the drain bias voltage and Vs is the knee voltage in V - I curve. For EFC480C Vs equals 2V, the value of Pout can be set 1.5W, finding RL equals 12Ω.

It is noteworthy that to identify bias voltage and maximum output power of GaAs MESFET, the critical parameters is the breakdown voltage. If the load resistance and RF output voltage is too large, it is easy to breakdown. Therefore, it should be determined whether the output voltage will be into the breakdown region. It should meet the standard 2V_b-Vs <BVgd-Vp, wherein BVgd is the gate-drain breakdown voltage, Vp is (gate-source) pinch-off voltage. BVgd of EFC480C is about 20V while Vp is about 2.5V. So the load choice is impedance.

Only when the load impedance between the two ends of the controlled source is a real number, the maximum output power can be got. So the imaginary part of the output load impedance in the matching circuit should resonate with the MESFET drain-source capacitance Cds. During the matching network design, it needs to absorb the imaginary part of the output impedance to make a comprehensive matching network. Cds can be fitted according to the small-signal equivalent circuit parameters and S parameters of the tube. In the light of S parameters provided by Excelics, component values of the MESFET small signal equivalent circuit are fitted through ADS simulation software and small signal circuit is represented as Fig.1:

Measured S-parameter data

Li near FET m odel

Since no optim ization is run here, t he opt im ization ranges f oreach param eter are ignored.

GoalOptim Goal4

R angeMax [1] =R angeMin[1]=R angeVar[1]=W eight=30Max=0Min=0Sim Ins tanceN am e="SP1"Expr="s12dp "

GOAL

GoalOptim Goal2

R angeMax [1] =R angeMin[1]=R angeVar[1]=W eight=20Max=0Min=0Sim Ins tanceN am e="SP1"Expr="s22dp"

GOAL

MeasEqnMeas1

Sm odel=S(3:: 4,3::4)Sm eas=S(1: :2,1::2)

EqnMeas

MeasEqns11_quo

s22dp = m ag( (Sm eas (2, 2) - Sm odel(2,2)) / Sm eas (2,2) )s11dp = m ag( (Sm eas (1, 1) - Sm odel(1,1)) / Sm eas (1,1) )s21dp = m ag( (Sm eas (2, 1) - Sm odel(2,1)) / Sm eas (2,1) )s12dp = m ag( (Sm eas (1, 2) - Sm odel(1,2)) / Sm eas (1,2) )

EqnMeas

S_ParamSP1

Step=0.5 GH zStop=10.5 GH zStart=0. 5 GHz

S-PARAMETERS

GoalOptim Goal3

R angeMax [1]=R angeMin[1]=R angeVar[1]=W eight=5Max=0Min=0Sim Ins tanceN am e="SP1"Expr="s21dp"

GOAL

GoalOptim Goal1

R angeMax [ 1]=R angeMin[1] =R angeVar[1] =W eight=10Max=0Min=0Sim Ins t anceNam e="SP1"Expr="s11dp"

GOAL OptimOptim 1

UseAllGoals=y esUseAllOptVars=y es

Sav eAllI terat ions=noSav eN om inal=y esU pdateD ataset =y esSav eOptim Vars=noSav eGoals=noSav eSolns=noSeed= SetBes tValues=noF inalAnaly s is="N one"StatusLev el=4D es iredError=0.0P=2Max Iters=2000ErrorF orm =L2Optim Ty pe=Gradient

OPTIM

FETFET1

R ds=23.5566 Ohm opt { 0 Ohm t o 1000 Ohm }C ds=7.19214e-013 F opt{ 0 pF t o 2 pF }C dc=0 pFC dg=3.54214e-013 F opt{ 0 pF t o 1 pF }R i=5.71957 Ohm opt{ 0 Ohm to 10 Ohm }Ggs=0 uSC gs=4.7214e-012 F opt{ 0 pF t o 15 pF }F=0 GH zT=4.68684 psec opt{ 2 psec to 5 psec }G=640.245 m S opt{ 0 m S to 2000 m S }

S2PSN P1F ile="D :\N J \GaAsF ET\GaAs? ? \FC 480C .S2P"

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Re f

TermTerm 2

Z=50 OhmNum =2

TermTerm 1

Z =50 OhmN um =1

TermTerm 4

Z=50 OhmN um =4

TermTerm 3

Z=50 OhmNum =3

Fig.1 The small signal equivalent circuit

The fitting result indicates that Cds equals 0.72PF. The load admittance resonates with Cds, therefore the load admittance valuation is given as: YL = GL-jwCds wherein GL = 1 / RL = 0.083s. It is available that YL = 0.083-0.014 * j and load impedance ZL = 1 / YL = 11.85 + 2.02 * j.

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Estimate output power: Since the load impedance in parallel of the current source is a real number, the AC component and load current of the drain voltage are in phase. The output power can be given as PL = (1/4) (Vb-Vs) Imax = 1.5W.

Circuit Design and Simulation. A. Bias circuit Quarter-wavelength band line offers subtle bias while the resonant capacitor is adopted to achieve

RF ground in the bias line terminal. The RF signal is isolated by inductance and RF signal and power ripple are filtered by different capacitance.

B. Design output matching circuit To a large extent, output matching circuit determines the maximum output power and the power

efficiency. It requires that output load impedance matching circuit provided the calculated load impedance of the tube core. We use simple and practical L-type low-pass matching circuit to achieve impedance transformation. In the literature [1], a number of L / S-band amplifiers are mentioned which shows shorting second harmonic (short circuit) enables efficiency increased by 6 percentage points. In the design process, the output matching network needs to make broadband frequency sweep. Integrated using RF terminal quarter-wave length bias line to suppress second harmonic in some degree will maintain a larger second harmonic attenuation in the output circuit and obtain a short-circuit point. What should be noted is that simulation should be included in the drain bonding of gold matching circuit. The appropriate circuit parameters are obtained after optimizing the circuit by ADS. Topology is shown below:

PortP1Num=1

WIREWire3

WIREWire4

CC4

MLOCTL10

MTEETee7

MLINTL11

CC13

CC2

V_DCSRC2Vdc=10 V

LL2

CC11

MLINTL6

Fig.2 Output matching circuit

C. Design input matching circuit Input matching circuit design requires providing matching input impedance and ensuring stability,

which is a key factor to ensure the design bandwidth. Considering all this factors, a π-type matching circuit is chosen. Specific steps include mapping output circuit to the input plane, designing the input network in the light of conjugate matching method and introducing a shunt resistor to improve the stability. Last but not least, ADS is used to optimize gain, VSWR, bandwidth and stability so that the optimal input matching network can be obtained finally.

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PortP1Num=1

W IREW ire2

W IREW ire1C

C3

MTEETee12

MLOCTL20

MLINTL19

LL3

CC10

MLINTL12

MTEETee13

MLINTL17

RR1

CC19

CC12

CC

V_DCSRC1

Fig.3 Input matching circuit

D. Simulations with ADS ADS is used to simulate stability of the circuit which has been shown in Fig 4, k always greater than

1.That means the circuit absolutely stable. ADS S-parameter simulation is shown in Figure 5 which indicates within 2.7GHz to 3.1GHz, the gain is over 14dB and input and output VSWR are both less than 2.

2.0 2.5 3.0 3.51.5 4.0

2

3

4

5

1

6

freq, GHz

Sta

bFac

t1

1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.81.6 4.0

-35

-30

-25

-20

-15

-10

-5

0

5

10

15

-40

20

fr eq, G Hz

dB(S

)

Fig.4 Circuit stability coefficient map Fig.5 The small signal frequency response

Production, Test and Conclusions Rogers4003 microstrip plate is selected in the production whose thickness is 0.5mm and permittivity is 3.38. Tube core solders on a molybdenum film carrier whose thermal expansion coefficient is similar to GaAs with gold-tin eutectic. It also should be noted that the carrier chip forms a good combination of alloy type, and otherwise it will affect the performance. Using thermo-compression bonding method, the chip electrode is connected with microstrip by gold bond. What have to be aware of are the parameters consistent with simulation.

Fig.6 The physical map of the power amplifier

After formed, the circuit is debugged with the copper foil as showed in Figure 6. The results of the final tests show the small-signal frequency response ranges from 2.7 to 3.1GHz, gain is greater than

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11dB and input and output VSWR both less than 1.5. The output power is more than 1W, power added efficiency is 23%.The power amplifier performance indicators meets the requirements

Acknowledgement This work is supported by the Natural Science Foundation of the Higher Education Institutions of

Jiangsu Province, China (Grant No. 16KJB140017 and 13KJB510037).

References

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[3]Lin Chuan, Yang Bin, Yuan Xiaolin, Gao Qun. A S-band Miniaturized Integrated PA Based on Lange Coupler Technology [J]. Research and Progress of SSE, 2012, 06:565-568.

[4] Li Jihao. Design of T/R Module Power Amplifier Based on SiC Wide Bandgap Semiconductor [J]. Journal of Microwaves, 2010, S1:564-567.

[5] Yu Xuming, Hong Wei, Wang Weibo, Zhang Bin. Ku Band Power Amplifier MMIC Based on GaN HEMT Technology [J]. ACTA Electronic Sinica, 2015, 09:1859-1863.

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