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Design of an Integrated Switched-Capacitor Filter

Jens Pejtersen

March 3, 2008

Abstract

The design of a fully differential integrated Switched Capacitor (SC) third order But-terworth low pass filter is described. The filter is designed to have a corner frequencyof 1 MHz and unity passband gain. The filter is realized as a cascade of a first orderfilter and a second order filter. The filter is implemented using a 0.35 µm CMOSprocess in Cadence Virtuoso. The discrete time z-domain transfer functions is firstdesigned to satisfy the performance requirements. These are used to calculate the ca-pacitor ratios required to realize the desired filtering functionality. All the necessarycomponents required to realize a SC filter are designed and combined in the imple-mentation of the filter. Finally the performance of the designed filter is simulatedusing the Spectre RF simulator.

i

Resumé

Designet af et fuldt differentiabelt integreret Switched Capacitor (SC) trejde ordenButterworth low pass filter bliver beskrevet. Filteret er designet til at have knæk-frevens ved 1 MHz og enhedsforstærkning. Filteret realiseres som en kaskade af etførste ordens filter og et andet ordens filter. Filteret implementeres i en0.35 µm

CMOS process i Cadence Virtuoso. Filteret bliver først designet som z-domæneoverføringsfunktioner, der opfylder kravspecifikationen. Disse overføringsfunktionerbruges til at beregne de kapacitor-forhold, der kræves for at kunne realisere denønskede filterfunktion. Alle de nødvendige komponenter, der skal bruges til at re-alisere et SC filter, bliver designet individuelt. Disse kombineres herefter i imple-mentationen filteret. Det endelige filters funktionalitet simuleres ved brug af SpectreRF.

iii

Preface

This thesis has been submitted in order to meet the requirements to obtain the degreeof Bachelor of Science in Engineering (BScE) at the Technical University of Den-mark, DTU. This project has been carried out in the Centre forPhysical Electronicsat the Deparment of Electrical Engineering (DTU ElectricalEngineering). The workin this thesis has been carried out under supervision of ErikBruun in the period fromOctober 2007 to February 2008.

Kongens Lyngby, February 29th 2008

Jens Pejtersen, s042180

v

CONTENTS

Contents

1 Introduction 1

1.1 Performance Specification . . . . . . . . . . . . . . . . . . . . . . . 1

2 Designing the Switched Capacitor Filter 3

2.1 Switched Capacitor Filters . . . . . . . . . . . . . . . . . . . . . . . 3

2.1.1 First Order Switched Capacitor Filter . . . . . . . . . . . . .4

2.1.2 Second Order Switched Capacitor Low-Q BiQuad . . . . . . 5

2.2 Analytical Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2.1 Determing the Filter Transfer Functions . . . . . . . . . . .. 7

2.3 Determining the Capacitor Ratios . . . . . . . . . . . . . . . . . . .8

2.3.1 First Order Filter Section . . . . . . . . . . . . . . . . . . . . 9

2.3.2 Second Order Filter Section . . . . . . . . . . . . . . . . . . 9

2.3.3 Matching the Capacitors . . . . . . . . . . . . . . . . . . . . 9

3 Designing the Filter Building Blocks 13

3.1 The CMOS Process . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1.1 Process Parameters . . . . . . . . . . . . . . . . . . . . . . . 13

3.1.2 Cadence Models . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 The Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . 14

3.2.1 Design of the Single Output Operational Amplifier . . . .. . 15

vii

CONTENTS

3.2.1.1 Simulation . . . . . . . . . . . . . . . . . . . . . . 18

3.2.2 The Fully Differential Operational Amplifier . . . . . . .. . 20

3.2.2.1 Common Mode Feedback Circuit (CMFB) . . . . . 21

3.2.2.2 Simulation . . . . . . . . . . . . . . . . . . . . . . 23

3.3 Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.3.1 The NMOS Switch . . . . . . . . . . . . . . . . . . . . . . . 27

3.3.2 The Transmission Gate . . . . . . . . . . . . . . . . . . . . . 27

3.4 Creating the Non-Overlapping Clock Signals . . . . . . . . . .. . . 29

3.5 Sample and Hold Circuit . . . . . . . . . . . . . . . . . . . . . . . . 31

4 Implementation of the Filter 33

4.1 First Order Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.2 Second Order Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.3 Third Order Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5 Conclusion 41

A Operational Amplifier Cadence Schematics 43

B Filter Cadence Schematics 45

List of Figures 48

List of Tables 50

Bibliography 51

viii

Chapter 1

Introduction

Switched Capacitor (SC) circuits have been widely used in the design of integratedcircuits. They have become popular in integrated filters because they can be usedto design filters with very high precision compared to normalRC-filters, that oftenrequires a tuning circuit to ensure proper operation.

The frequency response of SC filters is ideally a function of capacitor ratios, whereas the frequency response of RC-filters is highly dependableon the operating tem-perature and the fabrication process. Capacitor ratios canbe made very precise andalmost independable of fabrication errors.

This report describes the design of a fully differential integrated SC third order lowpass Butterworth filter. The third order filter is realized asa cascade of a first order fil-ter and a second order biquad filter. The filter is designed to have the corner requencyfc at 1 MHz and unity passband gain.

The filter is implemented in a 0.35µm CMOS process with supply voltages of±1.25 V. The supply voltages and the sampling clock signal are assumed to besupplied by external circuitry. The filter is implemented and simulated at schematiclevel using Cadence Virtuoso and the Spectre RF simulator.

1.1 Performance Specification

The SC filter is designed using the following requirements:

• Third order Butterworth low pass filter.

1

CHAPTER 1. INTRODUCTION

• Unity passband gain.

• Corner frequency at1 MHz.

• ±1.25 V.

• Fully differential input and output.

2

Chapter 2

Designing the Switched CapacitorFilter

This chapter describes the process of designing a third order low pass ButterworthSwitched-Capacitor (SC) filter. The filter is designed to meet the requirements statedin the performance specification. The third order filter is realized as a cascade of afirst order and a second order SC filter section.

The filter is first designed as a continuous time (CT) transferfunction, which is thentransformed to a discrete time (DT) transfer function usingthe bilinear z-transform.This is performed purely analytical. The DT transfer function is then used to calcu-late the capacitor ratios needed to realize the first order and second order SC filtersections.

2.1 Switched Capacitor Filters

SC circuits operates by charging and discharging capacitors with a predefined switch-ing scheme consisting of two or more non-overlapping clock signals. The nettocharge transferred during the switching period averaged over time can be seen asa current. This makes it possible to emulate resistors.

The charging and discharging of a capacitor ideally acts as asimple sample and holdcircuit. This sampling property makes it possible to describe the functionality of SCcircuits using DT z-domain transfer functions.

SC filters are designed to perform continuous time filtering using SC circuit concepts.

3

CHAPTER 2. DESIGNING THE SWITCHED CAPACITOR FILTER

The input signals are quantized and filtered using analog integrators similiar to RCfilters. The quantization of the input results in a quantizedoutput signal drom whichathe continuous time signal can be recreated by an interpolation filter.

Because a SC filter acts as an analog sampling filter it is necessary that the inputsignal satisfies Nyquist’s sampling criterion:

fs ≥ 2fc (2.1)

, wherefs is the switching/sampling frequency of the SC filter andfc is the maximumfrequency to be processed by the filter. This means that the input signal needs to bebandlimited tofc to avoid aliasing.

2.1.1 First Order Switched Capacitor Filter

Figure 2.1: First order switched capacitor filter section

The first order filter section is realized as described in [3, p. 409-413]. A schematicof the circuit is shown in 2.1. The z-domain transfer function is given by [3, Eq.(10.33)]:

H1st(z) = −

(

C1+C2

CA

)

z − C1

CA(

1 + C3

CA

)

z − 1(2.2)

CA is the integrating capacitor in the first order filter. All theother capacitors in thecircuit are referenced toCA by the capacitor ratios:K1 = C1/CA, K2 = C2/CA

4

2.1. SWITCHED CAPACITOR FILTERS

Figure 2.2: Second order switched capacitor low-Q biquad filter section

and K3 = C3/CA. Inserting the capacitor ratios into equation (2.2) expressesH1st(z) as a function of the capacitor ratios.

H1st(z) = −(K1 + K2) z − K1

(1 + K3) z − 1(2.3)

2.1.2 Second Order Switched Capacitor Low-Q BiQuad

The second order filter section is implemented using the low-Q SC biquad describedin [3, p. 415-420]. The schematic of the second order sectionis shown i figure 2.2.

The capacitor ratios are calculated by comparing the coefficients of the second orderfilter transfer function with (2.4).

H2nd(z) −a2z

2 + a1z + a0

b2z2 + b1z + 1(2.4)

5


The coefficients are then used to calculated the capacitor ratios using (2.5)-(2.9)

K4 = K5 =√

b2 + b1 + 1 (2.5)

K1 = (a0 + a1 + a2)/K5 (2.6)

K2 = a2 − a0 (2.7)

K3 = a0 (2.8)

K6 = b2 − 1 (2.9)

2.2 Analytical Filter Design

The normalized CT transfer function of a third order Butterworth low pass filter isgiven by:

H0(s) =1

(s + 1) (s2 + s + 1)(2.10)

H0(s) can be realized as a cascade of a first order transfer functionH0,1(s) and asecond order transfer functionH0,2(s).

H0(s) = H0,1(s) H0,2(s)

, where

H0,1(s) =1

s + 1(2.11)

H0,2(s) =1

s2 + s + 1(2.12)

The normalized transfer functionH0(s) has a unity passband gain and a corner fre-quency at 1 rad/s. The corner frequency of the normalized transfer functions is scaledto a specific corner frequencyωc by exchangings with s/ωc. Frequency scaling ofH0,1(s) andH0,2(s) yields:

H1(s) =1

sωc

+ 1=

ωc

s + ωc

(2.13)

H2(s) =1

(

sωc

)2

+ sωc

+ 1=

ω2c

s2 + ωc s + ω2c

(2.14)

The CT transfer function is transformed from the s-domain tothe z-domain using thebilinear z-transform. This is done by replacings in the CT transfer function with itsbilinear z-domain equivalent:

s =2

T

z − 1

z + 1(2.15)

6

2.2. ANALYTICAL FILTER DESIGN

Due to the frequency aliasing of the bilinear z-transform, the corner frequencyωc istransformed into the corresponding bilinear equivalentΩc. This is done using:

Ωc =2

Ttan

(

ωc T

2

)

(2.16)

, whereT is the number of samples per radian. Theα parameter is introduced tosimplify the development of the DT transferfunctions.

α = tan

(

ωc T

2

)

(2.17)

Inserting (2.17) into (2.16) yields

Ωc =2

Tα (2.18)

The bilinear transform is now used to transformH0,1(s) andH0,2(s) into z-domaintransfer functions. Theωc is replaced byΩc ands is replaced by (2.15) in the CTtransfer functions.

H1(z) =Ωc

s + Ωc

]

s= 2

T

z−1

z+1

=2T

α2T

z−1z+1

+ 2T

α=

α(z + 1)

(α + 1)z + α − 1(2.19)

H2(z) =Ωc

2

s2 + Ωcs + Ωc2

]

s= 2T

z−1

z+1

=

(

2T

α)2

(

2T

z−1z+1

)2

+(

2T

)2αz−1

z+1+

(

2T

α)2

=α2

(

z2 + 2z + 1)

(1 + α + α2) z2 + (−2 + 2α2) z + (1 − α + α2)(2.20)

2.2.1 Determing the Filter Transfer Functions

The filter needs to have a corner frequency atfc = 1 MHz and unity gain in thepassband in order to meet the requirements stated in the performance specification.Because a SC filter is a analog sampled filter it has to have a sampling frequencyfs

that satisfies Nyquist’s sampling criterionfs ≥ 2fc. Using the Nyquist frequency assampling frequency would require an ideal low pass filter at the output to recreate theanalog signal from the samples. As this is not realizable thesampling frequency ischosen to be 5 times higher than the Nyquist frequency.

fs = 5 · 2fc = 10 · 1 MHz = 10 MHz

7


The period of the sampling frequency is equal toT .

T =1

fs

=1

10 MHz= 100 ns (2.21)

Theα coefficient is calculated using (2.17) by insertingT from (2.21) and the cornerfrequency in radiansωc = 2πfc = 20π Mrad/s.

α = tan

(

ωc T

2

)

= tan

(

2π Mrad/s · 100 ns

2

)

= tan (0.1π)

' 0.3249 (2.22)

Inserting (2.22) into (2.19) and (2.20) yields the numerical expressions of the DTtransfer functionsH1(z) andH2(z) that satisfies the performance requirements.

H1(z) =0.3249z + 0.3249

1.325z − 0.6751(2.23)

H2(z) =0.1056z2 + 0.2111z + 0.1056

1.431z2 − 1.789z + 0.7807(2.24)

The transfer functions has been plotted in figure 2.3.

−50

−40

−30

−20

−10

0

10

Mag

nitu

de (

dB)

104

105

106

107

−315

−270

−225

−180

−135

−90

−45

0

45

90

Pha

se (

deg)

Frequency (Hz)

First

Second

Third

Figure 2.3: Bode plot of the seperate and cascaded transfer functions.

2.3 Determining the Capacitor Ratios

The capacitor ratios of the first order and the second order filter sections can now bedetermined from the numerical transfer functions.

8

2.3. DETERMINING THE CAPACITOR RATIOS

2.3.1 First Order Filter Section

The capacitor ratios are determined by comparing the numerical first order transferfunction (2.23) and (2.3). NormalizingH1(z) with respect to the zero order coeffi-cient of the denominator yields:

H1(z) =0.4813z + 0.4813

1.963z − 1(2.25)

Comparing (2.25) with (2.3) gives the capacitor ratios:

K1 = 0.4813 (2.26)

K2 = −0.4813 − 0.4813 = −0.9626 (2.27)

K3 = 1.963 − 1 = 0.9626 (2.28)

2.3.2 Second Order Filter Section

H2(z) is normalized with respect to the zero order coefficient of the denominator.

H2(z) =0.1352z2 + 0.2705z + 0.1352

1.832z2 − 2.291z + 1(2.29)

The capacitor ratios of the second order biquad can be calculated by inserting thecoefficients of (2.24) into (2.4). These are then inserted into (2.5)-(2.9) to yield thecapacitor ratios of the second order filter. The ratios are listed in table 2.1.

K1 0.7355

K2 0

K3 0.1352

K4 0.7355

K5 0.7355

K6 0.8324

Table 2.1: Capacitor ratios of the second order biquad section.

2.3.3 Matching the Capacitors

The frequency response of a SC filter is ideally determined bycapacitor ratios. It istherefore essential to every SC filter design that the capacitor ratios are immune toimperfections caused by the fabrication process, such as overetching and variation of

9


the oxide thickness [3, p. 108]. Errors due to overetching can be minimized usingmultiple unit capacitor in parallel to realize the capacitor ratios. This ensures that theerror due to overetching is the same for all capacitors and that all the ratios ideallystays the same.

The capacitor ratios of the first order filter and the second order filter are modifiedto make them an integer multiple of a unit capacitor. The relative size of the unitcapacitor is chosen to be 0.125. The modified capacitor ratios are listed in the tables2.2 and 2.3 for the first order filter and the second order filterrespectively.

K1 0.5

K2 -1

K3 1

Table 2.2: Modified capacitor ratios of the first order section.

The transfer functions are updated based on the on the modified capacitor ratios.

H1m(z) =0.5z + 0.5

2z − 1

H2m(z) =0.1250z2 + 0.3125z + 0.1250

1.875z2 − 2.313z + 1

Figure 2.4 shows a comparison between the original transferfunctions and the mod-ified transfer functions. It is seen that the corner frequency of the third order filterhas not changed significantly. The modified first order filter has almost the same fre-quency response as the unmodified first order filter. The modification of the secondorder filter has caused the frequency response to flatten to approximately -38.4 dB at5 MHz, but has not changed the 0 dB crossing at 1 MHz significantly.

K1 0.750

K2 0

K3 0.125

K4 0.750

K5 0.750

K6 0.875

Table 2.3: Modified capacitor ratios of the second order biquad section.

10

2.3. DETERMINING THE CAPACITOR RATIOS

Frequency (Hz)10

6−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

10

Mag

nitu

de (

dB)

First

First Modified

Second

Second Modified

Third

Third Modified

Figure 2.4: Frequency responses of the modified transfer functions compared to theoriginals.

11


12

Chapter 3

Designing the Filter BuildingBlocks

A SC circuit consists of several components or building blocks. The most obviousis capacitors switches and operational amplifiers. In addition to those it is necessaryto implement a clock generating circuit that ensures that the switches are driven bynon-overlapping clock signals. It is also necessary to implement a Sample and Hold(S/H) circuit to ensure that the output of the circuits are valid. This is done becausethe output of the first and second order filters used are only valid at the end of theφ1.All of the components mentioned here are designed during this chapter.

3.1 The CMOS Process

The process used in the design of the filter is a0.35 µm CMOS process from AustriaMicro Systems [2]. The process parameters listed below are used as a guideline inthe dimensioning of the transistors throughout this document.

3.1.1 Process Parameters

The threshold voltageVthn of the NMOS transistors andVthp of the PMOS transis-tors are approximated by:

Vthn = 0.6 V (3.1)

Vthp = −0.75 V (3.2)

13

CHAPTER 3. DESIGNING THE FILTER BUILDING BLOCKS

The gain factork′n of the NMOS transistors andk′p of the PMOS transistors are ap-proximated by:

k′n = 150 µA/V2 (3.3)

k′p = −48 µA/V2 (3.4)

3.1.2 Cadence Models

The transistors are simulated using the PRIMLIB/NMOS4 and PRIMLIB/PMOS4models. The resistors are simulated using the analoglib/res model. The capacitorsare simulated using the analoglib/cap model.

3.2 The Operational Amplifier

The operational amplifier is designed as a fully differential self biased folded cascode[1, Fig. 7.3-5]. The folded cascode is a single stage operational amplifier using theload capacitanceCL as compensation capacitor. The fully differential topology hasbeen chosen to minimize the effects clock-feedthrough and DC offsets and other non-ideal secondary effects.

The requirements of the operational amplifier to be used in the implementation of theSC filter is inspired by [3, p. 394-395]. The operational amplifier is designed to meetthe following requirements:

• The gain bandwidth productGB should be at least 5 times higher than theswitching frequency.

GB ≥ 5fs = 50 MHz (3.5)

• The DC-gain should be higher than 40dB.

A0 ≥ 40 dB (3.6)

• The phase marginPM should be about 70 degrees.

PM ∼ 70 degrees (3.7)

These requirements should be met when both outputs are loaded with a capacitanceCL of 10 pF, and the supply rails are limited to±1.25 V, as stated in the performance

14

3.2. THE OPERATIONAL AMPLIFIER

specification.

Vdd = 1.25 V

Vss = −1.25 V

The operational amplifier is first designed to satisfy the requirements with a singleoutput. The dimensions of the transistors used in the singleoutput operational am-plifier are then used as a template for the development of the fully differential oper-ational amplifier. This shoul result in a fully differentialoperational amplifier with again and a frequency response similar to the single output version. A Common ModeFeedBack circuit (CMFB) is designed to ensure that the differential outputs are tiedto a stabilized common mode voltage.

3.2.1 Design of the Single Output Operational Amplifier

The schematic of the operational amplifier with a single output is shown in figure 3.1.All transistors except the input differential pair M1 and M2and the biasing transistorsM3 and M12 are dimensioned to have an overdrive voltageVeff of approximately0.25 V.

Veff = 0.25 V (3.8)

The drain currentID3of M3 determines the bias currents of the NMOS differential

pair consisting of M1 and M2.ID3is determined by choosing a desired slew rate.

The slew rateSR of the folded cascode is approximately determined by [1, p. 307]:

SR =ID3

CL

⇔

ID3= SR CL (3.9)

A slew rate of40 V/µs is chosen in order to minimize the slewing behaviour of theoutput.ID3

is calculated by insertingSR = 40 V/µs andCL = 10 pF into (3.9).

ID3= 40 V/µs · 10 pF = 400 µA (3.10)

The gain bandwidthGB of the folded cascode is approximately given by [1, p. 307]:

GB =gm1

CL(3.11)

, wheregm1is the transconductance of the input differential pair transistors M1 and

M2.

15


Figure 3.1: The self biased folded cascode single output operational amplifier.

M1 and M2 has to be sized to be able to meet theGB requirement. The transconduc-tance of a NMOS transistor operating in the saturation region is given by

gm1=

√

k′n (W/L)1 ID1(3.12)

, where(W/L)1 is the dimensions andID1is the drain current of M1.

An expression for(W/L)1 is derived by combining (3.11) with (3.12).

GB =

√

k′n (W/L)1 ID1

CL⇔

(W/L)1 =GB2 CL

2

k′n ID1

(3.13)

The drain currentsID1andID2

are equal toID3/2.

ID1= ID2

=ID3

2= 200 µA (3.14)

(W/L)1 is calculated by insertingID1andCL andGB into (3.13).

(W/L)1 =(100π Mrad/s)2 · (10 pF)2

150 µA/V2 · 200 µA(3.15)

= 328.9868 ∼ 330 (3.16)

16


The output current of the PMOS current mirror consisting of M4 and M5 is set to beequal toID3

. The drain currentID4of M4 and M5 is therefore−ID3

.

ID4= −ID3

= −400 µA (3.17)

(W/L)4 and(W/L)5 of M4 and M5 is calculated from (3.17) and (3.8).

(W/L)4 = (W/L)5 =2ID4

k′pVeff2

=2 · (−400 µA)

−48 µA/V2 · 0.25 V

= 266.6667 ∼ 270

The drain current of the cascoding PMOS transistors M6 and M7is equal toID4+ID1

.

ID6= −400 µA + 200 µA = −200 µA (3.18)

(W/L)6 and(W/L)7 of M6 and M7 are calculated from (3.18) and (3.8).

(W/L)4 = (W/L)5 =2ID6

k′pVeff2

=2 · (−200 µA)

−48 µA/V2 · 0.25 V

= 133.3333 ∼ 134

The NMOS transistors M8 to M11 are forming a cascode current mirror. All fourtransistors have the same dimensions. The drain currentID8

is equal to−ID6.

ID8= 200 µA (3.19)

(W/L)8 is calculated from (3.19) and (3.8)

(W/L)8 =2ID8

k′nVeff2

=2 · 200 µA

150 µA/V2 · 0.25 V

= 42.6667 ∼ 43

The biasing NMOS transistors M3 and M12 have their gates connected to the biasvoltageVBIAS. M3 and M12 determines the bias currents of the operational amplifieras a function ofVBIAS. M12 will in the fully differential design be used to controlthe common mode voltage of the outputs. The CMFB circuit is going to be designedto have a control voltage equal to0 V when the common mode voltage is0 V. M3and M12 are therefore sized using a bias voltage ofVBIAS = 0 V. The gate voltage

17


VG3= VBIAS. The sources of M3 and M12 are tied to the negative supplyVss =

−1.25 V.

VG3= VBIAS = 0 V

VS3= Vss = −1.25 V

The overdrive voltageVeff3of M3 and M12 with a gate voltageVG3

equal toVBIAS

is

Veff3= VG3

− VS3− Vthn = 0 V + 1.25 V − 0.6 V = 0.65 V (3.20)

The dimensions of M3 and M12 are calculated using (3.20) andID3= 400 µA

(W/L)3 =2ID3

k′nVeff3

2

=2 · 400 µA

150 µA/V2 · (0.65 V)2

= 14.8148 ∼ 15

The resistors R1 and R2 are set to1250 Ω.

3.2.1.1 Simulation

All the transistors have been sized to have a length of1 µm.

The DC simulation has been used to reduce the output offset voltage as much as pos-sible with as little modification as possible. During the optimization the dimensionsof M6, M7 and M8 has been changed to128 µm and R1 has been changed to2500 Ω.The modified dimensions of the single output operational amplifier are listed in table3.1.

The DC operating points of the circuit can be found on the plotof the schematic infigure A.1 in Appendix A.

Both the AC and the transient simulations was performed using the modified transis-tor dimensions from table 3.1 and a capacitive load at the output of10 pF.

The frequency response of the operational amplifier is shownin figure 3.2. The mea-surements of the design requirements are listed below:

• DC-gainA0 = 78.41 dB

18


Transistor Width LengthM1 330 µm 1 µm

M2 330 µm 1 µm

M3 15 µm 1 µm

M4 270 µm 1 µm

M5 270 µm 1 µm

M6 128 µm 1 µm

M7 128 µm 1 µm

M8 43 µm 1 µm

M9 43 µm 1 µm

M10 43 µm 1 µm

M11 43 µm 1 µm

M12 15 µm 1 µm

M13 128 µm 1 µm

M14 270 µm 1 µm

Resistor ResistanceR1 1250 Ω

R2 2500 Ω

Table 3.1: Modified transistor dimensions of the single output operational amplifier.

• Gain bandwidth productGB = 54.15 MHz

• Phase marginPM = 68.78degrees

The slew rateSR was measured using a transient simulation where the operationalamplifier was connected as a buffer, with the differential input connected to a square-wave voltage source. The slew rate of the positve and the negative slope are denotedSR+ andSR− respectively.

SR+ = 40.5 V/µs (3.21)

SR− = 37.1 V/µs (3.22)

All of the design requirements have been met and exceeded except for the phasemargin. But the phase margin is acceptably close to70 degrees.

19


Gain Phase

100 101 102 103 104 105 106 107 108 109 1010freq (Hz)

100

75.0

50.0

25.0

0

−25.0

−50.0

−75.0

−100

Gai

n (d

B)

50.0

0

−50.0

−100

−150

−200

−250

Pha

se (

deg)

freq (Hz)

Figure 3.2: Bode plot of the single output operational amplifier.

3.2.2 The Fully Differential Operational Amplifier

The fully differential operational amplifier is a modified version of the single outputfolded cascode that was designed in the previous section. The schematic of the fullydifferential operational amplifier is shown in figure 3.3. The common mode voltageof the differential outputs is stabilized using a internal Common Mode FeedBack(CMFB) circuit. The transistor dimensions from the single output design are kept.

The differential operational amplifier has three additional transistors compared to thesingle output version. M15 are used to determine the currentflowing through thecascode current mirror consisting of M16 and M17. This current mirror is used tobias the two NMOS current sinks at the outputs. M16 and M17 areboth sized to havethe same dimensions as the transistors of the cascode current sinks, e.g. M8.

(W/L)16 = (W/L)17 = (W/L)8 = 43 (3.23)

The dimensions of M15 is initially set to half of M4 because the drain currentID16of

M16 and M17 approximately200 µA.

(W/L)15 =(W/L)4

2= 135 (3.24)

M3 and M12 are contrary to the single output design not biasedat the same gatevoltage. M3 is still biased usingVBIAS but M12 is now used to control the common

20


mode voltage level at the differential output. The gate of M12 is connected to theoutput voltageVctrl of the CMFB circuit.

Figure 3.3: The self biased folded cascode with differential outputs.

3.2.2.1 Common Mode Feedback Circuit (CMFB)

The common mode feedback is implemented using the CMFB circuit shown in figure3.4 [3, Fig. 6.19]. This circuit is connected to the positiveand negative output of theoperational amplifier. The output signal of the CMFB circuitVctrl is connected tothe gate of M12. The CMFB circuit creates negative feedback from the outputs to thegate of M12. This ensures that the output common mode voltageis stabilized arounda specific operating point. Which is ideally0 V.

The CMFB is designed to consume little power and utilize relatively small transistor,in order to minimize the capacitive loading of the operational amplifier outputs. Thefeedback signalVctrl should be equal to0 V when the common mode voltage at theoutputs is0 V.

Vctrl = 0 V (3.25)

The current sinks M7 and M8 are sized to meet the requirement of Vctrl = 0. Thegate voltageVG7

of M7 is equal toVctrl and the source is tied to the negative supply

21


Figure 3.4: The CMFB circuit.

Vss.

VG7= Vctrl = 0 V

VS7= Vss = −1.25 V

The dimensions(W/L)7 of M7 and M8 are set to 2 to reduce the size of the CMFBcircuit.

(W/L)7 = 2 (3.26)

The drain current flowing through M7 is calculated.

ID7=

1

2k′n (W/L)7 (VG7

− VS7− Vthn)2

=1

2150 µA/V2 · 2 · (VG7

− VS7− 0.6 V)2

= 63.375 µA (3.27)

The PMOS current source consisting of M5 and M6 is now sized using the resultfrom (3.27).

ID5= −ID7

= −63.375 µA

(W/L)5 =2ID5

k′p Veff2

=2 · (−63.375 µA)

−48 µA/V2 · (0.25 V)2

= 42.2500 ∼ 42 (3.28)

22


The drain currentID1flowing through each of the PMOS transistors of the differential

gain stage is half ofID5.

ID1=

ID5

2= −31.687 µA (3.29)

The dimensions of M1 are now calculated.

(W/L)1 =2 ID1

k′p Veff2

=2 · (−31.687 µA)

−48 µA/V2 · (0.25 V)2

= 21.1250 ∼ 22 (3.30)

3.2.2.2 Simulation

The simulation was conducted on a circuit consisting of the fully differential oper-ational amplifier with the CMFB circuit. All the transistorshas been implementedusing a transistor length of1 µm.

The transitor dimensions and resistor values have been optimized using the DC sim-ulation in order to minimize the common mode voltage at the outputs. The modi-fied transistor dimensions and component values of the operational amplifier and theCMFB circuit are listed in table 3.3 and 3.2 respectivelly.


M2 20 µm 1 µm

M3 20 µm 1 µm

M4 20 µm 1 µm

M5 40 µm 1 µm

M6 40 µm 1 µm

M7 2 µm 1 µm

M8 2 µm 1 µm

M9 40 µm 1 µm

Table 3.2: Modified transistor dimensions of the CMFB.

The DC operating points of the operational amplifier and the CMFB circuit can befound on the schematics shown in figure A.2 and A.3 in AppendixA.

The frequency response of the fully differential operational amplifier was measuredwith both outputs loaded by10 pF. The frequency response is plotted in figure 3.5.

23



M2 330 µm 1 µm

M3 15 µm 1 µm

M4 270 µm 1 µm

M5 270 µm 1 µm

M6 122 µm 1 µm

M7 122 µm 1 µm

M8 43 µm 1 µm

M9 43 µm 1 µm

M10 43 µm 1 µm

M11 43 µm 1 µm

M12 14 µm 1 µm

M13 122 µm 1 µm

M14 270 µm 1 µm

M15 128 µm 1 µm

M16 43 µm 1 µm

M17 43 µm 1 µm

Resistor ResistanceR1 1250 Ω

R2 1250 Ω

Table 3.3: Modified transistor dimensions of the fully differential operational amplifier.

The measurements of the design requirements are listed below:

• DC-gainA0 = 72.67dB

• Gain bandwidth productGB = 54.4 MHz

• Phase marginPM = 77.04 degrees

The DC-gain has decreased at the cost of a increased gain bandwidth and the phasemargin has increased above the 70 degrees. The fully differential operational ampli-fier satisfies all the design requirements.

24

3.3. SWITCHES

Gain Phase

100 101 102 103 104 105 106 107 108 109 1010freq (Hz)

75.0

50.0

25.0

0

−25.0

−50.0

−75.0

−100

Gai

n (d

B)

50.0

0

−50.0

−100

−150

−200

−250

Pha

se (

deg)

freq (Hz)

Figure 3.5: Bode plot of differential operational amplifier with CMFB.

3.3 Switches

Switches are an essential part of SC circuits because they control the charge flow inthe circuit. An ideal switch has no ON resistance and thus conducts a signal from theinput to the output without loss. MOSFET switches are non-ideal elements and theyprovides a resistive load between the capacitors in a SC circuit. This limits the rateof which the charge can be transferred between the capacitors. This has to be takeninto account when sizing the switches.

Some switches in SC circuit must be able to pass a fully differential voltage sig-nal. This can be done using a transmission gate which is a parallel combination of aNMOS and a PMOS transistor. This ensures that the switch willalways be conduct-ing even though either the PMOS or the NMOS transistor is in the cut-off region.

Other switches in SC circuits are connected to ground or virtual ground. Theseswitches does not have to be able to pass a full signal swing, and can therefore beimplemented using a single NMOS transistor.

All switches connected to ground or virtual ground in the first order and second or-der filter sections are implemented using NMOS switches. Allother switches areimplemented using transmission gates.

A MOSFET transistor is operating in the triode region when itis used as a switch.

25


The drain source resistanceRDS of a MOSFET operating in the triode region can befound using (3.31).

RDS =1

k′n (W/L)N Veff

This is only valid when the drain source voltage of the transistor is equal to or closeto zero, which is the case when the transistor is used as a switch. The switchesare implemented using the minimum transistor lengthLmin = 0.35 µm in order tominimize RDS . InsertingLmin into (3.31) gives an expression for the width of thetransistor.

(W/L)1 =1

k′n RDS1Veff1

⇔

W1 =Lmin

k′n RDS1Veff1

(3.31)

The time constant of a switch can be approximated by:

τ = RonCL (3.32)

, whereRon is the effective resistance andCL is the total capacitive load of the theswitch.

Each switch needs to be able to pass the signal from input to output in less than T/2.It is assumed that a first order circuit has reached its settling point after a periodtsettle = 5 τ .

tsettle = 5RonCL (3.33)

Using (3.33) yields an equation that can be used to determinethe largest allowablevalue of theRon to ensure that the charge transfer has settled during the ON period.

T

2≥ 5 Ron CL ⇔

Ron =T

10 CL

(3.34)

InsertingCL = 10 pF andT = 100 ns into (3.34) gives the maximum allowed ONresistance in order to satisfy the requirements.

Ronmax=

100 ns

10 · 10 pF= 1000 Ω (3.35)

26

3.3. SWITCHES

Figure 3.6: NMOS switch.

3.3.1 The NMOS Switch

The ON resistance of a NMOS switch is the drain source resistance RDSN. The

gate voltage of the NMOS transistor isVG1= Vdd and the overdrive voltage is

Veff1= 0.65 V assuming that the signal voltageVsig at the input of the switch is

close to zero. The widthW1 of the NMOS switch required to meet the settling timerequirement are calculated using (3.31).

W1 =Lmin

k′n RonmaxVeff

=0.35 µm

150 µA/V2 · 1000 Ω · 0.65 V

= 3.5897 µm ∼ 4 µm (3.36)

The calculated width is the minimum size allowed to satisfy the settling time require-ment. The NMOS switches are implemented with a transistor width of20 µm.

3.3.2 The Transmission Gate

The ON resistanceRon of the transmission gate, shown in figure 3.7, is the parallelcombination of the drain source resistancesRDS1

of the NMOS transistor andRDS2

of the PMOS transistor.

Ron = RDS1‖ RDS2

(3.37)

The worst case resistances of the transmission gate is now determined. A transmis-sion gate can operate in three possible states when it is ON. In the first state both theNMOS and the PMOS transistors are conducting.Ron is the parallel combination ofthe drain source resistancesRDS1

andRDS2. Ron has the smallest value during this

state.

The transmission gate is operating in the second state when only the NMOS transitoris conducting.Ron is in this state equal to theRDS1

. RDS1has the largest resistance

at the voltage where the PMOS transistor enters the cut-off region. This voltage can

27


Figure 3.7: Transmission gate switch.

be found by setting the overdrive voltage of the PMOS equal to0 V.

Veff2= 0 V (3.38)

The effective voltage of the NMOS transitor can be found by deriving the sourcevoltageVS2

of the PMOS from (3.38), which is equal to the signal voltageVsig at theinput of the transmission gate.

Veff2= VS2

− VG2+ Vthp ⇔

VS2= Veff2

+ VG2− Vthp

= 0 V − 1.25 V + 0.75 V

= −0.5 V (3.39)

The minimum width of the NMOS are calculated using (3.31).

W1 =Lmin

k′n RonmaxVS2

=0.35 µm

150 µA/V2 · 1000 Ω · (−0.5 V)

= 2.0290 µm ∼ 3 µm (3.40)

The transmission gate is operating in the third state when only the PMOS transistoris conducting, thusRon is equal to the drain source resistanceRDS1

of the PMOStransistor. The largest resistance of the PMOS transistor is calculated using the samemethod as for the NMOS transistor above.

Veff1= 0 V (3.41)

28

3.4. CREATING THE NON-OVERLAPPING CLOCK SIGNALS

Transistor Width Length

M1 10 µm 0.35 µm

M2 20 µm 0.35 µm

M3 0.35 µm 0.35 µm

M4 0.35 µm 0.35 µm

Table 3.4: Modified transistor dimensions of transmission gate switch.

Veff1= VG1

− VS1− Vthn ⇔

VS1= VG1

− Veff1− Vthn

= 1.25 V − 0 V − 0.6 V

= 0.65 V (3.42)

The minimum width of the PMOS are calculated using (3.31).

W2 =Lmin

k′p RonmaxVS1

=0.35 µm

−48 µA/V2 · 1000 Ω · 0.65 V

= 6.3406 µm ∼ 7 µm (3.43)

As for the NMOS switch the widths are the minimum required to fulfill the require-ments. The transmission gates are implemented withW1 = 10 µm and W2 =

20 µm. The final dimensions of the transmission gate transistors are listed in table3.4.

3.4 Creating the Non-Overlapping Clock Signals

The circuit used to generate the non-overlapping clock signals is based on the circuitpresented in [3, p. 398]. The circuit is shown in figure 3.8.

The digital gates are normally implemented using the minimum transistor dimensionfor both width and length, as they are usually not used to drive relatively large capac-itive loads. The clock generating circuit is loaded with thecombined capacitance theof all the NMOS transistors used as switches. The PMOS transistors are not directlyloading the clock generating circuit, as their gate capacitances are loading the localinverter. The NOR-gate transistors are dimensioned to realize a low output resistance,and thereby reducing the settling time of the clock signalsφ1 andφ2. This is done by

29


Figure 3.8: The non-overlapping clock generator.

setting the width to4 µm and the length is set to the minimum size of0.35 µm.

WNOR = 4 µm

LNOR = 0.35 µm

The inverter used to invert the reference clock signalclk is implemented using aNMOS and a PMOS transistor with the minimum dimensions allowed for the process.

WINV = 0.35 µm

LINV = 0.35 µm

Each delay block is implemented using 8 inverters in cascade. The inverters aredimensioned to realize a relatively large time constants inorder to increase the prop-agation delay. This is done to make a suitable delay betweenφ1 andφ2. The width isset to2 µm and the length is set to3 µm in order to increase the output resistance ofthe inverters.

WDLY = 2 µm

LDLY = 3 µm

Figure 3.9 shows the non-overlapping clock signalsφ1 andφ2 together with the ref-erence clock signalclk, during a transient simulation of the third order filter. Thedelay betweenφ1 andφ2 is measured to be approximately14.1 ns.

30

3.5. SAMPLE AND HOLD CIRCUIT

0 100 200 300 400 500time (ns)

1.5

1.0

.5

0

−.5

−1.0

−1.5

Vol

tage

(V

)V

olta

ge (

V)

1.5

1.0

.5

0

−.5

−1.0

−1.5

Vol

tage

(V

)V

olta

ge (

V)

1.5

1.0

.5

0

−.5

−1.0

−1.5

Vol

tage

(V

)V

olta

ge (

V)

Reference Clock

phi1

phi2

time (ns)

Figure 3.9: Transient plot of the non-overlapping clocks.

3.5 Sample and Hold Circuit

The output of the SC filter is only valid at the end ofφ1. It is therefore necessaryto sample the filter output atφ1. This is done by implementing a simple open loopsample and hold circuit shown in figure 3.10. The single output operational amplifierdesigned earlier is used to implement the buffers. The switches are implemented astransmission gates because they have to transfer the full signal swing. The holdingcapacitorsCs are set to1 pF.

Figure 3.10: The sample and hold circuit used to sample the filter output at φ1.

31


32

Chapter 4

Implementation of the Filter

At this point the capacitor ratios of the of the first and second order filter sectionshave been determined. All the components needed to implement the SC filter havebeen designed. The filters are now implemented in Cadence Virtuoso and simulatedusing the Spectre RF simulator.

The first order and the second order SC filter are simulated seperately to determinetheir individual frequency response and transient performance. Finally the two filtersections are combined to form the third order SC filter.

The transient simulations are performed with a1 MHz sine wave with an amplitudeof 500 mV applied to the differential input terminals of the filters.

The AC simulations are performed using the periodic small signal (PAC) analysis,which are performed after a periodic steady state (PSS) analysis. The PSS analysisdetermines the steady states of the circuit nodes when the switches duty cycles istaken into account. The frequency responses of the filters are measured at the dif-ferential output of the sample and hold circuit to ensure that the measurements arevalid.

4.1 First Order Filter

The integrating capacitorCA is set to be10 pF and the other capacitor are referencedto CA using the ratios listed in table 2.2. The schematic of the first order filter usedin the simulation is shown in figure B.1 in Appendix B. The simulation is performedusing the test bench shown in figure B.2 in Appendix B.

33

CHAPTER 4. IMPLEMENTATION OF THE FILTER

Amplitude Phase

10−1 100 101 102 103 104 105 106 107freq (Hz)

0

−2.5

−5.0

−7.5

−10.0

−12.5

−15.0

−17.5

Am

plitu

de (

dB)

25.0

0

−25.0

−50.0

−75.0

−100

−125

Pha

se (

deg)

freq (Hz)

Figure 4.1: Frequency response of the first order filter.

The frequency response of the first order filter is shown in figure 4.1.

The passband gain is measured to be:

Apass = −573.2 mdB (4.1)

It is a little lower than unity which is to expected because ofthe resitance of thenon ideal switches. The corner frequencyfc is measured at−3 dB relative to thepassband gain (−3.5732 dB).

fc = 1.8822 MHz (4.2)

This is almost two times higher than the1 MHz design requirement.

The transfer function of the first order section could be changed to take the -573.2mdB passband gain into account, by designing it to have a gainat of atleast 573.2mdB. Adjusting the corner frequency requires that the capacitor ratios are loweredto reduce the frequency of the transfer function pole. The filter output is valid upto 5 MHz because of sampling criterion, where the gain is approximately -8.5 dB,which is a little higher than is expected from a first order filter assuming a -20 dB perdecade asymptote.

The transient simulation of the filter is shown i figure 4.2. The output of the sampleand hold is at approximately 400 mV, which is expected based on the results of the

34

4.2. SECOND ORDER FILTER

0 1 2 3 4time (us)

750

500

250

0

−250

−500

−750

Vol

tage

(m

V)

Vol

tage

(m

V)

600

400

200

0

−200

−400

−600

Vol

tage

(m

V)

Vol

tage

(m

V)

600

400

200

0

−200

−400

−600

Vol

tage

(m

V)

Vol

tage

(m

V)

Input Signal

Filter Output

S/H Output

time (us)

Figure 4.2: Transient response of the first order filter.

frequency response. The output signal is as expected an inverted quantized sine wavebut it is not perfect. The charging and discharging of the capacitors during the sam-pling period is easily seen from the waveform. This effect could be minimized bylowering the capacitance of the integrating capacitorCA. Because the three other ca-pacitors are related toCA by fixed ratios, this would ideally reduce the time constantsin circuit without affecting the filtering performance.

4.2 Second Order Filter

The integrating capacitorsCB and CC is set to10 pF, all other capacitors in thesecond order filter are sized using the the capacitor ratios listed in table 2.3. Theschematic of the circuit is shown figure B.3 and the test benchis shown in figure B.4in Appendix B.

The frequency response of the first order filter is shown in figure 4.3.

The passband gain is measured to be:

Apass = −592.7 mdB (4.3)

As for the first order section the passband gain is a little lower than unity. The fre-quency response of the second order filter has to cross0 dB at 1 MHz in order to

35


Amplitude Phase

10−1 100 101 102 103 104 105 106 107freq (Hz)

10

0

−10

−20

−30

−40

−50

Am

plitu

de (

dB)

100

0

−100

−200

−300

−400

−500

Pha

se (

deg)

freq (Hz)

Figure 4.3: Frequency response of the second order filter.

meet the requirements. The0 dB crossing frequencyf0 dB is measured relatively tothe passband gain (−592.7 mdB):

f0 dB = 758 kHz (4.4)

f0 dB is lower than the required value. This can be compensated by increasing thedominant pole frequency of the second order transfer function. The less than unitygain can be compensated by modifying the gain of the transferfunction, as describedfor the first order sectio n above.

The transient response is plotted in figure 4.4. The output signal measured at thesample and hold circuit is a quantized sine wave inverted with respect to the inputsignal. The output signal doesn’t suffer from large time constants as the first ordersection did.

36

4.3. THIRD ORDER FILTER

0 1 2 3 4time (us)

750

500

250

0

−250

−500

−750

Vol

tage

(m

V)

Vol

tage

(m

V)

1000

750.0

500.0

250.0

0−250.0

−500.0

−750.0

−1000

Vol

tage

(m

V)

Vol

tage

(m

V)

750

500

250

0

−250

−500

−750

Vol

tage

(m

V)

Vol

tage

(m

V)

Input Signal

Filter Output

SH Output

time (us)

Figure 4.4: Transient response of the second order filter.

4.3 Third Order Filter

The third order filter is implemented by cascading the first order and the second orderfilter sections that were simulated above. The test bench used to perform the simu-lation is shown in figure B.5 in Appendix B. The input signal isfeed into the firstorder filter which is then connected to the second order filter. The output of the sec-ond order filter is connected to a differential sample and hold circuit. The frequencyresponse of the filter is measured at the output of the sample and hold circuit, and isshown in figure 4.5.

The passband gain of the third order filter is measured to be

Apass = −2.348 dB (4.5)

The passband gain is lower than unity and is approximately 1.17 dB lower than ex-pected by cascading the first order filter (-573.2 mdB) and thesecond order filter(-592.7 mdB).

The corner frequencyfc is measured at−3 dB relative to the passband gain (−5.348 dB).

fc = 1.003 MHz (4.6)

The corner frequency are measured to be very close to the design requirement. A

37


Amplitude Phase

10−1 100 101 102 103 104 105 106 107freq (Hz)

0

−10

−20

−30

−40

−50

Am

plitu

de (

dB)

100

0

−100

−200

−300

−400

−500

−600

−700

Pha

se (

deg)

freq (Hz)

Figure 4.5: Frequency response of the third order filter.

difference of approximately 8 kHz is very acceptable but thefilter doesn’t satisfy theunity gain passband requirement.

The transient response of the filter is plotted in figure 4.6. The output of the sampleand hold circuit is as expected a quantized sine wave. But theamplitude is about halfof the input sine wave. The transient output of the first ordersection in third orderfilter is very similar to the transients results of the first order section when it wasmeasured separately. The signal has the same amplitude level and characteristics.The output of the second order filter has a waveform similar tothat simulated earlierbut has a significantly lower amplitude. A possible explanation could be that thesecond order section was not tested with additional capacitance equivalent to theoutput capacitance of the first order section. This additional capacitance has thenaffected the gain of the second order section, yielding a lower gain than theoreticallyexpected from the cascade combination.

38

4.3. THIRD ORDER FILTER

0 1 2 3 4time (us)

750500

2500

−250

−500−750

Vol

tage

(m

V)

Vol

tage

(m

V)

600400

2000

−200

−400−600

Vol

tage

(m

V)

Vol

tage

(m

V)

750500

2500

−250

−500−750

Vol

tage

(m

V)

Vol

tage

(m

V)

400

0

−400

Vol

tage

(m

V)

Vol

tage

(m

V)

Input Signal

First Order Output

Second Order Output

S/H Third Order Output

time (us)

Figure 4.6: Transient response of the third order filter.

39


40

Chapter 5

Conclusion

The integrated third order Butterworth SC filter was first designed mathematically asa transfer function. The transfer function was then used to synthesize the third orderfilter using a cascade of a first order and second order section. All the necessarycomponents required to implement the filter in a CMOS processwas then designed.Finally the filter was successfully implemented and tested in Cadence Virtuoso usingthe Specttre simulator.

The frequency response of the filter was only partly satisfying the design require-ments. The corner frequency of filter response was very closeto the desired value.The passband gain requirement was not met and was at an unacceptable level.

Even though the performance of the filter did not satisfy the design requirements, theimplementation of the filter and all of the necessary components yielded a functioningfilter that confirmed the theory of SC filters.

The most time consuming part of the project was the design of the necessary compo-nents needed to implement the SC filter. Once the designs of the components weredone they were simply wired together to realize the SC filter.

Optimization of the third order filter to satisfy the design requirements should bepossible by iterating through the processes of optimizing the transfer functions, cal-culating the modified capacitor ratios, performing capacitance matching, simulatingthe filter using the new capacitance values.

41

CHAPTER 5. CONCLUSION

42

Appendix A

Operational Amplifier CadenceSchematics

Figure A.1: Single output operational amplifier Cadence schematic.

43

APPENDIX A. OPERATIONAL AMPLIFIER CADENCE SCHEMATICS

Figure A.2: Differential output operational amplifier Cadence schematic.

Figure A.3: CMFB Cadence schematic

44

Appendix B

Filter Cadence Schematics

Figure B.1: First order filter Cadence schematic.

45

APPENDIX B. FILTER CADENCE SCHEMATICS

Figure B.2: First order filter simulation test bench.

Figure B.3: Second order filter Cadence schematic.

46

Figure B.4: Second order filter simulation test bench.

Figure B.5: Third order filter simulation test bench.

47

APPENDIX B. FILTER CADENCE SCHEMATICS

48

LIST OF FIGURES

List of Figures

2.1 First order switched capacitor filter section . . . . . . . . .. . . . . . 4

2.2 Second order switched capacitor low-Q biquad filter section . . . . . 5

2.3 Bode plot of the seperate and cascaded transfer functions. . . . . . . . 8

2.4 Frequency responses of the modified transfer functions compared to the originals. 11

3.1 The self biased folded cascode single output operational amplifier. . . 16

3.2 Bode plot of the single output operational amplifier. . . .. . . . . . . 20

3.3 The self biased folded cascode with differential outputs. . . . . . . . . 21

3.4 The CMFB circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.5 Bode plot of differential operational amplifier with CMFB. . . . . . . 25

3.6 NMOS switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.7 Transmission gate switch. . . . . . . . . . . . . . . . . . . . . . . . . 28

3.8 The non-overlapping clock generator. . . . . . . . . . . . . . . .. . 30

3.9 Transient plot of the non-overlapping clocks. . . . . . . . .. . . . . 31

3.10 The sample and hold circuit used to sample the filter output atφ1. . . 31

4.1 Frequency response of the first order filter. . . . . . . . . . . .. . . . 34

4.2 Transient response of the first order filter. . . . . . . . . . . .. . . . 35

4.3 Frequency response of the second order filter. . . . . . . . . .. . . . 36

4.4 Transient response of the second order filter. . . . . . . . . .. . . . . 37

49

LIST OF FIGURES

4.5 Frequency response of the third order filter. . . . . . . . . . .. . . . 38

4.6 Transient response of the third order filter. . . . . . . . . . .. . . . . 39

A.1 Single output operational amplifier Cadence schematic.. . . . . . . . 43

A.2 Differential output operational amplifier Cadence schematic. . . . . . 44

A.3 CMFB Cadence schematic . . . . . . . . . . . . . . . . . . . . . . . 44

B.1 First order filter Cadence schematic. . . . . . . . . . . . . . . . .. . 45

B.2 First order filter simulation test bench. . . . . . . . . . . . . .. . . . 46

B.3 Second order filter Cadence schematic. . . . . . . . . . . . . . . .. . 46

B.4 Second order filter simulation test bench. . . . . . . . . . . . .. . . . 47

B.5 Third order filter simulation test bench. . . . . . . . . . . . . .. . . 47

50

LIST OF TABLES

List of Tables

2.1 Capacitor ratios of the second order biquad section. . . .. . . . . . . 9

2.2 Modified capacitor ratios of the first order section. . . . .. . . . . . . 10

2.3 Modified capacitor ratios of the second order biquad section. . . . . . 10

3.1 Modified transistor dimensions of the single output operational amplifier. 19

3.2 Modified transistor dimensions of the CMFB. . . . . . . . . . . .. . 23

3.3 Modified transistor dimensions of the fully differential operational amplifier. 24

3.4 Modified transistor dimensions of transmission gate switch. . . . . . . 29

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LIST OF TABLES

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BIBLIOGRAPHY

Bibliography

[1] Phillip E. Allen and Douglas R. Holberg.CMOS Analog Circuit Design. OxfordUniversity Press, second edition, 2002.

[2] Austria Micro Systems.0.35 µm CMOS C35 Process Parameters, 2007. Revi-sion 5 - Eng-182.

[3] David Johns and Ken Martin.Analog Integrated Circuit Design. Wiley, firstedition, 1996.

[4] B. P. Lathi. Signal Processing and Linear Systems, USA. Oxford UniversityPress, 2000.

[5] Adel S. Seedra and Kenneth C. Smith.Microelectronic Circuits. Oxford Univer-sity Press, USA, fifth edition, 2003.

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