design of envelope amplifier based on interleaved

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Universidad Politécnica de Madrid

Design of envelope amplifier based on interleaved multiphase

buck converter with minimum time control for RF application

P. M. Cheng

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IV Annual Meeting

2011 March

Introduction

D.Brubaker, “Optimizing Performance and Efficiency of PAs in Wireless Base Stations: Digital pre-distortion reducessignal distortion at high power levels”, White Paper, Texas Instruments, February 2008

Complex signal and non-constant envelope in new wireless standards

High efficiency PA architectures are needed for high peak to average power ratio envelope.

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2011 March

Power amplifer architectures

Envelope Tracking (ET)

Envelope eliminationand restoration (EER)

DC-DC converter with output Voltage in proportion to RF envelope

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IV Annual Meeting

2011 March

Envelope amplifier solutions

Switching dc-dc converter

High efficiency of power amplifier

low Bandwidth or low power applications

High switching losses for wide envelope bandwidth

V. Pinon, F. Hasbani, A. Giry, D. Pache, C. Gamier, "A Single-Chip WCDMA Envelope Reconstruction LDMOS PAwith 130MHz Switched-Mode Power Supply," Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of TechnicalPapers. IEEE International , vol., no., pp.564-636, 3-7 Feb. 2008

Switching DC-DC converter

PARF OUT

Envelope reference

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2011 March


Linear Regulator in parallel with Switching dc-dc converter

High efficiency

Fast dynamic response (Wide Bandwidth)

F.Wang, D.F.Kimball, J.D.Popp, A.H.Yang, D.Y.Lie, P.M.Asbeck, L.E.Larson, “An Improved Power-Added Efficiency 19-dBmHybrid Envelope Elimination and Restoration Power Amplifier for 802.11g WLAN Applications”, IEEE Transactions onMicrowave Theory and Techniques, Volume 54, Number 12, December 2006, pages 4086-4099

Switching DC-DC converter

PARF OUT

Envelope reference

Linear Regulator

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2011 March


Multilevel DC-DC converter in series with a linear regulator

dc-dc converterLinear Reg.

VOVA

Control

VIN

VR

Multilevel converter

Control

time

Volta

ge

1 122 level

level levellevel

st st

nd nd

n levelth n levelthVA

VR

VO

High system bandwidth

High efficiency

Power saved

VO

time

Volta

ge

VR

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IV Annual Meeting

2011 March


Proposed solution

Minimum time control

d=1

d=0.5

d=0.75

d=0.25

time

volta

ge

PWMd=25%

PWMd=50%


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IV Annual Meeting

2011 March

Multiphase buck converter

Operates in open loop Without current andvoltage senses

Only has discrete dutycycles d=i/n, i=1, 2…n (n

is the number of phases)

Inductor design trade off Small L for fast transition Small L leads to high losses

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IV Annual Meeting

2011 March


Z. Zhao, A. Prodic, “Continuous-Time DigitalController for High-Frequency DC-DC converters”,IEEE Transactions on Power Electronics, vol. 23, no.2 March 2008, pp. 564-573.


A single on-off action of power switches for each phase

Charge balance

Control parameters (ton and toff) are stored in look-up table

Minimum transition time is fixed by filter

and the voltage before and after the

transition

),,,(),,,(,

FIi

FIiON

VVCLftVVCLft

=∆

=

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IV Annual Meeting

2011 March




No need to know the load current for transition

Very fast voltage transition

The currents unbalance does not have influence during the transition

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IV Annual Meeting

2011 March

Control strategy in 4 phases buck converter

Transition is synchronized with rising or falling edge of PWM

Different tON,i and tOFF,i but the same ∆t for each phase

t

t

t

t

phase1

phase2

phase3

phase4

90° delay

180° delay

270° delay

t

t

t

t

phase1

phase2

phase3

phase4


90° delay

180° delay

270° delay

t

t

t

t

phase1

phase2

phase3

phase4


90° delay

180° delay

270° delay

After the transition the phases maintain the synchronization

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IV Annual Meeting

2011 March

Control implementation in FPGA

quantization

counter1Pwm_state

Non_pwm_state

PWM1

counter2

PWM2

counter3PWM3

counter4

PWM4

PWMA

PWMB

PWMC

PWMD

Input data

Duty cycle

tON,1, tON,2, tON,3, tON,4, Δt memory

reset

reset

reset

reset

Counter

register

Initial value

The change of the duty cycle

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2011 March

Multilevel converter experiment result

Output voltage

Phase currents

3V 6Vton1

ton2

ton3

ton4

transient

Current unbalance

VIN = 12Vfsw = 1MHz

around 1.5 switching period

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IV Annual Meeting

2011 March

Envelope amplifier experiment result

VIN = 12Vfsw = 1MHz Output of envelope amplifier

Output of multilevel converter

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IV Annual Meeting

2011 March

Conclusion

Solution for the wide bandwidth envelope amplifier

Based on multiphase buck converter with minimum time control

Multiphase buck converter works in open-loop

Without voltage and current feedback

Minimum time control algorithm for multiphase buck converter is based on charge balance

Without over-shoot and oscillation after transition

dc-dc converterLinear Reg.

VOVA

Control

VIN

VR


Minimum time Control

The proposed solution can track fast envelope change with relatively low switching frequency and it also can be used for DVS application

It is necessary to improve design for higher frequency envelope and optimize the efficiency in the future

design of envelope amplifier based on interleaved

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