design of high-speed serial-links in cmos...src review 9/10/03 w. namgoong, usc 1 design of...
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SRC Review 9/10/03 W. Namgoong, USC 1
Design of High-Speed Serial-Links in CMOS
(Task ID: 930.001)
SRC Research ReviewSeptember 10, 2003
Won NamgoongUniversity of Southern California
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Design of High-Speed Serial-Links in CMOS
• Technical Thrust– Circuit Design
• Students– Kyongsu Lee– Lei Feng
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Accomplishments for 2003
• Developed adaptive/synchronization techniques for frequency channelized receivers.
• Designed a serial-link prototype based on frequency channelization.– Currently in fabrication.
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Outline of Talk
• Adaptive frequency channelized receiver.• Frequency channelized receiver
implementation.• Research plans for next year.
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Background in Signaling
• Transistor mismatches.• On-chip noise.• Inter-symbol interference.
– Wire losses and package parasitics.– Finite receiver/transmitter bandwidth.
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Existing Architecture – Time-Interleaved Receiver
• Sample at approx. Nyquist rate; 2-4 bit ADC’s (flash).• ADC sees the full bandwidth of the input signal.
– Sample/hold circuitry difficult to design.– Sensitive to sampling jitter and sample-time offsets.
• Large input capacitance.
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Frequency Channelized Receiver
• Achieves the same effective sampling frequency as time-interleaved receiver using the same number of ADCs.
• ADC input bandwidth reduced.– Sample/hold circuitry relaxed.– More robust to sampling jitter even with mixer phase noise present.
• Reduced input bandwidth.
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Adaptive Frequency Channelized Receiver Overview
• Adaptive synthesis filter bank.– Equalize distortion caused by the propagation channel
and reconstruct the channelized signal for detection.– Analog analysis filter bank not accurately known at
design time.– Error signal based on the detected symbol.
• Digital interpolators.– ADC sampling frequency generally not an integer
multiple of the symbol frequency. – Interpolation must occur after synthesis filter bank.
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Overall Receiver Structure
• Timing/detection module extracts timing information and detects transmitted symbol.
• Adaptive control module generates error signal used to update the adaptive synthesis filter bank.
AdaptiveFilterBank
TrainingSymbols
][ls ][ma
Delay
TimingController
ReferenceInterpolator
TimingRecovery
Backward TimingPrediction
DetectionInterpolator Detector
Adaptive Control Module
Timing/Detection Module
+-
][ˆ nd
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Adaptive Filter Bank (1)
ADC
ADC
ADC
2exp tfj sampleπ−
)1(2exp tfMj sample−− π
)()( tntx + ][0 ls
][1 ls
][1 lsM−
-][ne
+][nd
γ↑ )(0 zG
)(1 zG
)(1 zGM−γ↑
γ↑
][0 ny
][1 nyM−: :
Re ⋅
)( ΩjH
)( ΩjH
)( ΩjH][nd
samplef
samplef
samplef
• Effective sampling frequency , where γ = 2M – 1.• Re applied since transmitted signal is a baseband real signal.
sampleeff ff ⋅=γ
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Adaptive Filter Bank (2)][0 ls
][1 lsM−
][ lz γ
][ le γ
)(0,0 zW
)(0,1 zWM−:
-
]1[ −+ γγlz
+][nd
)(1,0 zW −γ
)(1,1 zWM −− γ
:
: :
Re ⋅
Re ⋅
]1[ −+ γγle][ne
code channel 0
code channel 1−γ
][ˆ nd
• Synthesis filter bank is LPTV system with period γ.• Each code channel estimates one of γ consecutive samples.• LMS adapts each code channel independently:
][][][]1[ ilelll ii ++=+ γεsww
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Timing/Detection Module
LoopFilterNCO
][meT][meTLmµ
][nη
][maDetection
Interpolator Detector][mu
M&MTiming Error
Detector
OverflowComputeFractionalIntervalTiming Controller
][ˆ nd
Timing Recovery
• Detection interpolator resamples to symbol rate.• Timing recovery determines timing error that
controls interpolator.
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Adaptive Control Module
ReferenceInterpolator
]'[nd]'[ne Symbols
rDnn −=′
+
-
rDDelay
NCO
n′ξ
][nηComputeFractionalInterval
Backward Timing Predictor
ComputePast
Overflow
][nwNCO
][ˆ nd
][ˆ nd ′ Overflow
• Backward timing predictor calculates timing information of delayed filter bank output based on current NCO state.– Delayed for used in DD mode.
• Reference interpolator generates desired reference signal.
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Simulation Results –Convergence Performance
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Simulation Results – Effect of Filter Taps
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Simulation Results – Effect of ADC Bits
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Summary of Adaptive Frequency Channelized Receiver Work
• Based on frequency channelized signals, an adaptive synchronization/detection scheme is described.
• Performance of proposed receiver is similar to that of a single channel receiver.– Convergence time is slightly longer.
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Implementation of Frequency Channelized Receiver
• A frequency channelized receiver excluding the digital back-end has been implemented in 0.25um CMOS.
• Symbol rate of 10Gsymbols/sec.• Three frequency subbands and 10 3-bit
ADC’s each operating at 1.24Gsamples/sec.• Currently in fabrication.
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System ArchitectureΩ50 fof 3dB- =
I/Q 2fo
I/Q 4fo
fofs =
LPF ADC
2fo 4fo
ADC
LPF ADC
ADC
LPF ADC
ADC
LPF ADC
ADC
LPF ADC
ADC
signalinput alDifferenti
driver Output &
decoderGray
2
1.24Gfo =
freq.
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Quad-Phase Mixing
• Conventional passive double balanced mixer.• 50 ohm matching allows wide input bandwidth: ~6.5GHz.
SIGV+LOI+
SIGV-LOI-
LOQ+
LOQ-
LOI+
LOI-
LOI+
I+
I−
Q+
Q−
Ω50
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Low Pass Filtering
• Vc adjusts gm of transistor M1 to control gain without affecting bandwidth.
• Achieves 20dB gain with 1.4GHz 3-dB bandwidth.
4-stage Feedback LPFBuffer
SR
FR
SR
FRVc
BV
CMFB1MMa
iR OR
Freq.
[dB]Gain
80dB/dec−
20dB/dec−
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ADC Architecture
LPF
1.24Gf 3dB =−
ADC
ADC
1.24Gf s =
• 2 Time-interleaved 3-bit ADC
• Each 3-bit ADC samples at 1.24Gsps.• Effective sampling rate/channel is 2.48Gsps.• No offset scheme necessary.
• ADC architecture
a6
PVNV
ref
a5 a4 a3 a2 a1 a0
comparator
sampler
latch
CLK
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Local Oscillator Frequency Generation
BPF LPF VCO
4fo
4fo phase-4
Doubler Freq.
phase-Quad mixer drive ⇒
2fo aldifferenti phase-Quad
DividerFreq.
fo phase-2
2fo phase-4 mixer drive ⇒
converter Code ADC, drive ⇒
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ADC & DECODER
LPF
MIXER &LO SIGNALINTERFACE
Freq. Doubler
Chip Layout
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Plans for Next Year• Fabricate and test design prototype to verify main
concepts.• Develop/analyze more sophisticated adaptive
reception algorithms based on maximum-likelihood sequence estimation (MLSE).– Faster convergence speed and higher performance.
• Design transmitter/receiver to support higher rates.– Multi-level signaling.– OFDM based communication systems.