design of sram in verilog
TRANSCRIPT
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Design Of Dual Port SRAM Using Verilog HDL
TABLE OF CONTENTS
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List of figures
List of tables
Ca!ter " #NTRODUCT#ON
"$" Design Ob%e&ti'es
"$( ACCOMPL#SHMENTS
Ca!ter ( L#TERATURE REV#E)
Ca!ter *
*$" Design ofSRAM
*$( SRAM O!eration
Ca!ter + #ntro,u&tion to FP-A ,esign Flo.
+$" #NTRODUCT#ON TO VLS# / FP-A DES#-N FLO)
+$"$" Design Entr0
+$"$( S0ntesis
+$"$*$ #1!le1entation
+$"$*$" Translate
+$"$*$( Ma!
+$"$*$* Pla&e an, Route
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+$"$+ De'i&e Progra11ing
+$"$2 Design Verifi&ation
+$"$3 Bea'ioral Si1ulation
+$"$4 Fun&tional si1ulation
+$"$5$ Stati& Ti1ing Anal0sis
Ca!ter 2 VER#LO- #NTRODUCT#ON
Ca!ter 3 Si1ulation Results
Ca!ter 4 Con&lusion an, Future S&o!e
Bibliogra!0 an, Referen&es
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ABSTRACT
Low power and low area Static Random Access Memory (SRAM) is essential
for System on Chip (SoC) technology. Dual-ort (D) SRAM greatly reduces the
power consumption !y full current-mode techni"ues for read#write operation and the
area !y using Single-ort (S) cell. An $ !it D-SRAM is proposed in this study.
%egati&e !it-line techni"ue during write has !een utili'ed for write-assist solutions.
%egati&e &oltage is generated on-chip using capaciti&e coupling. he proposed circuit
design topology does not affect the read operation for !it interlea&ed architectures
ena!ling high-speed operation. Designed in *L*% *S+ ,. Simulation results and
comparati&e study of the present scheme with state of-the art con&entional schemes
proposed .show that the proposed scheme is superior in terms of process-&ariations
impact area o&erhead timings and dynamic power consumption. he proposed
negati&e !itline techni"ue can !e used to impro&e the write a!ility of / Single-ort
(S) as well as $ D and other multiport SRAM cells.
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CHAPTER "
#NTRODUCT#ON
Most systems contain the following 0inds of memories1
2R3M
2 +R3M
2 ++R3M#4lash
2 DRAM
2SRAM
R3Ms +R3Ms and 4lash memories come under the cat- egory of non&olatile
memories. %on&olatile memories are de&ices that will store data e&en when the power
to the de&ice is remo&ed. R3Ms +R3Ms and 4lash memories differ in the
technology used and method !y which the user reprograms the de&ice and the method
!y which the user erases the data in the memory de&ice. SRAM and DRAM are
random access memories that can store data as long as power is applied to the de&ice.
*f the power is e&er remo&ed all data that was stored in the mem- ory will !e lost.
+&en when powered in DRAMs data could !e lost if it is not periodically refreshed5
while in SRAMs the data can !e stored without any 0ind of e6tra processing or
refresh- ing. he data will remain in t he SRAM once it has !een writ- ten there as
long as the power supply to the de&ice is maintained. SRAMs are differentiated from
their other memory counter- parts !y the type of the memory cell. %early all SRAMs
either use a -transistor or a /-tran sistor Memory Cell. hese cell structures allow
data to !e stored for an indefinite amount of time in the de&ice as long as it is
powered. 4igure ,!elow shows the -transistor and the /-transistor cell. (hese are
usually referred to as the - and the /- cells respecti&ely.) he SRAM cell is
formed !y two cross-coupled in&erters. System e&olution o&er time has led to the
creation of different types of SRAMs. he ne6t section goes into the details of the
different 0inds of SRAMs and their applications.
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A si6-transistor CM3S SRAM cell.
Tools Re6uire,7
Si1ulators7Modelsim /.7! ilin6 ,8.,i *sim SimulatorS0ntesis7 ilin6 ,. S (ilin6 Synthesis echnology) Synthesi'er$
FP-A Fa1il07ilin6 Spartan 9+ C9S7::+.
"$( ACCOMPL#SHMENTS7
his section descri!es the wor0 done in the pro;ect. he accomplishments are
categori'ed in to four main phases of the pro;ect in chronological order1
,. Literature Re&iewa. Sur&eyed the theory on memories .
!. Studied the concept of Static RAM.8. *nitially done a pen and paper wor0 and designed a top le&el !loc0 diagram of
SRAM9. Design hase
a. Designed a top le&el module of SRAM in
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!. Applied different test cases for the multiplier in the
dri&er section of the test !ench and performed
!eha&ioral simulation for the top le&el module.7. Synthesis hase
a. erformed logic synthesis ranslate Map lace and
Route processes and synthesis report is generated.
CHAPTER (
L#TERATURE REV#E)
Se1i&on,u&tor 1e1or0is an electronic data storage de&ice often used as computer
memory implemented on a semiconductor-!ased integrated circuit. *t is made in
many different types and technologies.
Semiconductor memory has the property of random access which means that it ta0es
the same amount of time to access any memory location so data can !e efficiently
accessed in any random order.?,@his contrasts with data storage media such as hard
dis0s and CDswhich read and write data consecuti&ely and therefore the data can
only !e accessed in the same se"uence it was written. Semiconductor memory also
has much faster access timesthan other types of data storage5 a!yteof data can !e
written to or read from semiconductor memory within a few nanoseconds while
access time for rotating storage such as hard dis0s is in the range of milliseconds. 4or
these reasons it is used for main computer memory(primary storage) to hold data the
computer is currently wor0ing on among other uses.
Shift registers processor registers data !uffersand other small digital registers that
ha&e no memory address decoding mechanism are not considered as memory
although they also store digital data.
http://en.wikipedia.org/wiki/Data_storage_devicehttp://en.wikipedia.org/wiki/Computer_memoryhttp://en.wikipedia.org/wiki/Computer_memoryhttp://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/Random_access_memoryhttp://en.wikipedia.org/wiki/Semiconductor_memory#cite_note-Dawoud-1http://en.wikipedia.org/wiki/Hard_diskhttp://en.wikipedia.org/wiki/Hard_diskhttp://en.wikipedia.org/wiki/Compact_diskhttp://en.wikipedia.org/wiki/Access_timehttp://en.wikipedia.org/wiki/Bytehttp://en.wikipedia.org/wiki/Nanosecondhttp://en.wikipedia.org/wiki/Computer_memoryhttp://en.wikipedia.org/wiki/Shift_registerhttp://en.wikipedia.org/wiki/Processor_registerhttp://en.wikipedia.org/wiki/Data_bufferhttp://en.wikipedia.org/wiki/Address_decoderhttp://en.wikipedia.org/wiki/Computer_memoryhttp://en.wikipedia.org/wiki/Computer_memoryhttp://en.wikipedia.org/wiki/Semiconductorhttp://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/Random_access_memoryhttp://en.wikipedia.org/wiki/Semiconductor_memory#cite_note-Dawoud-1http://en.wikipedia.org/wiki/Hard_diskhttp://en.wikipedia.org/wiki/Hard_diskhttp://en.wikipedia.org/wiki/Compact_diskhttp://en.wikipedia.org/wiki/Access_timehttp://en.wikipedia.org/wiki/Bytehttp://en.wikipedia.org/wiki/Nanosecondhttp://en.wikipedia.org/wiki/Computer_memoryhttp://en.wikipedia.org/wiki/Shift_registerhttp://en.wikipedia.org/wiki/Processor_registerhttp://en.wikipedia.org/wiki/Data_bufferhttp://en.wikipedia.org/wiki/Address_decoderhttp://en.wikipedia.org/wiki/Data_storage_device -
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"$" Des&ri!tion
*n a semiconductor memory chip each !itof !inary data is stored in a tiny circuit
called a memory cellconsisting of one to se&eral transistors. he memory cells are
laid out in rectangular arrays on the surface of the chip. he ,-!it memory cells are
grouped in small units called words which are accessed together as a single memory
address. Memory is manufactured in word length that is usually a power of two
typically %, 8 or $ !its.
Data is accessed !y means of a !inary num!er called a memory addressapplied to the
chipBs address pins which specifies which word in the chip is to !e accessed. *f the
memory address consists of M !its the num!er of addresses on the chip is 8 M each
containing an % !it word. Conse"uently the amount of data stored in each chip is %8 M
!its.?,@he data capacity is usually a power of two1 8 $ ,/ 98 / ,8$ 87/ and
7,8 and measured in 0i!i!its me!i!itsgi!i!itsor te!i!its etc. Currently (8:,) the
largest semiconductor memory chips hold a few gi!i!its of data !ut higher capacity
memory is constantly !eing de&eloped. y com!ining se&eral integrated circuits
memory can !e arranged into a larger word length and#or address space than what is
offered !y each chip often !ut not necessarily apower of two.?,@
he two !asic operations performed !y a memory chip are read in which the data
contents of a memory word is read out (nondestructi&ely) and write in which data
is stored in a memory word replacing any data that was pre&iously stored there. o
increase data rate in some of the latest types of memory chips such as DDR SDRAM
multiple words are accessed with each read or write operation.
*n addition to standalone memory chips !loc0s of semiconductor memory are integral
parts of many computer and data processing integrated circuits. 4or e6ample the
microprocessorchips that run computers contain cache memoryto store instructions
awaiting e6ecution.
http://en.wikipedia.org/wiki/Binary_digithttp://en.wikipedia.org/wiki/Memory_cell_(computers)http://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/Word_lengthhttp://en.wikipedia.org/wiki/Memory_addresshttp://en.wikipedia.org/wiki/Semiconductor_memory#cite_note-Dawoud-1http://en.wikipedia.org/wiki/Kibibithttp://en.wikipedia.org/wiki/Mebibithttp://en.wikipedia.org/wiki/Gibibithttp://en.wikipedia.org/wiki/Tebibithttp://en.wikipedia.org/wiki/Power_of_twohttp://en.wikipedia.org/wiki/Semiconductor_memory#cite_note-Dawoud-1http://en.wikipedia.org/wiki/DDR_SDRAMhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Cache_memoryhttp://en.wikipedia.org/wiki/Binary_digithttp://en.wikipedia.org/wiki/Memory_cell_(computers)http://en.wikipedia.org/wiki/Transistorhttp://en.wikipedia.org/wiki/Word_lengthhttp://en.wikipedia.org/wiki/Memory_addresshttp://en.wikipedia.org/wiki/Semiconductor_memory#cite_note-Dawoud-1http://en.wikipedia.org/wiki/Kibibithttp://en.wikipedia.org/wiki/Mebibithttp://en.wikipedia.org/wiki/Gibibithttp://en.wikipedia.org/wiki/Tebibithttp://en.wikipedia.org/wiki/Power_of_twohttp://en.wikipedia.org/wiki/Semiconductor_memory#cite_note-Dawoud-1http://en.wikipedia.org/wiki/DDR_SDRAMhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Cache_memory -
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"$( T0!es
RAM chips for computers usually come on remo&a!le memory modulesli0e these.
Additional memory can !e added to the computer !y plugging in additional modules.
RAM (Random access memory) has !ecome a generic term for any semiconductor
memory that can !e written to as well as read from in contrast to R3M (!elow)
which can only !e read. All semiconductor memory not ;ust RAM has the property
of random access.
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o FPM DRAM(4ast page mode DRAM) An older type of asynchronous
DRAM that impro&ed on pre&ious types !y allowing repeated accesses
to a single page of memory to occur at a faster rate. Esed in the mid-
,FF:s.
o EDO DRAM (+6tended data out DRAM) An older type of
asynchronous DRAM which had faster access time than earlier types
!y !eing a!le to initiate a new memory access while data from the
pre&ious access was still !eing transferred. Esed in the later part of the
,FF:s.
o VRAM (
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DDR* SDRAM transfers $ consecuti&e words per
internal cloc0 cycle.
DDR+ SDRAM transfers ,/ consecuti&e words per
internal cloc0 cycle. *t is scheduled to de!ut in 8:,8.
RDRAM (Ram!us DRAM) an alternate dou!le data rate
memory standard that was used on some *ntel systems !ut
ultimately lost out to DDR SDRAM.
S-RAM (Synchronous graphics RAM) a speciali'ed type of
SDRAM made for graphics adaptors (&ideo cards). *t canperform graphics-related operations such as !it mas0ing and
!loc0 write and can open two pages of memory at once.
PSRAM (seudostatic RAM) his is DRAM which has
circuitry to perform memory refreshon the chip so that it acts
li0e SRAM allowing the e6ternal memory controller to !e shut
down to sa&e energy. *t is used in a few porta!le game
controllers such as the >ii.
SRAM (Static random-access memory) which relies on se&eral transistors
forming a digital flip-flop to store each !it. his is less dense and more
e6pensi&e per !it than DRAM !ut faster and does not re"uire memory refresh.
*t is used for smaller cache memories in computers.
Content8a,,ressable 1e1or0his is a speciali'ed type in which instead of
accessing data using an address a data word is applied and the memory
returns the location if the word is stored in the memory. *t is mostly
incorporated in other chips such as microprocessors where it is used for cache
memory.
%on&olatile memorypreser&es the data stored in it during periods when the power to
the chip is turned off. herefore it is used for the memory in porta!le de&ices which
http://en.wikipedia.org/wiki/DDR3_SDRAMhttp://en.wikipedia.org/wiki/DDR4_SDRAMhttp://en.wikipedia.org/wiki/Rambus_DRAMhttp://en.wikipedia.org/wiki/Graphics_adaptorhttp://en.wikipedia.org/wiki/Bit_maskinghttp://en.wikipedia.org/wiki/Dynamic_random_access_memoryhttp://en.wikipedia.org/wiki/Memory_refreshhttp://en.wikipedia.org/wiki/Game_controllerhttp://en.wikipedia.org/wiki/Game_controllerhttp://en.wikipedia.org/wiki/Wiihttp://en.wikipedia.org/wiki/Static_random-access_memoryhttp://en.wikipedia.org/wiki/Transistorshttp://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/Memory_refreshhttp://en.wikipedia.org/wiki/Cache_memoryhttp://en.wikipedia.org/wiki/Content-addressable_memoryhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Cache_memoryhttp://en.wikipedia.org/wiki/Cache_memoryhttp://en.wikipedia.org/wiki/Nonvolatile_memoryhttp://en.wikipedia.org/wiki/DDR3_SDRAMhttp://en.wikipedia.org/wiki/DDR4_SDRAMhttp://en.wikipedia.org/wiki/Rambus_DRAMhttp://en.wikipedia.org/wiki/Graphics_adaptorhttp://en.wikipedia.org/wiki/Bit_maskinghttp://en.wikipedia.org/wiki/Dynamic_random_access_memoryhttp://en.wikipedia.org/wiki/Memory_refreshhttp://en.wikipedia.org/wiki/Game_controllerhttp://en.wikipedia.org/wiki/Game_controllerhttp://en.wikipedia.org/wiki/Wiihttp://en.wikipedia.org/wiki/Static_random-access_memoryhttp://en.wikipedia.org/wiki/Transistorshttp://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Bithttp://en.wikipedia.org/wiki/Memory_refreshhttp://en.wikipedia.org/wiki/Cache_memoryhttp://en.wikipedia.org/wiki/Content-addressable_memoryhttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Cache_memoryhttp://en.wikipedia.org/wiki/Cache_memoryhttp://en.wikipedia.org/wiki/Nonvolatile_memory -
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donBt ha&e dis0s and for remo&a!le memory cardsamong other uses. Ma;or types are1
?8@?9@
ROM (Read-only memory) his is designed to hold permanent data and in
normal operation is only read from not written to. Although many types can
!e written to the writing process is slow and usually all the data in the chip
must !e rewritten at once. *t is usually used to store system softwarewhich
must !e immediately accessi!le to the computer such as the *3S program
which starts the computer and the software (microcode) for porta!le de&ices
and em!edded computers such asmicrocontrollers.
o Mas9 !rogra11e, ROM*n this type the data is programmed into
the chip during manufacture so it is only used for large production
runs. *t cannot !e rewritten with new data.
o PROM (rogramma!le read-only memory) *n this type the data is
written into the chip !efore it is installed in the circuit !ut it can only
!e written once. he data is written !y plugging the chip into a de&ice
called a R3M programmer.
o EPROM(+rasa!le programma!le read-only memory) *n this type the
data in it can !e rewritten !y remo&ing the chip from the circuit !oard
e6posing it to an ultra&iolet light to erase the e6isting data and
plugging it into a R3M programmer. he *C pac0age has a small
transparent window in the top to admit the E< light. *t is often used
for prototypes and small production run de&ices where the program in
it may ha&e to !e changed at the factory.
M +R3M showing transparent window used to erase the chip
http://en.wikipedia.org/wiki/Memory_cardshttp://en.wikipedia.org/wiki/Semiconductor_memory#cite_note-Godse-2http://en.wikipedia.org/wiki/Semiconductor_memory#cite_note-Arora-3http://en.wikipedia.org/wiki/Read-only_memoryhttp://en.wikipedia.org/wiki/System_softwarehttp://en.wikipedia.org/wiki/BIOShttp://en.wikipedia.org/wiki/Microcodehttp://en.wikipedia.org/wiki/Microcontrollerhttp://en.wikipedia.org/wiki/Programmable_read-only_memoryhttp://en.wikipedia.org/wiki/Erasable_programmable_read-only_memoryhttp://en.wikipedia.org/wiki/Ultraviolet_lighthttp://en.wikipedia.org/w/index.php?title=PROM_programmer&action=edit&redlink=1http://en.wikipedia.org/wiki/Memory_cardshttp://en.wikipedia.org/wiki/Semiconductor_memory#cite_note-Godse-2http://en.wikipedia.org/wiki/Semiconductor_memory#cite_note-Arora-3http://en.wikipedia.org/wiki/Read-only_memoryhttp://en.wikipedia.org/wiki/System_softwarehttp://en.wikipedia.org/wiki/BIOShttp://en.wikipedia.org/wiki/Microcodehttp://en.wikipedia.org/wiki/Microcontrollerhttp://en.wikipedia.org/wiki/Programmable_read-only_memoryhttp://en.wikipedia.org/wiki/Erasable_programmable_read-only_memoryhttp://en.wikipedia.org/wiki/Ultraviolet_lighthttp://en.wikipedia.org/w/index.php?title=PROM_programmer&action=edit&redlink=1 -
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o EEPROM(+lectrically erasa!le programma!le read-only memory) *n
this type the data can !e rewritten electrically while the chip is on the
circuit !oard !ut the writing process is slow. his type is used to hold
firmware the low le&el microcode which runs hardware de&ices suchas the *3Sprogram in most computers so that it can !e updated.
NVRAM :Flas 1e1or0;*n this type the writing process is intermediate in
speed !etween ++R3MS and RAM memory5 it can !e written to !ut not fast
enough to ser&e as main memory. *t is often used as a semiconductor &ersion
of a hard dis0 to store files. *t is used in porta!le de&ices such as DAs ES
flash dri&es and remo&a!le memory cards used in digital cameras and
cellphones.
Stati& ran,o18a&&ess 1e1or0(SRAMor stati& RAM) is a type of semiconductor
memory that uses !ista!le latching circuitry to store each !it. he term static
differentiates it from dynamic RAM (DRAM) which must !e periodically refreshed.
SRAM e6hi!its data remanence?,@!ut it is still &olatilein the con&entional sense that
data is e&entually lost when the memory is not powered.
"$* A!!li&ations an, uses
SRAM cells on the dieof a SM984,:9
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"$*$" Cara&teristi&s
SRAM is more e6pensi&e and less dense than DRAM and is therefore not used
for high-capacity low-cost applications such as the main memoryin personal
computers.
"$*$"$" Clo&9 rate an, !o.er
hepowerconsumption of SRAM &aries widely depending on how fre"uently it is
accessed5 it &an !e as power-hungry as dynamic RAM when used at high
fre"uencies and some *Cscan consume many wattsat full !andwidth. 3n the other
hand static RAM used at a somewhat slower pace such as in applications with
moderately cloc0ed microprocessors draws &ery little power and can ha&e a nearly
negligi!le power consumption when sitting idle H in the region of a few micro-watts.
Static RAM e6ists primarily as1
general purpose products
o with asynchronous interface such as the u!i"uitous 8$-pin $I J $ and
98I J $ chips (often !ut not always named something along the lines
of /8/and /8C87/ respecti&ely) as well as similar products up to
,/ M!it per chip
o with synchronous interface usually used for caches and other
applications re"uiring !urst transfers up to ,$ M!it (87/I J K8) per
chip
integrated on chip
o as RAM or cache memory in micro-controllers (usually from around
98 !ytes up to ,8$ 0ilo!ytes)
o as the primary caches in powerful microprocessors such as the 6$/
family and many others (from $ I up to many mega!ytes)
http://en.wikipedia.org/wiki/Computer_memoryhttp://en.wikipedia.org/wiki/Personal_computerhttp://en.wikipedia.org/wiki/Personal_computerhttp://en.wikipedia.org/wiki/Electric_powerhttp://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/Watthttp://en.wikipedia.org/wiki/6264http://en.wikipedia.org/wiki/Kilobytehttp://en.wikipedia.org/wiki/X86http://en.wikipedia.org/wiki/Kilobytehttp://en.wikipedia.org/wiki/Computer_memoryhttp://en.wikipedia.org/wiki/Personal_computerhttp://en.wikipedia.org/wiki/Personal_computerhttp://en.wikipedia.org/wiki/Electric_powerhttp://en.wikipedia.org/wiki/Integrated_circuithttp://en.wikipedia.org/wiki/Watthttp://en.wikipedia.org/wiki/6264http://en.wikipedia.org/wiki/Kilobytehttp://en.wikipedia.org/wiki/X86http://en.wikipedia.org/wiki/Kilobyte -
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o to store the registers and parts of the state-machines used in some
microprocessors (see register file)
o on application specific *Cs or AS*Cs (usually in the order of 0ilo!ytes)
o in 4GAsand CLDs
"$*$"$( E1be,,e, use
Many categories of industrial and scientific su!systems automoti&e
electronics and similar contain static RAM.
Some amount (0ilo!ytes or less) is also em!edded in practically all modern
appliances toys etc. that implement an electronic user interface.
Se&eral mega!ytes may !e used in comple6 products such as digital cameras
cell phones synthesi'ers etc.
SRAM in its dual-ported form is sometimes used for realtime digital signal processing
circuits.?citation needed@
"$*$"$* #n &o1!uters
SRAM is also used in personal computers wor0stations routers and peripheral
e"uipment1 CE register files internal CE cachesand e6ternal!urst modeSRAM
cacheshard dis0!uffers router!uffers etc. LCD screensandprinters also normally
employ static RAM to hold the image displayed (or to !e printed).
"$*$"$+ Hobb0ists
=o!!yists specifically home!uilt processor enthusiasts?8@often prefer SRAM due to
the ease of interfacing. *t is much easier to wor0 with than DRAMas there are no
refresh cycles and the address and data !uses are directly accessi!le rather than
multiple6ed.*n addition to !uses and power connections SRAM usually re"uires only
three controls1 Chip +na!le (C+) >rite +na!le (>+) and 3utput +na!le (3+). *n
synchronous SRAM Cloc0 (CLI) is also included.?citation needed@
http://en.wikipedia.org/wiki/Register_filehttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/CPLDhttp://en.wikipedia.org/wiki/Dual-ported_RAMhttp://en.wikipedia.org/wiki/Digital_signal_processinghttp://en.wikipedia.org/wiki/Electronic_circuithttp://en.wikipedia.org/wiki/Wikipedia:Citation_neededhttp://en.wikipedia.org/wiki/Register_filehttp://en.wikipedia.org/wiki/CPU_cachehttp://en.wikipedia.org/wiki/Burst_mode_(computing)http://en.wikipedia.org/wiki/Hard_diskhttp://en.wikipedia.org/wiki/Router_(computing)http://en.wikipedia.org/wiki/LCD_screenhttp://en.wikipedia.org/wiki/Computer_printerhttp://en.wikipedia.org/wiki/Static_random-access_memory#cite_note-2http://en.wikipedia.org/wiki/DRAMhttp://en.wikipedia.org/wiki/Multiplexedhttp://en.wikipedia.org/wiki/Wikipedia:Citation_neededhttp://en.wikipedia.org/wiki/Register_filehttp://en.wikipedia.org/wiki/Application-specific_integrated_circuithttp://en.wikipedia.org/wiki/FPGAhttp://en.wikipedia.org/wiki/CPLDhttp://en.wikipedia.org/wiki/Dual-ported_RAMhttp://en.wikipedia.org/wiki/Digital_signal_processinghttp://en.wikipedia.org/wiki/Electronic_circuithttp://en.wikipedia.org/wiki/Wikipedia:Citation_neededhttp://en.wikipedia.org/wiki/Register_filehttp://en.wikipedia.org/wiki/CPU_cachehttp://en.wikipedia.org/wiki/Burst_mode_(computing)http://en.wikipedia.org/wiki/Hard_diskhttp://en.wikipedia.org/wiki/Router_(computing)http://en.wikipedia.org/wiki/LCD_screenhttp://en.wikipedia.org/wiki/Computer_printerhttp://en.wikipedia.org/wiki/Static_random-access_memory#cite_note-2http://en.wikipedia.org/wiki/DRAMhttp://en.wikipedia.org/wiki/Multiplexedhttp://en.wikipedia.org/wiki/Wikipedia:Citation_needed -
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"$+ T0!es of SRAM
"$+$" Non8'olatile SRAM
%on-&olatile SRAMs or n&SRAMs ha&e standard SRAM functionality !ut they sa&e
the data when the power supply is lost ensuring preser&ation of critical information.
n&SRAMs are used in a wide range of situationsnetwor0ing aerospace and
medical among many others?9@where the preser&ation of data is critical and where
!atteries are impractical.
"$+$( As0n&ronous SRAM
Asynchronous SRAM are a&aila!le from I! to / M!. he fast access time of
SRAM ma0es asynchronous SRAM appropriate as main memory for small cache-less
em!edded processors used in e&erything from industrial electronics and measurement
systems to hard dis0sand networ0ing e"uipment among many other applications.
hey are used in &arious applications li0e switches and routers *-hones *C-esters
DSLAM Cards to Automoti&e +lectronics.
"$+$* B0 transistor t0!e
ipolar ;unction transistor(used in Land +CL) H &ery fast !ut consumes alot of power
M3S4+(used in CM3S) H low power and &ery common today
"$+$+ B0 fun&tion
AsynchronousH independent of cloc0 fre"uency5 data in and data out are
controlled !y address transition
SynchronousH all timings are initiated !y the cloc0 edge(s). Address data in
and other control signals are associated with the cloc0 signals
"$+$2 B0 feature
( stands for 'ero!us turnaround) H the turnaround is the num!er of
cloc0 cycles it ta0es to change access to the SRAM from write to read and
http://en.wikipedia.org/wiki/NvSRAMhttp://en.wikipedia.org/wiki/Static_random-access_memory#cite_note-3http://en.wikipedia.org/wiki/Main_memoryhttp://en.wikipedia.org/wiki/Industrial_electronicshttp://en.wikipedia.org/wiki/Measurement_systemhttp://en.wikipedia.org/wiki/Measurement_systemhttp://en.wikipedia.org/wiki/Hard_diskhttp://en.wikipedia.org/wiki/Bipolar_junction_transistorhttp://en.wikipedia.org/wiki/Transistor-transistor_logichttp://en.wikipedia.org/wiki/Emitter_coupled_logichttp://en.wikipedia.org/wiki/MOSFEThttp://en.wikipedia.org/wiki/CMOShttp://en.wikipedia.org/wiki/Asynchronoushttp://en.wikipedia.org/wiki/Synchronizationhttp://en.wikipedia.org/w/index.php?title=Zero_bus_turnaround&action=edit&redlink=1http://en.wikipedia.org/w/index.php?title=Bus_turnaround&action=edit&redlink=1http://en.wikipedia.org/wiki/NvSRAMhttp://en.wikipedia.org/wiki/Static_random-access_memory#cite_note-3http://en.wikipedia.org/wiki/Main_memoryhttp://en.wikipedia.org/wiki/Industrial_electronicshttp://en.wikipedia.org/wiki/Measurement_systemhttp://en.wikipedia.org/wiki/Measurement_systemhttp://en.wikipedia.org/wiki/Hard_diskhttp://en.wikipedia.org/wiki/Bipolar_junction_transistorhttp://en.wikipedia.org/wiki/Transistor-transistor_logichttp://en.wikipedia.org/wiki/Emitter_coupled_logichttp://en.wikipedia.org/wiki/MOSFEThttp://en.wikipedia.org/wiki/CMOShttp://en.wikipedia.org/wiki/Asynchronoushttp://en.wikipedia.org/wiki/Synchronizationhttp://en.wikipedia.org/w/index.php?title=Zero_bus_turnaround&action=edit&redlink=1http://en.wikipedia.org/w/index.php?title=Bus_turnaround&action=edit&redlink=1 -
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&ice &ersa. he turnaround for SRAMs or the latency !etween read and
write cycle is 'ero.
syncurst (syncurst SRAM or synchronous-!urst SRAM) H features
synchronous !urst write access to the SRAM to increase write operation to the
SRAM
DDR SRAMH Synchronous single read#write port dou!le data rate *#3
Nuad Data Rate SRAMH Synchronous separate read and write ports
"uadruple data rate *#3
Ca!ter *
http://en.wikipedia.org/w/index.php?title=SyncBurst&action=edit&redlink=1http://en.wikipedia.org/w/index.php?title=DDR_SRAM&action=edit&redlink=1http://en.wikipedia.org/wiki/Quad_Data_Rate_SRAMhttp://en.wikipedia.org/w/index.php?title=SyncBurst&action=edit&redlink=1http://en.wikipedia.org/w/index.php?title=DDR_SRAM&action=edit&redlink=1http://en.wikipedia.org/wiki/Quad_Data_Rate_SRAM -
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DES#-N OF SRAM #N VER#LO-
*$" Design of SRAM
A typical SRAM cell is made up of si6 M3S4+s. +ach!itin an SRAM is stored on
four transistors (M, M8 M9 M) that form two cross-coupled in&erters. his
storage cell has two sta!le states which are used to denote
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4our transistor SRAM pro&ides ad&antages in density at the cost of manufacturing
comple6ity. he resistors must ha&e small dimensions and large &alues.
his is sometimes used to implement more than one (read and#or write) port which
may !e useful in certain types of &ideo memory and register files implemented with
multi-ported SRAM circuitry.
Generally the fewer transistors needed per cell the smaller each cell can !e. Since the
cost of processing a silicon wafer is relati&ely fi6ed using smaller cells and so
pac0ing more !its on one wafer reduces the cost per !it of memory.
A si6-transistor CM3S SRAM cell.
Memory cells that use fewer than four transistors are possi!le H !ut such 9 ?$@?F@or ,
cells are DRAM not SRAM (e&en the so-called,-SRAM).
Access to the cell is ena!led !y the word line (>L in figure) which controls the two
access transistors M7 and M/ which in turn control whether the cell should !e
connected to the !it lines1 L and L. hey are used to transfer data for !oth read and
write operations. Although it is not strictly necessary to ha&e two !it lines !oth the
signal and its in&erse are typically pro&ided in order to impro&e noise margins.
http://en.wikipedia.org/wiki/Video_memoryhttp://en.wikipedia.org/wiki/Register_filehttp://en.wikipedia.org/wiki/Static_random-access_memory#cite_note-8http://en.wikipedia.org/wiki/Static_random-access_memory#cite_note-9http://en.wikipedia.org/wiki/DRAMhttp://en.wikipedia.org/wiki/1T-SRAMhttp://en.wikipedia.org/wiki/Noise_marginhttp://en.wikipedia.org/wiki/Video_memoryhttp://en.wikipedia.org/wiki/Register_filehttp://en.wikipedia.org/wiki/Static_random-access_memory#cite_note-8http://en.wikipedia.org/wiki/Static_random-access_memory#cite_note-9http://en.wikipedia.org/wiki/DRAMhttp://en.wikipedia.org/wiki/1T-SRAMhttp://en.wikipedia.org/wiki/Noise_margin -
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During read accesses the !it lines are acti&ely dri&en high and low !y the in&erters in
the SRAM cell. his impro&es SRAM !andwidth compared to DRAMsH in a
DRAM the !it line is connected to storage capacitors and charge sharingcauses the
!itline to swing upwards or downwards. he symmetric structure of SRAMs also
allows for differential signaling which ma0es small &oltage swings more easily
detecta!le. Another difference with DRAM that contri!utes to ma0ing SRAM faster is
that commercial chips accept all address !its at a time. y comparison commodity
DRAMs ha&e the address multiple6ed in two hal&es i.e. higher !its followed !y
lower !its o&er the same pac0age pins in order to 0eep their si'e and cost down.
he si'e of an SRAM with m address lines and n data lines is 8mwords or 8mJ n !its.
he most common word si'e is $ !its meaning that a single !yte can !e read or
written to each of 8mdifferent words within the SRAM chip. Se&eral common SRAM
chips ha&e ,, address lines (thus a capacity of 8m 8:$ 80 words) and an $-!it
word so they are referred to as 80 J $ SRAM.
*$(SRAM o!eration
An SRAM cell has three different states. *t can !e in1 stand!y (the circuit is idle)
reading (the data has !een re"uested) and writing (updating the contents). he SRAM
to operate in read mode and write mode should ha&e reada!ility and write sta!ility
respecti&ely. he three different states wor0 as follows1
*$($" Stan,b0
*f the word line is not asserted the access transistors M 7and M/disconnect the
cell from the !it lines. he two cross-coupled in&erters formed !y M , H M
will continue to reinforce each other as long as they are connected to the
supply.
*$($( Rea,ing
Assume that the content of the memory is a " stored at N. he read cycle is
started !y precharging !oth the !it lines to a logical " then asserting the word
line >L ena!ling !oth the access transistors. he second step occurs when the
&alues stored in N and N are transferred to the !it lines !y lea&ing L at its
precharged &alue and discharging L through M,and M7to a logical
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e&entually discharging through the transistor M,as it is turned on !ecause the
N is logically set to "). 3n the L side the transistors Mand M/pull the !it
line toward
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CHAPTER +
#NTRODUCT#ON TO VLS# / FP-A DES#-N FLO)
*ntroductionto
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his trend is e6pected to continue with &ery important implications on
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transistors depending on the function. State-of-the-art e6amples of ELS* chips such
as the D+C Alpha or the *%+L entium contain 9 to / million transistors.
+RA DA+ C3ML+*O
(num!er of logic !loc0s per chip)
Single transistor ,F7F less than ,
Enit logic (one gate) ,F/: ,
Multi-function ,F/8 8 -
Comple6 function ,F/ 7 - 8:
Medium Scale *ntegration ,F/K 8: - 8:: (MS*)
Large Scale *ntegration ,FK8 8:: - 8:::
(LS*)
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Figure8*$(7 +&olution of integration density and minimum feature si'e as seen in the
early ,F$:s.
herefore the current trend of integration will also continue in the foreseea!le
future. Ad&ances in de&ice manufacturing technology and especially the steady
reduction of minimum feature si'e (minimum length of a transistor or an interconnect
reali'a!le on chip) support this trend. 4igure ,.8 shows the history and forecast of
chip comple6ity - and minimum feature si'e - o&er time as seen in the early ,F$:s. At
that time a minimum feature si'e of :.9 microns was e6pected around the year 8:::.
he actual de&elopment of the technology howe&er has far e6ceeded these
e6pectations. A minimum si'e of :.87 microns was readily achie&a!le !y the year
,FF7. As a direct result of this the integration density has also e6ceeded pre&ious
e6pectations - the first / M!it DRAM and the *%+L entium microprocessor chip
containing more than 9 million transistors were already a&aila!le !y ,FF pushing
the en&elope of integration density.
>hen comparing the integration density of integrated circuits a clear distinction must
!e made !etween the memory chips and logic chips. 4igure ,.9 shows the le&el of
integration o&er time for memory and logic chips starting in ,FK:. *t can !e o!ser&edthat in terms of transistor count logic chips contain significantly fewer transistors in
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any gi&en year mainly due to large consumption of chip area for comple6
interconnects. Memory circuits are highly regular and thus more cells can !e
integrated with much less area for interconnects.
Figure8*$*7 Le&el of integration o&er time for memory chips and logic chips.
Generally spea0ing logic chips such as microprocessor chips and digital
signal processing (DS) chips contain not only large arrays of memory (SRAM) cells
!ut also many different functional units. As a result their design comple6ity is
considered much higher than that of memory chips although ad&anced memory chips
contain some sophisticated logic functions. he design comple6ity of logic chips
increases almost e6ponentially with the num!er of transistors to !e integrated. his is
translated into the increase in the design cycle time which is the time period from the
start of the chip de&elopment until the mas0-tape deli&ery time. =owe&er in order to
ma0e the !est use of the current technology the chip de&elopment time has to !e short
enough to allow the maturing of chip manufacturing and timely deli&ery to customers.
As a result the le&el of actual logic integration tends to fall short of the integration
le&el achie&a!le with the current processing technology. Sophisticated computer-aided
design (CAD) tools and methodologies are de&eloped and applied in order to manage
the rapidly increasing design comple6ity.
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+$( VLS# Design Flo.
he design process at &arious le&els is usually e&olutionary in nature. *t starts
with a gi&en set of re"uirements. *nitial design is de&eloped and tested against the
re"uirements. >hen re"uirements are not met the design has to !e impro&ed. *f such
impro&ement is either not possi!le or too costly then the re&ision of re"uirements and
its impact analysis must !e considered. he O-chart (first introduced !y D. Ga;s0i)
shown in 4ig. ,. illustrates a design flow for most logic chips using design acti&ities
on three different a6es (domains) which resem!le the letter O.
Figure8*$+7 ypical
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he design flow starts from the algorithm that descri!es the !eha&ior of the target
chip. he corresponding architecture of the processor is first defined. *t is mapped
onto the chip surface !y floorplanning. he ne6t design e&olution in the !eha&ioral
domain defines finite state machines (4SMs) which are structurally implemented with
functional modules such as registers and arithmetic logic units (ALEs).
hese modules are then geometrically placed onto the chip surface using CAD
tools for automatic module placement followed !y routing with a goal of minimi'ing
the interconnects area and signal delays. he third e&olution starts with a !eha&ioral
module description. *ndi&idual modules are then implemented with leaf cells. At this
stage the chip is descri!ed in terms of logic gates (leaf cells) which can !e placed and
interconnected !y using a cell placement Q routing program. he last e&olution
in&ol&es a detailed oolean description of leaf cells followed !y a transistor le&el
implementation of leaf cells and mas0 generation. *n standard-cell !ased design leaf
cells are already pre-designed and stored in a li!rary for logic design use.
*$" CONVOLUT#ONAL ENCODER
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Figure8*$27 A more simplified &iew of
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to fit the architecture into the allowa!le chip area some functions may ha&e to !e
remo&ed and the design process must !e repeated. Such changes may re"uire
significant modification of the original re"uirements. hus it is &ery important to feed
forward low-le&el information to higher le&els (!ottom up) as early as possi!le.
*n the following we will e6amine design methodologies and structured
approaches which ha&e !een de&eloped o&er the years to deal with !oth comple6
hardware and software pro;ects. Regardless of the actual si'e of the pro;ect the !asic
principles of structured design will impro&e the prospects of success. Some of the
classical techni"ues for reducing the comple6ity of *C design are1 =ierarchy
regularity modularity and locality.
*$* Design Hierar&0
he use of hierarchy or di&ide and con"uertechni"ue in&ol&es di&iding a
module into su!- modules and then repeating this operation on the su!-modules until
the comple6ity of the smaller parts !ecomes managea!le. his approach is &ery
similar to the software case where large programs are split into smaller and smaller
sections until simple su!routines with well-defined functions and interfaces can !e
written. *n Section ,.8 we ha&e seen that the design of a
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layout) domain resulting in a simple floorplan. his physical &iew descri!es the
e6ternal geometry of the adder the locations of input and output pins and how pin
locations allow some signals (in this case the carry signals) to !e transferred from one
su!-!loc0 to the other without e6ternal routing. At lower le&els of the physical
hierarchy the internal mas0
Figure8*$37 Structural decomposition of a four-!it adder circuit showing the
hierarchy down to gate le&el.
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Figure8*$47 Regular design of a 8-, ME a D44 and an adder using in&erters and
tri-state !uffers.
*$+ VLS# Design St0les
Se&eral design styles can !e considered for chip implementation of specified
algorithms or logic functions. +ach design style has its own merits and shortcomings
and thus a proper choice has to !e made !y designers in order to pro&ide the
functionality at low cost.
*$+$" Fiel, Progra11able -ate Arra0 :FP-A;
4ully fa!ricated 4GA chips containing thousands of logic gates or e&en more
with programma!le interconnects are a&aila!le to users for their custom hardware
programming to reali'e desired functionality. his design style pro&ides a means for
fast prototyping and also for cost-effecti&e chip design especially for low-&olume
applications. A typical field programma!le gate array (4GA) chip consists of *#3
!uffers an array of configura!le logic !loc0s (CLs) and programma!le interconnect
structures. he programming of the interconnects is implemented !y programming ofRAM cells whose output terminals are connected to the gates of M3S pass transistors.
A general architecture of 4GA from *L*% is shown in 4ig. 9.$. A more detailed
&iew showing the locations of switch matrices used for interconnect routing is gi&en
in 4ig. 9.F.
A simple CL (model C8::: from *L*%) is shown in 4ig. 9.,:. *t
consists of four signal input terminals (A C D) a cloc0 signal terminal user-
programma!le multiple6ers an SR-latch and a loo0-up ta!le (LE). he LE is a
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digital memory that stores the truth ta!le of the oolean function. hus it can
generate any function of up to four &aria!les or any two functions of three &aria!les.
he control terminals of multiple6ers are not shown e6plicitly in 4ig. 9.,:.
he CL is configured such that many different logic functions can !e
reali'ed !y programming its array. More sophisticated CLs ha&e also !een
introduced to map comple6 functions. he typical design flow of an 4GA chip starts
with the !eha&ioral description of its functionality using a hardware description
language such as
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Figure8*$"
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transistors of the array (4ig. 9.,,). Since the patterning of metallic interconnects is
done at the end of the chip fa!rication the turn-around time can !e still short a few
days to a few wee0s. 4igure 9.,8 shows a corner of a gate array chip which contains
!onding pads on its left and !ottom edges diodes for *#3 protection nM3S
transistors and pM3S transistors for chip output dri&er circuits in the neigh!oring
areas of !onding pads arrays of nM3S transistors and pM3S transistors underpass
wire segments and power and ground !uses along with contact windows.
Figure8*$""7 asic processing steps re"uired for gate array implementation.
Figure8*$"(7 A corner of a typical gate array chip.
4igure 9.,9 shows a magnified portion of the internal array with metal mas0
design (metal lines highlighted in dar0) to reali'e a comple6 logic function. ypical
gate array platforms allow dedicated areas called channels for intercell routing asshown in 4igs. 9.,8 and 9.,9 !etween rows or columns of M3S transistors. he
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a&aila!ility of these routing channels simplifies the interconnections e&en using one
metal layer only. he interconnection patterns to reali'e !asic logic gates can !e
stored in a li!rary which can then !e used to customi'e rows of uncommitted
transistors according to the netlist. >hile most gate array platforms only contain rows
of uncommitted transistors separated !y routing channels some other platforms also
offer dedicated memory (RAM) arrays to allow a higher density where memory
functions are re"uired. 4igure 9., shows the layout &iews of a con&entional gate
array and a gate array platform with two dedicated memory !an0s.
>ith the use of multiple interconnect layers the routing can !e achie&ed o&er
the acti&e cell areas5 thus the routing channels can !e remo&ed as in Sea-of-Gates
(S3G) chips. =ere the entire chip surface is co&ered with uncommitted nM3S and
pM3S transistors. As in the gate array case neigh!oring transistors can !e customi'ed
using a metal mas0 to form !asic logic gates. 4or intercell routing howe&er some of
the uncommitted transistors must !e sacrificed. his approach results in more
fle6i!ility for interconnections and usually in a higher density. he !asic platform of
a S3G chip is shown in 4ig. ,.,F. 4igure ,.8: offers a !rief comparison !etween the
channeled (GA) &s. the channelless (S3G) approaches.
Figure8*$"*7 Metal mas0 design to reali'e a comple6 logic function on a channeled
GA platform.
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Figure8*$"+7 Layout &iews of a con&entional GA chip and a gate array with two
memory !an0s.
Figure8*$"27 he platform of a Sea-of-Gates (S3G) chip.
*n general the GA chip utili'ation factor as measured !y the used chip area di&ided
!y the total chip area is higher than that of the 4GA and so is the chip speed since
more customi'ed design can !e achie&ed with metal mas0 designs. he current gate
array chips can implement as many as hundreds of thousands of logic gates.
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Figure8*$"37 Comparison !etween the channeled (GA) &s. the channelless (S3G)
approaches.
*$+$* Stan,ar,8Cells Base, Design
he standard-cells !ased design is one of the most pre&alent full custom design
styles which re"uire de&elopment of a full custom mas0 set. he standard cell is also
called the polycell. *n this design style all of the commonly used logic cells are
de&eloped characteri'ed and stored in a standard cell li!rary. A typical li!rary may
contain a few hundred cells including in&erters %A%D gates %3R gates comple6
A3* 3A* gates D-latches and flip-flops. +ach gate type can ha&e multiple
implementations to pro&ide ade"uate dri&ing capa!ility for different fanouts. 4or
instance the in&erter gate can ha&e standard si'e transistors dou!le si'e transistors
and "uadruple si'e transistors so that the chip designer can choose the proper si'e to
achie&e high circuit speed and layout density. he characteri'ation of each cell is done
for se&eral different categories. *t consists of
delay time &s. load capacitance
circuit simulation model
timing simulation model
fault simulation model
cell data for place-and-route
mas0 data
o ena!le automated placement of the cells and routing of inter-cell connections
each cell layout is designed with a fi6ed height so that a num!er of cells can !e
a!utted side-!y-side to form rows. he power and ground rails typically run parallel
to the upper and lower !oundaries of the cell thus neigh!oring cells share a common
power and ground !us. he input and output pins are located on the upper and lower
!oundaries of the cell. 4igure 9.,K shows the layout of a typical standard cell. %otice
that the nM3S transistors are located closer to the ground rail while the pM3S
transistors are placed closer to the power rail.
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Figure8"$"47 A standard cell layout e6ample.
4igure 9.,$ shows a floorplan for standard-cell !ased design. *nside the *#3
frame which is reser&ed for *#3 cells the chip area contains rows or columns of
standard cells. etween cell rows are channels for dedicated inter-cell routing. As in
the case of Sea-of-Gates with o&er-the- cell routing the channel areas can !e reduced
or e&en remo&ed pro&ided that the cell rows offer sufficient routing space. he
physical design and layout of logic cells ensure that when cells are placed into rows
their heights are matched and neigh!oring cells can !e a!utted side-!y-side which
pro&ides natural connections for power and ground lines in each row. he signal
delay noise margins and power consumption of each cell should !e also optimi'ed
with proper si'ing of transistors using circuit simulation.
Figure8*$"57 A simplified floorplan of standard-cells-!ased design.
*f a num!er of cells must share the same input and#or output signals a
common signal !us structure can also !e incorporated into the standard-cell-!ased
chip layout. 4igure ,.89 shows the simplified sym!olic &iew of a case where a signal
!us has !een inserted !etween the rows of standard cells. %ote that in this case the
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chip consists of two !loc0s and power#ground routing must !e pro&ided from !oth
sides of the layout area. Standard-cell !ased designs may consist of se&eral such
macro-!loc0s each corresponding to a specific unit of the system architecture such as
ALE control logic etc.
Figure8*$"=7 Simplified floorplan consisting of two separate !loc0s and a common
signal !us.
After chip logic design is done using standard cells in the li!rary the most
challenging tas0 is to place indi&idual cells into rows and interconnect them in a way
that meets stringent design goals in circuit speed chip area and power consumption.
Many ad&anced CAD tools for place-and-route ha&e !een de&eloped and used to
achie&e such goals. Also from the chip layout circuit models which include
interconnect parasitics can !e e6tracted and used for timing simulation and analysis to
identify timing critical paths. 4or timing critical paths proper gate si'ing is often
practiced to meet the timing re"uirements. *n many
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he a&aila!ility of dedicated memory !loc0s also reduces the area since the
reali'ation of memory elements using standard cells would occupy a larger area.
Figure8*$(
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*n digital CM3S
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+$" FP-A DES#-N FLO)
4GA contains a two dimensional arrays of logic !loc0s and interconnections
!etween logic !loc0s. oth the logic !loc0s and interconnects are programma!le.Logic !loc0s are programmed to implement a desired function and the interconnects
are programmed using the switch !o6es to connect the logic !loc0s. o !e more clear
if we want to implement a comple6 design (CE for instance) then the design is
di&ided into small su! functions and each su! function is implemented using one
logic !loc0. %ow to get our desired design (CE) all the su! functions implemented
in logic !loc0s must !e connected and this is done !y programming the interconnects.
*nternal structure of an 4GA is depicted in the following figure.
4GAs alternati&e to the custom *Cs can !e used to implement an entire System 3n one
Chip (S3C). he main ad&antage of 4GA is a!ility to reprogram. Eser can reprogram an
4GA to implement a design and this is done after the 4GA is manufactured. his !rings thename 4ield rogramma!le.
Custom *Cs are e6pensi&e and ta0es long time to design so they are useful when produced in
!ul0 amounts. ut 4GAs are easy to implement with in a short time with the help of
Computer Aided Designing (CAD) tools (!ecause there is no physical layout process no
mas0 ma0ing and no *C manufacturing).
Some disad&antages of 4GAs are they are slow compared to custom *Cs as they canTt
handle &ary comple6 designs and also they draw more power.
ilin6 logic !loc0 consists of one Loo0 Ep a!le (LE) and one 4lip4lop. An LE is used to
implement num!er of different functionality. he input lines to the logic !loc0 go into the
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LE and ena!le it. he output of the LE gi&es the result of the logic function that it
implements and the output of logic !loc0 is registered or unregistered out put from the LE.
SRAM is used to implement a LE.A 0-input logic function is implemented using 8U0 V ,
si'e SRAM. %um!er of different possi!le functions for 0 input LE is 8U8U0. Ad&antage of
such an architecture is that it supports implementation of so many logic functions howe&er
the disad&antage is unusually large num!er of memory cells re"uired to implement such a
logic !loc0 in case num!er of inputs is large.
4igure !elow shows a -input LE !ased implementation of logic !loc0.
LE !ased design pro&ides for !etter logic !loc0 utili'ation. A 0-input LE !ased logic !loc0
can !e implemented in num!er of different ways with trade off !etween performance and
logic density.
An n-LE can !e shown as a direct implementation of a function truth-ta!le. +ach of the
latch holds the &alue of the function corresponding to one input com!ination. 4or +6ample1 8-
LE can !e used to implement ,/ types of functions li0e A%D 3R AWnot .... etc.
A A%D 3R %A%D ...... ....
: : : : ,
: , : , ,
, : : , ,
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, , , , :
#nter&onne&ts
A wire segment can !e descri!ed as two end points of an interconnect with no
programma!le switch !etween them. A se"uence of one or more wire segments in an
4GA can !e termed as a trac0.
ypically an 4GA has logic !loc0s interconnects and switch !loc0s (*nput#3utput
!loc0s). Switch !loc0s lie in the periphery of logic !loc0s and interconnect. >ire
segments are connected to logic !loc0s through switch !loc0s. Depending on the
re"uired design one logic !loc0 is connected to another and so on.
FP-A DES#-N FLO)
*n this part of tutorial we are going to ha&e a short intro on 4GA design flow. A
simplified &ersion of design flow is gi&en in the flowing diagram.
+$"$" Design Entr0
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here are different techni"ues for design entry. Schematic !ased =ardware
Description Language and com!ination of !oth etc. . Selection of a method depends
on the design and designer. *f the designer wants to deal more with =ardware then
Schematic entry is the !etter choice. >hen the design is comple6 or the designer
thin0s the design in an algorithmic way then =DL is the !etter choice. Language
!ased entry is faster !ut lag in performance and density.
=DLs represent a le&el of a!straction that can isolate the designers from the details of
the hardware implementation. Schematic !ased entry gi&es designers much more
&isi!ility into the hardware. *t is the !etter choice for those who are hardware
oriented. Another method !ut rarely used is state-machines. *t is the !etter choice for
the designers who thin0 the design as a series of states. ut the tools for state machine
entry are limited. *n this documentation we are going to deal with the =DL !ased
design entry.
+$"$( S0ntesis
he process which translates
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+$"$*$ #1!le1entation
his process consists a se"uence of three steps
,. ranslate
8. Map
9. lace and Route
+$"$*$" Translate
his process com!ines all the input netlists and constraints to a logic design file. his
information is sa&ed as a %GD (%ati&e Generic Data!ase) file. his can !e done using
%GD uild program. =ere defining constraints is nothing !ut assigning the ports in
the design to the physical elements (e6. pins switches !uttons etc) of the targeted
de&ice and specifying time re"uirements of the design. his information is stored in a
file named EC4 (Eser Constraints 4ile). ools used to create or modify the EC4 are
AC+ Constraint +ditor etc.
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+$"$*$( Ma!
his process di&ides the whole circuit with logical elements into su! !loc0s such that
they can !e fit into the 4GA logic !loc0s. hat means map process fits the logic
defined !y the %GD file into the targeted 4GA elements (Com!inational Logic
loc0s (CL) *nput 3utput loc0s (*3)) and generates an %CD (%ati&e Circuit
Description) file which physically represents the design mapped to the components of
4GA. MA program is used for this purpose.
+$"$*$* Pla&e an, Route
AR program is used for this process. he place and route process places the su!
!loc0s from the map process into logic !loc0s according to the constraints and
connects the logic !loc0s. +6. if a su! !loc0 is placed in a logic !loc0 which is &ery
near to *3 pin then it may sa&e the time !ut it may effect some other constraint. So
trade off !etween all the constraints is ta0en account !y the place and route process.
he AR tool ta0es the mapped %CD file as input and produces a completely routed
%CD file as output. 3utput %CD file consists the routing information.
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Pla&e an, RouteAR program is used for this process. he place and route process
places the su! !loc0s from the map process into logic !loc0s according to the
constraints and connects the logic !loc0s. +6. if a su! !loc0 is placed in a logic !loc0
which is &ery near to *3 pin then it may sa&e the time !ut it may effect some other
constraint. So trade off !etween all the constraints is ta0en account !y the place and
route process. he AR tool ta0es the mapped %CD file as input and produces a
completely routed %CD file as output. 3utput %CD file consists the routing
information.
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+$"$+ De'i&e Progra11ing
%ow the design must !e loaded on the 4GA. ut the design must !e con&erted to a
format so that the 4GA can accept it. *G+% program deals with the con&ersion.
he routed %CD file is then gi&en to the *G+% program to generate a !it stream
(a .* file) which can !e used to configure the target 4GA de&ice. his can !e done
using a ca!le. Selection of ca!le depends on the design.
+$"$2 Design Verifi&ation
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+$"$4 Fun&tional si1ulation (ost ranslate Simulation) 4unctional simulation gi&es
information a!out the logic operation of the circuit. Designer can &erify the
functionality of the design using this process after the ranslate process. *f the
functionality is not as e6pected then the designer has to made changes in the code and
again follow the design flow steps.
+$"$5$ Stati& Ti1ing Anal0sishis can !e done after MA or AR processes ost
MA timing report lists signal path delays of the design deri&ed from the design logic.
ost lace and Route timing report incorporates timing delay information to pro&ide a
comprehensi&e timing summary of the design.
CHAPTER 2
#ntro,u&tion to Verilog
*n the semiconductorand electronic designindustry Verilogis a hardwaredescription language(=DL) used to modelelectronic systems.
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confused with
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concurrent and se"uential statement !loc0s and instances of other modules (su!-
hierarchies). Se"uential statements are placed inside a !egin#end !loc0 and e6ecuted
in se"uential order within the !loc0. ut the !loc0s themsel&es are e6ecuted
concurrently "ualifying
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"$3$( Verilog8=2
>ith the increasing success of
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"$3$+ Verilog (
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he most &alua!le !enefit of System
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en,
en,1o,ule
+681 A simple e6ample of two flip-flopsfollows1
1o,uletople&el(cloc0reset)5
in!utcloc05
in!utreset5
regflop,5
regflop85
al.a0s^ (!ose,gereset or!ose,gecloc0)
if(reset)
begin
flop, Z :5
flop8 Z ,5
en,
else
begin
flop, Z flop85
flop8 Z flop,5
en,
en,1o,ule
he Z operator in hen assignment is used for the purposes of logic the target &aria!le is updated
immediately. *n the a!o&e e6ample had the statements used the !loc0ing operator
instead of Z flop, and flop8 would not ha&e !een swapped. *nstead as in
http://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Flip-flop_(electronics)http://en.wikipedia.org/wiki/Flip-flop_(electronics) -
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traditional programming the compiler would understand to simply set flop, e"ual to
flop8 (and su!se"uently ignore the redundant logic to set flop8 e"ual to flop,.)
+691 An e6ample countercircuit follows1
1o,uleDi&8:6 (rst cl0 cet cep count tc)5
## *L+ BDi&ide-!y-8: Counter with ena!lesB
## ena!le C+ is a cloc0 ena!le only
## ena!le C+ is a cloc0 ena!le and
## ena!les the C output
## a counter using the
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al.a0s^ (!ose,gecl0 or!ose,gerst)
if(rst) ## his causes reset of the cntr
count Z [si'e[,B!:\\5
else
if(cet QQ cep) ## +na!les !oth true
begin
if(count length-,)
count Z [si'e[,B!:\\5
else
count Z count W ,B!,5
en,
## the &alue of tc is continuously assigned
## the &alue of the e6pression
assigntc (cet QQ (count length-,))5
en,1o,ule
E>+7 An e>a1!le of ,ela0s7
...
rega ! c d5
.iree5
...
al.a0s^(! ore)
begin
a ! Q e5
! a !5
b7 c !5
d b/ c U e5
en,
he always clause a!o&e illustrates the other type of method of use i.e. the
always clause e6ecutes any time any of the entities in the list change i.e. the ! or e
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change. >hen one of these changes immediately a is assigned a new &alue and due
to the !loc0ing assignment ! is assigned a new &alue afterward (ta0ing into account
the new &alue of a.) After a delay of 7 time units c is assigned the &alue of ! and the
&alue of c U e is tuc0ed away in an in&isi!le store. hen after / more time units d is
assigned the &alue that was tuc0ed away.
Signals that are dri&en from within a process (an initial or always !loc0) must !e of
type reg. Signals that are dri&en from outside a process must !e of type wire. he
0eyword reg does not necessarily imply a hardware register.
3$* Constants
he definition of constants in idth in !its]BZ!ase letter]Znum!er]
+6amples1
,8Bh,89 - =e6adecimal ,89 (using ,8 !its)
8:Bd - Decimal (using 8: !its - : e6tension is automatic)
B!,:,: - inary ,:,: (using !its)
/BoKK - 3ctal KK (using / !its)
3$+ S0ntesi?able Constru&ts
here are se&eral statements in
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assignout sel P a 1 !5
## the second e6ample uses a procedure
## to accomplish the same thing.
regout5
al.a0s^(a or! orsel)
begin
&ase(sel)
,B!:1 out !5
,B!,1 out a5
en,&ase
en,
## 4inally - you can use if#else in a
## procedural structure.
regout5
al.a0s^(a or! orsel)
if(sel)
out a5
else
out !5
he ne6t interesting structure is atransparent latchit will pass the input to the
output when the gate signal is set for pass-through and captures the input and stores
it upon transition of the gate signal to hold. he output will remain sta!le regardless
of the input signal while the gate is set to hold. *n the e6ample !elow the pass-
through le&el of the gate would !e when the &alue of the if clause is true i.e. gate
,. his is read if gate is true the din is fed to latchout continuously. 3nce the ifclause is false the last &alue at latchout will remain and is independent of the &alue
of din.
+/1 ## ransparent latch e6ample
regout5
al.a0s^(gate ordin)
if(gate)
out din5 ## ass through state
http://en.wikipedia.org/wiki/Transparent_latchhttp://en.wikipedia.org/wiki/Transparent_latchhttp://en.wikipedia.org/wiki/Transparent_latch -
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## %ote that the else isnBt re"uired here. he &aria!le
## out will follow the &alue of din while gate is high.
## >hen gate goes low out will remain constant.
he flip-flopis the ne6t significant template5 in
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else
" Z d5
%ote1 *f this model is used to model a Set#Reset flip flop then simulation errors
can result. Consider the following test se"uence of e&ents. ,) reset goes high 8) cl0
goes high 9) set goes high ) cl0 goes high again 7) reset goes low followed !y /) set
going low. Assume no setup and hold &iolations.
*n this e6ample the always ^ statement would first e6ecute when the rising
edge of reset occurs which would place " to a &alue of :. he ne6t time the always
!loc0 e6ecutes would !e the rising edge of cl0 which again would 0eep " at a &alue of
:. he always !loc0 then e6ecutes when set goes high which !ecause reset is highforces " to remain at :. his condition may or may not !e correct depending on the
actual flip flop. =owe&er this is not the main pro!lem with this model. %otice that
when reset goes low that set is still high. *n a real flip flop this will cause the output
to go to a ,. =owe&er in this model it will not occur !ecause the always !loc0 is
triggered !y rising edges of set and reset - not le&els. A different approach may !e
necessary for set#reset flip flops.
%ote that there are no initial !loc0s mentioned in this description. here is a
split !etween 4GA and AS*C synthesis tools on this structure. 4GA tools allow
initial !loc0s where reg &alues are esta!lished instead of using a reset signal. AS*C
synthesis tools donBt support such a statement. he reason is that an 4GABs initial
state is something that is downloaded into the memory ta!les of the 4GA. An AS*C
is an actual hardware implementation.
3$2 #nitial Vs Al.a0s7
here are two separate ways of declaring a
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!loc0. *n fact it is !etter to thin0 of the initial-!loc0 as a special-case of the al.a0s-
!loc0 one which terminates after it completes for the first time.
##+6amples1
initial
begin
a ,5 ## Assign a &alue to reg a at time :
b,5 ## >ait , time unit
! a5 ## Assign the &alue of reg a to reg !
en,
al.a0s^(a or!) ## Any time a or ! C=A%G+ run the process
begin
if(a)
c !5
else
d !5
en,## Done with this !loc0 now return to the top (i.e. the ^ e&ent-control)
al.a0s^(!ose,gea)## Run whene&er reg a has a low to high change
a Z !5
hese are the classic uses for these two 0eywords !ut there are two significant
additional uses. he most common of these is an al.a0s0eyword without
the :$$$;sensiti&ity list. *t is possi!le to use always as shown !elow1
al.a0sbegin## Always !egins e6ecuting at time : and %+ait for , time unit
cl0 ,5 ## Set cl0 to ,
b,5 ## >ait , time unit
en,## Ieeps e6ecuting - so continue !ac0 at the top of the !egin
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he al.a0s0eyword acts similar to the C construct .ile:"; $$in the sense
that it will e6ecute fore&er.
he other interesting e6ception is the use of the initial0eyword with the
addition of the fore'er0eyword.
3$3 Ra&e Con,ition
he order of e6ecution isnBt always guaranteed within
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itwise
Logical
Reduction
Arithmetic
Relational
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Shift
3$5 S0ste1 Tas9s7
System tas0s are a&aila!le to handle simple *#3 and &arious design measurement
functions. All system tas0s are prefi6ed with to distinguish them from user tas0s and
functions. his section presents a short list of the most often used tas0s. *t is !y no
means a comprehensi&e list.
_display - rint to screen a line followed !y an automatic newline.
_write - >rite to screen a line without the newline.
_swrite - rint to &aria!le a line without the newline.
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_sscanf - Read from &aria!le a format-specified string. (Vrite to file a line followed !y an automatic newline.
_fwrite - >rite to file a line without the newline.
_fscanf - Read from file a format-specified string. (V
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#L#N #SE "($" Design Suite Tutorial
, . Clic0 on ilin> #SE Design Suite "($" *con on des0top
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8 . #SE Pro%e&t Na'igator :M2* D; 8 #SE Design Suite #nfo &enter window will
!e opened.
9. ress 30 .hen go to Filemenu . Select the Ne. !ro%e&t.
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,. %ew op up window named Ne. Pro%e&t .i?ar,appeared.
8. +nter the ro;ect name in Na1e field.
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9. Select the location where you want to store the pro;ect !y selecting the
Lo&ation field
. >or0ing Directory is automatically select same location .
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7. Select the HDL in To! Le'el Sour&e T0!e present at !ottom of window.
/. hen press the NET $
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K. hen it goes to ro;ect Settings .
$. *n this pro;ect settings you can select the product details used to dump our
program.
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F. After selecting the &alues clic0 %+.
,:. *t goes to ro;ect Summary ta! .hen Clic0 4inish.
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,,. After that it Can !ac0 to #SE Pro%e&t Na'igator :M2* D; window .
,8. Go to Pro%e&tta! open the Ne. Sour&e$
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,9. %ew Source >i'ard pup up will !e opend.
,. =ere we can seselect &erilog Module.
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,7. hen enter the file name for new source.
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8:.
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Verifcation usingtest bench
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Ca!ter 3
Results an, ,is&ussions
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V##. CONCLUS#ON
*n this paper we ha&e presented the design and implementation of the SRAM . his
design has !een simulated in M3D+LS*M altera /./d and synthesi'ed using *L*%-
*S+ ,.i targeted to Spartan 9+ 4GA . he gi&en input se"uence has !een Stored in
SRAM and return as output .
REFERENCES
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