sram design for vfat3
DESCRIPTION
SRAM design for VFAT3. CERN – Round Table Meeting - July 4 th Jérôme Masson. Outline. Work done since May 22th (CERN workshop) Modifications to bring What I need to do before end of July. Reminder : Block diagram. DataIN SRAM1 128. DataIN SRAM2 128. Encoder. Decoder. Encoder. - PowerPoint PPT PresentationTRANSCRIPT
SRAM design for VFAT3
CERN – Round Table Meeting - July 4th
Jérôme Masson
Round Table Meeting 2
Outline
07/04/2013
• Work done since May 22th (CERN workshop)• Modifications to bring• What I need to do before end of July
Round Table Meeting 3
Reminder : Block diagram
07/04/2013
SRAM 1 SRAM 2
Control Logic
Encoder
Encoder
Decoder
Decoder
DataIN SRAM1
128
DataIN SRAM2
128
Data Formatter
Wa1 W1 R1Ra1 Wa2 W2 Ra2 R2
Wa: Write address
W: Write enabled
Ra: Read address
R: Read enabled
DataOUT
data Valid
140
12
tag
156 e Port
Round Table Meeting 4
SRAM1 : a placed/routed config
07/04/2013
Round Table Meeting 5
SRAM1 : Write
07/04/2013
Time before a data is written in memory : #2.5 clock period reduce to 1.5 clock period
CONTROL LOGIC
Round Table Meeting 6
SRAM1 : Read
07/04/2013
Time before a data is read in memory : #2.5 clock period reduce to 1.5 clock period
Round Table Meeting 7
Modifications
• Modifications done :– Take off the flops to win 1 clock period (functionality of the
block not changed)– Synthesis : a path is unconstrained (timing issue)
• Size modifications for SRAM1 (to do):
07/04/2013
Current Future
Size of data 152 bits 152 bits
Size of basic module 128x64 256x32
Blocks 10 blocks of 3 modules 5 blocks of 5 modules
Width of blocks 64x3 = 192 bits 32x5 = 160 bits
Memory bits not used 40x1280 = 51200 8x1280 = 10240
Mieczyslaw idea
Round Table Meeting 8
SRAM1 : write (behaviour)
07/04/2013
Better than previous design : faster and smaller
Round Table Meeting 907/04/2013
SRAM1 : read (behaviour)
Better than previous design : faster and smaller
Round Table Meeting 10
To DO
• #3 weeks to finish the blocks– Make transition with Mieczyslaw– Ensure the timing (current task)– Physical design
• Assets:– Design flow: already gone through– Work environment (scripts, .lib, STA) : set
07/04/2013
Round Table Meeting 11
Thanks for paying attention
07/04/2013
Round Table Meeting 12
Back up
07/04/2013
Round Table Meeting 13
SRAM1 : Control (1/2)
07/04/2013
Décodeurd’adresses
Mux A
dataIN128 channels
read_address<10:0>
write_address<10:0>
Module
Encoder
7
address A
Module
Module
7address address J
7 7
Block A Block J
7read_address
write_address
Mux Mux J
write_en
read_en
Round Table Meeting 14
SRAM1 : Control (2/2)
07/04/2013
Hamming Dec3
Hamming Dec0
Hamming Dec2
Hamming Dec1
…..
Output block A
Output block B
Output block C
Output block J
38
38
38
38
152
152
152
152
32
32
32
32
dataOUT140Control
Logic
12 bits time stamps are added to the data in the Control Logic
Round Table Meeting 15
SRAM2 : Write
07/04/2013
NEED TO BE CHANGED
as for SRAM1
Round Table Meeting 16
SRAM2 : Read
07/04/2013
NEED TO BE CHANGED
as for SRAM1