design options for digital systems
DESCRIPTION
Design options for digital systemsTRANSCRIPT
Hanbat
National
UniversityHanbat
National
University
Design Options for Digital Systems
Design Options for Digital Systems
Gookyi Dennis A. N.
SoC Design Lab.
August.05.2014
Contents ASIC Design Options FPGA PLDs
2
Overview The various design options for digital systems
3
Design options
ASIC
Full Cus-tom
Cell-based
Gate-ar-ray-
based
Field Programmable
PLDs
ROM PAL PLA
CPLDs FPGAs
Hierarchical System Design Digital system designers widely use a hierarchical
structure to design digital systems The essence is to partition the system into smaller
independent sub-structures which combine to perform the same functionality as the original system
The design hierarchy can be classified into four level:System levelRegister transfer levelLogic gate levelCircuit level
4
Hierarchical System Design Differences in the various hierarchies
5
Design levels
Operand size Processing time range(s)
Logic devices
System Bytes/byte blocks
Microprocessors/microcomputers, memory devices, timers
RTL Bits/bytes Decoders, en-coders, multiplex-ers, registers, counters
Logic gate
Bits Basic logic gates, flip-flops, latches
circuit Bits MOSFETs, BJTs
SB
RB
Q
QB
SG
D
G
S
D
regis
ter
regis
ter
Combinational circuit
mux
CLK A CLK B
X F
𝑉 𝐷𝐷
RAM
ROM
ParallelI/O port
DMAcontroller
Clock
microP
SYSTEM LEVEL
RTL LEVEL
LOGIC LEVELCIRCUIT LEVEL
Design Options for Digital Systems A variety of options are available for designing a
given digital system These options are used to:
Reduce hardware sizeReduce power consumptionIncrease system performance
6
Design options of digital systems
ASIC
Full-custom Cell-based
Cell library Compiled macros (RAM/ROM/PLA) Platform IP
Gate array
microP/DSP Field-programmable devices
PLD
ROM PAL PLA
FPGA CPLD
Design Options for Digital Systems Comparison of various design options in terms of
time to market and cost
7
PLDs
FPGAs, GAs
Cell-based ASICs
Full-custom ASICs
Design flexibility, Process complexity,Density, speed, NRE cost
Tim
e t
o m
ark
et,
Cost
Design Options for Digital Systems Comparison of design options in terms of cost and
design flexibility
8
Product volume
cost
FPGAs
ASICs
k
GAs
FPGAsCPLDs
Cell-based ASICs
Full-custom ASICs
PLDs
Easy to use
Desig
n fl
exib
ilit
y
Cost = NRE + Fixed + recurring
NRE +fixed cost
k = division of product volume
ASIC Designs: Full-Custom Design In full custom design, each transistor and its layout is
designed carefully in order to achieve the best performance
Full custom offers highest performance and reduced area
9
ASIC Designs: Cell-Based Design Cell based design is composed of a set of predefined
cells with layouts known as standard cells The basic cell types of a typical cell library is as
below
10
Standard cell types Variations
Inverter/buffer/tristate buf-fer
1X, 2X, 4X, 8X, 16X
NAND/AND gate 2 – 8 inputs
NOR/OR gate 2 – 8 inputs
XOR/XNOR gate 2 – 8 inputs
MUX/deMUX 2 – 8 inputs
Encoder/Decoder 2 – 16 inputs
Schmitt trigger circuit Inverted/non-inverted out-put
Latch/register/counter D/JK (sync/async clear/reset)
I/O pad circuits I/O (tristate/bidirectional)
ASIC Designs: Full-custom vs Cell-based
11
Full Custom Cell Based
Design from the scratch Predefined cells with layouts
Sizes are customized Size of each cell is stan-dard
Space is reduced Requires much more space
Performance is higher Performance is lower
Productivity is reduced Improve productivity
ASIC: Gate-Array-Based Designer uses a library of standard cells The design is mapped onto an array of transistors
which is already created on a wafer
12
ASIC Designs: Comparisons Full-custom vs cell-based vs gate-array
13
Full-Cus-tom
Cell-Based Gate-Array
Density Highest Medium Low
Perfor-mance
Highest Medium Low
Design time Long Medium Short
Chip dev. Cost
High Medium Low
testability Difficult Less difficult Easy
Field Programmable devices: FPGA The basic structure of an FPGA is composed of
configurable logic blocks (CLBs) and interconnections as well as input/output blocks
14
PLDs Any combination of logic can be implemented with
sum of product which is AND-OR implementation PLD as a black box:
15
Inputs(logic variables)
Outputs (logic functions)
Logic gates andProgrammable switches
PLDs General structure of PLDs:
Functionality table
16
Device AND-array OR-array
ROM Fixed Programmable
PAL Programmable Fixed
PLA Programmable Programmable
Input bufferand inverters
ANDPlane
ORPlane
X1
X1 X1’ Xn Xn’
Xn
Pk
P1 F1
Fk
PLDs To examine the essential difference among the
various PLD devices, an implementation example is given
Implement the table below using ROM, PLA and PAL
Simplifying the table gives:
17
x y z F1 F2 F3
0 0 0 0 1 0
0 0 1 1 1 1
0 1 0 0 0 0
0 1 1 1 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 0 0 1
0 1 1 0 0 1
PLDs: ROM Requirements:
18
Product term
Inputsx y z
Output func-tionF1 F2 F3
x’y’z’ P1 0 0 0
- 1 -
x’y’z P2 0 0 1
1 1 1
x’yz’ P3 0 1 0
- - -
x’yz P4 0 1 1
1 1 -
xy’z’ P5 1 0 0
1 1 -
xy’z P6 1 0 1
1 1 1
xyz’ P7 1 1 0
- - 1
xyz P8 1 1 1
- - 1
X Y Z
The AND array generates all minterms of the inputs and hence is fixed but the OR array is programmable to implement the required function
P1
P8
P7
P6
P5
P4
P3
P2
F1 F3F2Fixed AND array
Programmable OR array
PLDs: PLA Requirements:
19
Product term
InputsX y z
output
xy’ P1 1 0 - F1
x’z P2 0 - 1 F1, F2
y’ P3 - 0 - F2
xy P4 1 1 - F3
y’z P5 - 0 1 F3
X Y Z
Common terms in the outputs are combined
P1
P2
P3
P4
P5
F1 F2 F3
Programmable ANDarray
Programmable ORarray
PLDs: PAL Requirements:
20
Product term
InputsX y z
Out-put
xy’ P1x’z P2
1 0 -0 - 1
F1
y’ P3 x’z P4
- 0 -0 - 1
F2
xy P5y’z P6
1 1 -
- 0 1
F3
X Y Z
F1 F2 F3
P1
P2
P3
P4
P5
P6
Programmable ANDarray
Fixed OR array
OR gates do not shareproduct terms
Modeling ROM Code and truth table for a
21
InputA1 A0
OutputO1 O2
0 0 0 1
0 1 1 0
1 0 0 0
1 1 1 1
Modeling ROM RTL schematic
22
Modeling ROM Waveform
23