determination of solder paste inspection tolerance limits for fine pitch packages

DETERMINATION OF SOLDER PASTE INSPECTION TOLERANCE

LIMITS FOR FINE PITCH PACKAGES

BY

KRISHNA CHAITANYA CHINTAMANENI

BTech, Jawaharlal Nehru Technological University, 2010

THESIS

Submitted in partial fulfillment of the requirements for

the degree of Master of Science in Industrial and Systems Engineering

in the Graduate School of

Binghamton University

State University of New York

2015

iii

Accepted in partial fulfillment of the requirements for

the degree of Master of Science in Industrial and Systems Engineering

in the Graduate School of


State University of New York

2015

December 09, 2015

Dr. Nagendra Nagarur, Chair

Department of Systems Science and Industrial Engineering,


Dr. Susan Lu, Member



Dr. Christopher Greene, Member



iv

ABSTRACT

Increasing demand for miniaturization in electronic assemblies has driven the

electronics assembly industry to adopt processes to assemble components as small as

01005 passives and active components in the order of 0.3mm pitch (Sbiroli, 2010).

Assembling those small components poses significant challenges to solder paste printing,

which is a crucial stage in the manufacturing of electronics assembly. Numerous studies

have shown that the volume of solder paste deposited is a significant predictor of the

reliability of solder joints.

It is a widely believed fact that 52-71% of SMT defects can be attributed to the

solder paste printing process (Pan, 1999). Detection and prevention of these defects at an

early stage is crucial because each step adds greater value to the PCB and rework costs

increase proportionately. Burr (1998) has shown that correcting a pre-reflow print failure

is ten times cheaper than compared to reworking it after reflow, and at least 50 times less

expensive than reworking after the in-circuit test.

Solder paste inspection (SPI) is a potential process to detect and stop defects at an

early stage (Owen, 2000). Li, et al. (2010), showed that there exists a good correlation

between SPI and Automatic Optical Inspection (AOI) findings which prove that defects

caught at AOI, can be detected and controlled at SPI. However, literature review

indicates that there is little research done on determining SPI tolerances (Chen, 2011).

v

This thesis work is focused on determining SPI tolerances for fine pitch packages.

The packages have been selected after analyzing yield data at a tier I New Product

Introduction [NPI] Electronics Manufacturing Services [EMS] provider. Inspection

methods such as AOI, X-ray Inspection, and Cross section analysis were used to

accumulate data on reliable solder joint and the range of solder volume deposited, leading

to the identification of the desired range. This desired range of solder volume was used as

a basis to determine the SPI tolerance limits. A Design of Experiments (DOE) approach

is implemented to find the optimal print parameters for each package required for

achieving the desired range of solder volume.

vi

Dedicated to my parents and my dear sister

For their endless love, support and encouragement

vii

ACKNOWLEDGEMENTS

I am sincerely grateful to Dr. Srihari, Dr. Nagarur and Mr. Havens for their constant

guidance and support during the entire course of my study. Their valuable inputs and

critiques have enabled me to develop a strong researching technique that has been of

immense help in the professional aspects of my work. I would like to thank Dr. Lu and

Dr. Greene for being part of my committee and providing their valuable inputs on my

research work. I am also grateful to all my professors who taught the courses that I have

taken during my master’s degree.

I would like to thank my manager, Fikreta Jusufagic for her constant support and

continuous encouragement for my research work as well as the other project related

activities. I would also like to thank Dr. Shane Lewis and Tushar Tike for their invaluable

feedback during this research. I will be personally indebted to them for their guidance

and support that enabled me to rise to the expectations of the professional work

environment.

I am immensely thankful to my parents Prasad Chintamaneni and Padmavathi

Chintamaneni and my dear sister Bhargavi, who continuously supported and believed in

me even during the tough times. I am also grateful to all my friends and relatives who

have stood by me and believed in me all these years. Lastly, I am grateful to the God for

everything that he gave me.

viii

Table of Contents

List of Tables………………………………………………………………………………………………………………………………xi

List of Figures………………………………………………………………………………………………………………….…………xii

List of Abbreviations…………………………………………………………………………………………………………………xvi

Chapter 1: Introduction to Research……………………………………………………………………………………………1

1.1 Introduction………………………………………………………………………………..……………………………1

1.2 Problem Statement………………………………………………………………………………..…………………4

1.3 Research Objective………………………………………………………………………………..…………………5

1.4 Research Methodology…………………………………………………………………………….………………5

Chapter 2: Literature Review………………………………………………………………………………………………………7

2.1 Introduction…………………………………………………………………………………………………..…………7

2.2 Solder Paste Printing………………………………………………………………………………………..………7

2.2.1 Factors affecting solder paste printing………………………………………….…………11

2.2.2 Evaluation of the solder paste printing process……………………………….……..16

2.2.3 Solder paste rheology…………………………………………………………………………..…21

2.2.4 Optimization of stencil printing parameters……………………………………………23

2.3 SMT defects due to poor solder paste printing…………………………………………………….…24

2.3.1 Smear…………………………………………………………………………………………………..…24

2.3.2 Insufficient solder……………………………………………………………………………………27

2.3.3 Slump……………………………………………………………………………………………..………27

ix

2.3.4 Solder Bridging…………………………………………………………………………………….…28

2.3.5 Tombstoning………………………………………………………………………………………..…30

2.4 Solder Paste Inspection…………………………………………………………………………………………..31

2.4.1 Need for Solder Paste Inspection………………………………………………………….…31

2.4.2 Determining Solder Paste Inspection (SPI) Tolerance Limits……………………34

2.4.3 Functioning of Solder Paste Inspection machine……………………………………..36

2.4.4 Importance of true height measurement………………………………………………..42

Chapter 3: Research Methodology……………………………………………………………………………………………45

3.1 Introduction……………………………………………………………………………………………………………45

3.2 Methodology Overview………………………………………………………………………………………….46

3.3 Selection of Packages……………………………………………………………………………………………..47

3.3.1 0.4 mm pitch Package on Package…………………………………………………………..47

3.3.2 0.4mm Pitch SMT Connector…………………………………………………………………..53

3.3.3 0.4 mm Pitch Quad Flat No-Leads (QFN) Package……………………………………55

3.3.4 0.5 mm Pitch Surface Mount Connector………………………………………………….57

3.3.5 0.5mm Pitch Quad Flat No-Leads (QFN) Package………………………………….…59

3.3.6 2525 Surface Mount Passives………………………………………………………………….61

3.4 Test Vehicle Specifications……………………………………………………………………………………..63

3.4.1 Test Vehicle1…………………………………………………………………………………………..63

3.4.2 Test Vehicle2…………………………………………………………………………………………..64

3.4.3 Test Vehicle3…………………………………………………………………………………………..64

3.5 Equipment and Chemistries Used…………………………………………………………………………..64

3.6 Finding Optimal Print Parameters…………………………………………………………………………..66

3.6.1 Factors and Levels for DOE 1…………………………………………………………………..67



Chapter 4: Results and Discussions……………………………………………………………………………………………74

4.1 SMT yield analysis…………………………………………………………………………………………………..74

x

4.2 Determination of Solder Paste Inspection Tolerance Limits……………………………………76

4.3 0.4 mm pitch Package on Package (PoP)………………………………………………………………..76

4.3.1 Stencil design optimization…………………………………………………………………….76

4.3.2 Solder Paste Inspection tolerance limits for 0.4 mm pitch PoP……………….86

4.3.3 Finding optimal print parameters for 0.4 mm pitch PoP………………………….88

4.3.4 Validation of optimal print parameters……………………………………………………95

4.4 Solder Paste Inspection tolerance limits for the 0.4mm pitch SMT connector………..97

4.4.1 Finding optimal print parameters……………………………………………………………99

4.4.2 Validation of optimal print parameters…………………………………………………102

4.5 Solder Paste Inspection tolerance limits for 0.4 mm Pitch Quad Flat No-Leads (QFN) Package………………………………………………………………………………………………………………………104


4.6 Solder Paste Inspection tolerance limits for 0.5 mm pitch surface mount connector …………………………………………………………………………………………………………………………………..106


4.7 Solder Paste Inspection tolerance limits for 0.5 mm pitch Quad Flat No-Leads (QFN)

Package………………………………………………………………………………………………………………………108

4.8 Validation of the solder paste inspection tolerance limits…………………………………….110

4.9 2525 Surface Mount Passive…………………………………………………………………………………112

4.9.1 Solderability test on the components……………………………………………………112

4.9.2 Results of DOE 3……………………………………………………………………………………117

Chapter 5: Summary and Future Scope…………………………………………………………………………………..120

5.1 Summary of Research…………………………………………………………………………………………..120

5.2 Future Research……………………………………………………………………………………………………124

Appendix…………………………………………………………………………………………………………………………………126

References………………………………………………………………………………………………………………………………130

xi

List of Tables

Table 2.1: SPI solder volume % information for X board (Chen, 2011)………………...35

Table 2.2: SPI solder volume % information for Y board (Chen, 2011)………………...35

Table 2.3: SPI solder volume % information for Z board (Chen, 2011)………………...35

Table 3.1: Equipment and Chemistries Used………………………………………….…65

Table 3.2: Factors and levels considered for DOE 1………………………………….…67

Table 3.3: Factors and Levels used for DOE 2………………………………………..…69

Table 3.4: Experimental Design for DOE 3…………………………………………..…73

Table 4.1: Factors and Levels in DOE 1-1………………………………………………91

Table 4.2: Validation of the Solder Paste Inspection tolerance limits……………….…111

Table 5.1: Summary of Solder Paste Inspection Tolerance Limits…………………… 123

xii

List of Figures

Figure 1.1: Breakdown of SMT Defects (Biemans, 2011)…………….………………….3

Figure 2.1: Stencil Printing Process (Pan, 1999)…………………………...……………10

Figure 2.2: Aperture Emptying Process (Durairaj, 2001)………………..………………10

Figure 2.3: Dimensions of stencil aperture (Burr, 1998)………………………………...12

Figure 2.4: Solder paste stencil printing variables (Amalu, 2011)……………………....14

Figure 2.5: A hierarchical view of influence variables of stencil printing (Yang, 2005)..15

Figure 2.6: Perpendicular and Parallel Apertures (Pan, 1999)…………………………..20

Figure 2.7: Constituents of solder flux (Amalu, 2011)…………………………………..22

Figure 2.8: Effect of stencil thickness on print defect (Lee, 2001)………………………26

Figure 2.9: Bridging Mechanism (Lee, 2001)…………………………………………...29

Figure 2.10: Tombstoning model analysis (Lee, 2001)………………………………….29

Figure 2.11: Rework cost and the 10X rule (Riddle, 2007)……………………………...33

Figure 2.12(a): Contrast base, gray scale image (Mohanty, 2008)………………………38

Figure 2.12(b): Textured base image (Mohanty, 2008) …………………………………38

Figure 2.13(a): 2D image of solder deposits (Mohanty, 2008)…………………………..38

Figure 2.13(b): Segmented 2D image of solder deposits (Mohanty, 2008)……………...38

Figure 2.14: Height calculation using Moiré topography (Biemans, 2011)……………..41

Figure 2.15: Solder Paste Height Value under normal condition and after filtering

(Kulkarni, 2014)………………………………………………………………………….44

Figure 3.1(a) PoP configuration (Lin, 2007)…………………………………………….49

Figure 3.1(b) PoP bottom Package (Lin, 2007)………………………………………….49

xiii

Figure 3.2: DM3730/25 Digital Media Processor CBC s-PBGA-515 Package (Bottom

View) (Texas Instruments, 2010)………..…………………………………...………….49

Figure 3.3: Mechanism of warpage in PoP (Lin, 2007)………………...……………….50

Figure 3.4: Open joints induced in PoP due to warpage (Lin, 2007)………...………….50

Figure 3.5: Typical head-in-pillow failure between PoP bottom package and PCB…….50

Figure 3.6: Recommended P.C.Board Pattern Layout for the concerned 0.4 mm pitch

SMT connector (Molex, n.d)…………………………………………………………….54

Figure 3.7: Package Dimensions for the concerned 0.4 mm pitch Quad Flat No-Leads

(Onsemi, n.d)………………………………...………………………………….56

Figure 3.8: Package dimensions for the concerned 0.5 mm pitch connector (IHS CAPS

Universe, n.d)…………………………………..……………………………………….58

Figure 3.9: Package outline of 0.5 mm pitch QFN………………………........................60

Figure 3.10: View and Dimensions of 2525 Package

(Vishay Intertechnology Inc., nd)………………………………………………………..62

Figure 4.1: SMT defect analysis…………………………………………………………75

Figure 4.2: Solder bridge defects detected in the inner row of the PoP……………….…78

Figure 4.3: Shadow Moiré test results on the bottom package of the PoP (Source:

Sanmina)…...…………………………………………………………………………….79

Figure 4.4: Cross sectional map used for 'z' calculation…………………………...…….81

Figure 4.5: Cross section images used for 'z' calculation……………………………..…81

Figure 4.6: Pad area measurements using Vision Gauge software……………………...82

Figure 4.7: Aperture size calculation…………………………………………………….84

Figure 4.8: Expanded view for a single pad in the array………………………………...84

Figure 4.9: Final stencil design used for the concerned PoP (Dimensions in mils)……..85

Figure 4.10: Range of Transfer Efficiency (%) of solder paste deposition for the

0.4 mm pitch PoP…………………………………………………………………….…..87

Figure 4.11: Main Effects Plot for DOE1………………………………………………..89

Figure 4.12: Interaction Effects Plot for DOE 1…………………………………………89

Figure 4.13: Pareto Chart of the Standardized Effects………………………….……….90

Figure 4.14: P values of all factors and their interactions in DOE 1…………………….90

xiv

Figure 4.15: Main Effects Plot for Transfer Efficiency in DOE 1-1…………………….93

Figure 4.16: Interaction Plot for Transfer Efficiency in DOE 1-1……………………….93

Figure 4.17: P values of factors in DOE 1-1……………………………………………..94

Figure 4.18: Range of Transfer Efficiency (%) for the 0.4 mm pitch PoP in the

validation run…………………………………………………………………………….96

Figure 4.19: Range of Transfer Efficiency (%) for 0.4 mm pitch SMT connector99

Figure 4.20: Main Effects Plot for DOE 2…………………...…………………………100

Figure 4.21: Interaction Effects Plot for DOE 2………………………………………..100

Figure 4.22: Pareto Chart of the Effects for DOE 2…………………………...……….101

Figure 4.23: P-values for all factors considered in DOE 2……………………………..101

Figure 4.24: Range Transfer Efficiency (%) for 0.4 mm pitch SMT connector in

validation run…………………………………………………………………………...103

Figure 4.25: Range of Transfer Efficiency (%) for 0.4 mm pitch QFN……………..…105

Figure 4.26: Range of Transfer Efficiency (%) for 0.4 mm pitch QFN in validation

run………………………………………………………………………………………105

Figure 4.27: Range of Transfer Efficiency (%) for 0.5 mm pitch connector…………...107

Figure 4.28: Range of Transfer Efficiency (%) for 0.5 mm pitch connector in validation

run……………………………………….……………………………………………...107

Figure 4.29: Range of Transfer Efficiency (%) for 0.5 mm pitch QFN………………..109

Figure 4.30: Range of Transfer Efficiency (%) for 0.5 mm pitch QFN in validation

run………………………………………………………………………………………109

Figure 4.31: DC 1402 component as received from stock……………………………...114

Figure 4.32: Typical appearance of DC1402 after 5 seconds immersion dip and look

test……………………………………………………………………………………....114

Figure 4.33: DC 1348 component as received from stock……………………………...114

Figure 4.34: Typical appearance of DC 1348 after 5 seconds immersion dip and look

test………………………………………………………………………………………114

Figure 4.35: Solderability test report on DC 1402 of the concerned component

(Source: Sanmina)……....................................................................................................115

Figure 4.36: Solderability test report on DC 1348 of the concerned component

(Source: Sanmina)……………………………………………...……………………….116

xv

Figure 4.37: ANOVA for 5 factor model in DOE 3……………………………………………...118

Figure 4.38: Main Effects Plot for Peak Force………………………………………....118

Figure 4.39: ANOVA for 4 factor model in DOE 3…………………………………....119

Figure 4.40: 4 Factor Interaction Plot in DOE 3………………………………………..119

xvi

List of Abbreviations

SMT Surface Mount Technology

SPI Solder Paste Inspection

PCB Printed Circuit Board

AOI Automatic Optical Inspection

AXI Automatic X-ray Inspection

DOE Design of Experiments

QFN Quad-Flat-No-Leads

ANOVA Analysis of Variance

PoP Package on Package

TE Transfer Efficiency

NPI New Product Introduction

EMS Electronic Manufacturing Services

CTE Coefficient of Thermal Expansion

1

Chapter 1: Introduction to Research

1.1 Introduction

Manufacturing processes in the electronics manufacturing industry have been

continually evolving due to a constant increase in demand for ever smaller and more

powerful electronics products. This demand is accompanied by a further requirement to

deliver these products at reduced cost and higher reliability. The fabrication of fine pitch

components with higher I/O was possible due to advancements in Integrated Circuit(IC)

fabrication, ball grid array and flip chip technologies. The introduction of Surface Mount

Technology (hereafter referred as SMT in this report) majorly changed the electronics

industry. There are three essential operations in surface mount assembly: (1) solder paste

printing, (2) component placement and (3) solder reflow. The SMT process starts with

solder paste printing that involves depositing solder paste onto the bare pads of the

Printed Circuit Board (PCB) via stencil printing. A reliable solder joint is dependent on

required solder volume deposition, which is possible through uniform transfer

characteristics of solder paste from the stencil to the PCB. After the solder paste

deposition, different components are placed onto their designated solder pads on the

PCB.

2

Accurate placement of components is crucial for avoiding placement related

defects after reflow. After the placement operation, components are soldered onto to the

board during the reflow process, which is the final stage of the SMT process. During the

reflow process, the solder pads, component leads and solder are heated above the melting

point of solder for a certain period (dwell time) which is necessary for the formation of a

reliable solder joint. The reflow process is aimed at forming reliable solder joints on all

components placed on board without damaging the components.

The PCBs are then inspected after the reflow process to catch any defects that

may have occurred during the SMT process. Defects caught at the end of SMT process

are reworked, which can degrade the reliability of solder joint or sometimes may even

lead to the scrapping of the PCBs. Since there is an industry-wide consensus that a

majority of SMT defects can be related to the solder paste printing process, many

manufacturers are moving towards inspection of solder paste printing operation using 2D

or 3D SPI machines (Valenzuela, 2004). Figure 1.1 shows the breakdown of SMT defects

3

Figure 1.1: Breakdown of SMT Defects (Biemans, 2011)

4

1.2 Problem Statement

The SPI machine is programmed to measure area, height and volume of solder

paste printed on the soldering pads of the PCB. The machine will then check if the

measured values fall within the preset tolerance limits. If the values are within the

tolerance limits, the boards would be passed downstream. If the values are not within the

preset tolerance limits, the concerned locations are flagged by SPI machine. This way the

SPI machine is expected to detect printing related defects before component placement.

However, the SPI tolerance limits are determined subjectively. Review of literature also

indicates that there is little research done on the determination of SPI tolerance limits. As

defects occur only after the reflow process, effective determination of SPI tolerance

limits should be based on feedback from post-reflow inspection (Huang, 2011). SPI

machine set up with incorrect tolerance limits would become ineffective in catching print

related defects. So the problem of subjective SPI tolerance limits is addressed in this

report, by determining SPI tolerance limits based on inspection feedback after reflow.

It is a challenging task to achieve a consistent solder paste deposition with desired

transfer efficiency, especially in the case of fine pitch packages. Transfer Efficiency is

calculated as the solder paste volume deposition divided by its concerned stencil aperture

volume. Having optimal print parameters would help in achieving a consistent good

transfer efficiency of the solder paste. Since the solder paste printing process involves

many variables, a Design of Experiments (DOE) approach has been a proven approach to

understanding the interaction of the variables that influence the solder paste printing. So,

5

a DOE approach is used in this report to find optimal print parameters for all packages

considered in this thesis.

1.3 Research Objective

The goal of this research is to determine the SPI tolerances for different fine pitch

packages using feedback from post-reflow inspection and to use a design of experiments

approach to find optimal print parameters that can help in achieving the desired solder

paste printing consistently.

This report includes

1. Determination of SPI tolerances for the following components

o 0.4 mm pitch Package on Package

o 0.4 mm pitch surface mount connector

o 0.4 mm pitch Quad Flat No-Leads Package

o 0.5 mm pitch surface mount connector

o 0.5 mm pitch Quad Flat No-Leads Package

2. Determination of near optimal print parameters to achieve the desired solder

volume deposition on a consistent basis.

1.4 Research Methodology

This thesis work is performed in two stages. In the first stage, yield data at a Tier I

electronics manufacturer service provider was analyzed to find out the components that

are experiencing solder paste print related defects. Once the packages are listed, the

6

solder paste deposition for each package was analyzed. The SPI tolerances for each

package were determined using the feedback from post-reflow inspection

In the second stage, a DOE approach was used to find out optimal print

parameters for each package that can help in achieving the desired solder volume

deposition on a consistent basis.

A detailed description of the methodology adopted in this research will be given

in Chapter 3 of this thesis work.

7

Chapter 2: Literature Review

2.1 Introduction

SMT is the process of soldering electronic components onto the conductive pads

of PCB. The SMT process consists of three sub-processes: printing solder paste onto the

substrate, automatic placement of components onto their designated locations and reflow

of the substrate along with components to form a solder joint. The Literature Review

shows that 52-71% of SMT defects can be attributed to the solder paste printing process

(Pan, 1999). As the trend of product miniaturization continues to happen, the need for

assembling area array type packages increases. The assembly of area array packages

involves depositing very small solder paste deposits, wherein the surface tension effects

are dominant over the viscous flow of the solder paste. For this reason, printing of solder

paste through small apertures usually results in stencil clogging and incomplete paste

transfer. An in-depth understanding of the interactions between process parameters and

their interactions is essential for achieving acceptable print yields.

2.2 Solder Paste Printing

In the solder paste printing process, solder paste is deposited onto the PCBs

before placing the components. Due to advantages such as high production speed and

cost reduction, stencil printing is widely adopted in the industry for solder paste printing.

8

According to Amalu, et al. (2011), controlling the exact amount of solder paste deposited

on the PCB is one of the main challenges at second level packaging. The solder paste

deposited on the solder pads varies from pad to pad within a PCB, and it also varies from

one PCB to another. This inconsistency is because of many variables involved in the

stencil printing, and the problem of not achieving consistent printing worsens with fine

pitch apertures. Hence, there is a need for a better understanding of solder paste printing

process (Amalu, 2011).

In stencil printing, the solder paste is transferred into the stencil aperture by the

squeegee action and the desired amount of solder paste is left on the pads of the substrate.

According to Nguty (1999), the quality of solder paste printing process is dominated by

the flow of solder paste into the stencil aperture and the aperture emptying process. The

Solder paste must have the ability to deform easily into the stencil aperture when sheared

and flow out of the stencil aperture during paste release (Durairaj, 2001). According to

Yang, et al. (2005), three sequential stages in stencil printing proces are illustrated in

Figure 2.1. In the first stage, a squeegee forces the solder paste to roll in front of its blade

for some distance before shearing off the paste in stencil apertures as the squeegee moves

over the stencil. In the second stage, the hydrodynamic pressure that is generated during

the paste roll injects the solder paste into the stencil apertures. Finally, in the third stage,

solder paste is left on the pad of the substrate after the PCB is mechanically separated

from the stencil. As the board moves away from the stencil, the solder paste experiences

forces at the pad surface and aperture walls. As shown in Figure 2.2, the adhesive

frictional force operating between the stencil walls and the solder paste competes directly

with the adhesive pull force between the solder paste and the PCB bond pad. The net

9

force determines the final release of paste from the stencil aperture (Durairaj, 2001) and

(Amalu, 2011).

10

Figure 2.1: Stencil Printing Process (Pan, 1999)

Figure 2.2: Aperture Emptying Process (Durairaj, 2001)

11

2.2.1 Factors affecting solder paste printing

A number of process parameters influence the solder paste printing process.

According to Haslehurst, et al. (1996), the process parameters can be categorized into

four groups: printer, paste, environmental and stencil. Squeegee pressure, squeegee

speed, stencil separation speed and print direction are the key processes in stencil

printing. Literature Review indicates that area ratio and aspect ratio are important factors

in addressing the challenges of solder paste printing. Durairaj, et al. (2001), showed

experimentally that aspect ratio should be higher than 1.25 and area ratio should be

greater than 0.6. Paste transfer is also directly impacted by particle size and other paste

related properties.

2.2.1.1 Aspect ratio and Area ratio

Aspect ratio is defined as the ratio of aperture width (W) to the stencil thickness (T).

Aspect Ratio = 𝐴𝑝𝑒𝑟𝑡𝑢𝑟𝑒 𝑊𝑖𝑑𝑡ℎ

𝑆𝑡𝑒𝑛𝑐𝑖𝑙 𝑇ℎ𝑖𝑐𝑘𝑛𝑒𝑠𝑠 =

𝑊

𝑇 (Durairaj, 2001)

Area ratio is defined as the ratio of the area of the aperture opening (L*W) to the area of

the aperture wall (2T * (L+W))

Area Ratio = 𝐴𝑟𝑒𝑎 𝑜𝑓 𝑎𝑝𝑒𝑟𝑡𝑢𝑟𝑒 𝑜𝑝𝑒𝑛𝑖𝑛𝑔

𝐴𝑟𝑒𝑎 𝑜𝑓 𝑎𝑝𝑒𝑟𝑡𝑢𝑟𝑒 𝑤𝑎𝑙𝑙 =

𝐿∗𝑊

2∗𝑇∗(𝐿+𝑊) (Durairaj, 2001)

The dimensions of stencil aperture used in the calculation of Aspect ratio and Area ratio

are illustrated in Figure 2.3.

12

Figure 2.3: Dimensions of stencil aperture (Burr, 1998)

13

Amalu, et al. (2011), grouped the critical variables, that influence the solder paste

deposition, into five categories: Solder Paste, Stencil, Substrate, Printer and

Environmental parameters that are shown in Figure 2.4. The stencil and substrate

parameters do not change during the manufacturing process, but the remaining three of

the five parameters stated above, vary either automatically or on their own. A change in

properties of the solder paste during printing process significantly impacts the paste

transfer efficiency.

14

Figure 2.4: Solder paste stencil printing variables (Amalu, 2011)

15

Yang, et al. (2005), proposed “a hierarchical view of influence variables of the stencil

printing” that is shown in Figure 2.5.

Figure 2.5: A hierarchical view of influence variables of stencil printing (Yang, 2005)

16

2.2.2 Evaluation of the solder paste printing process

Lau, et al. (1997), evaluated the solder paste printing process and developed the

five level hierarchies for the solder paste printing process and states that such hierarchical

evaluation of the solder paste printing process is essential for improving the concerned

process. According to Lau, et al. (1997), following are the five major factors that

determine the quality of solder joint: (i) “The choice of stencil opening geometry; (ii) The

matching of the solder paste; (iii) The control of the waiting time (iv) The selection of the

squeegee material; and (v) The parameter setting of printing machine” (Lau, 1997).

Descriptions of the five factors mentioned are as follows:

2.2.2.1 Choice of stencil opening geometry

Chemical etching, laser cutting, and electroforming are the three different stencil

fabrication processes that are used in the stencil manufacturing industry. The Chemical

etching process usually produces a knife edge shaped aperture opening, which affects the

release of solder paste especially when the aperture opening is less than 25µm. Therefore,

an additional process called electropolishing is employed after chemical etching, to

smoothen the knife edge shaped aperture openings. The laser cutting process yields a

stencil opening such that the bottom is slightly larger than the top, and such internal taper

on aperture walls favors the better release of solder paste from the stencil. The

electroforming process can produce a stencil with very fine and smooth aperture with

vertically tapered walls. The stencils fabricated through the electroforming process favors

a smooth release of solder paste even at fine pitch aperture openings (Lau, 1997).

17

2.2.2.2 Matching of solder paste

The quality of the solder paste printing process is greatly influenced by the

composition of solder paste and its corresponding properties. Few characteristics of the

solder paste, such as viscosity, wetting, metal composition, particle shape and size, and

also the flux activity play a significant role in the solder paste printing process (Lau,

1997).

2.2.2.3 Control of waiting time

The wait time of the solder paste after being deposited onto their designated

solder pads affects the solder joint quality. This is because after solder paste printing, the

paste slumps, spreads and absorbs moisture from the environment. The slumping effect

gets more significant for fine pitch components than when compared with normal

components. Excessive wait time can also lead to other defects such as solder balls.

Therefore, the wait time before reflow should be controlled (Lau, 1997).

2.2.2.4 Selection of squeegee material

A squeegee is used to spread the solder paste across the stencil and allow the

transfer of solder paste through the stencil onto the PCB. A harder squeegee favors better

paste transfer when compared to a softer squeegee. A soft squeegee is preferred while

using a stepped stencil. However, using a soft squeegee may cause scoop printing, due to

the spring back property of the soft squeegee. A metal squeegee, usually made from

18

stainless steel, is used as a hard squeegee, and it does not create scooping problem (Lau,

1997).

2.2.2.5 Settings of solder printing process

The solder paste printing process is highly affected by five print machine

parameters. These are the printing pressure, the printing speed, the snap off, the

parallelism of the squeegee, and the squeegee angle. “Environmental conditions such as

humidity and temperature also impact the solder printing process” (Lau, 1997). The

effects of the parameters mentioned above are explained below

Low print speed may lead to inconsistent fill in of stencil apertures because the

low squeegee speed may not favor the roll of solder paste in front of the squeegee. High

print speed will cause loss of viscosity in the solder paste that may lead to slumping and

misprint. It also pushes down the squeegee into stencil apertures and may scoop out some

of the solder paste. On the other hand, if the squeegee pressure is too light, the solder

paste may not adhere to the solder pads. The distance to which the PCB is mechanically

separated at a controlled speed is known as the snap-off distance. The squeegee angle is

the angle at which the squeegee gets in contact with the stencil. The squeegee angle

affects the forces that are required to roll the solder paste in front of the squeegee and

push the solder paste into the stencil apertures. When the squeegee travel direction is

perpendicular to the longer side of the stencil aperture, then the aperture is called a

perpendicular aperture. When the squeegee travel direction is parallel to the longer side

of the stencil aperture, then the aperture is called parallel aperture. Both perpendicular

and parallel apertures are shown in Figure 2.6. Pan, et al. (1999), showed experimentally

19

that a stencil with perpendicular apertures can deposit 5-6% more volume than a stencil

with parallel apertures.

20

Figure 2.6: Perpendicular and Parallel Apertures (Pan, 2004)

21

2.2.3 Solder paste rheology

For several reasons such as low cost, a low melting point when compared to its

alternatives, good mechanical strength and comparatively good solderability, Sn-Ag-

Cu(SAC) solder alloy is considered as the most promising lead-free solder alloy (Kim,

2003). As the print quality of the solder paste is directly impacted by its rheological

properties such as flow, slump resistance, and tack value, rheology of solder paste is

gaining significance. Mallik, et al. (2008), proposed that microscopic distributions of

solder powders strongly affect the rheological behavior of the solder paste. The solder

paste is considered as a non-Newtonian fluid that exhibits thixotropic behavior. Amalu, et

al. (2011), established the way the transfer efficiency of lead-free solder is affected by

“solder paste rheology and stencil aperture cavity size” (Amalu, 2011). According to

Durairaj (2001), consistent withdrawal of the solder paste is highly dependent on the

paste rheology at minuscule aperture sizes. This is because the surface tension dominates

viscous flow at smaller aperture sizes and, therefore, impacts the paste transfer efficiency.

The constituents of the solder flux are shown below, in Figure 2.7.

22

Figure 2.7: Constituents of solder flux (Amalu, 2011)

23

2.2.4 Optimization of stencil printing parameters

Stencil print parameters play a key role in improving the SMT yield. This section

lists the important print parameters and the research that have been done in the

optimization of those key print parameters.

Sekharan, et al. (2006), conducted a half factorial DOE by considering five

factors at two levels and obtained optimal settings for a solder paste printing process.

squeegee pressure, squeegee speed, snap off, separation speed and stencil wipe frequency

were the five different factors that were considered for performing the DOE. The height

of the solder paste deposition was considered as a response variable. The interactions of

the snap off and the separation speed, the print speed and the squeegee pressure, and the

separation speed and the stencil wipe frequency were identified as significant interactions

that influenced the solder paste height deposition. The results of the DOE indicated that

among the two levels chosen for each factor, a high squeegee pressure, high printing

speed, low snapoff , low separation speed were part of optimal print parameters. The

authors have also shown a 20% percent improvement in response variable by performing

a validation run with the optimal print parameters.

Pan, et al. (2004), identified the critical variables that influence the height, area,

and volume of the solder paste deposition. The authors used ANOVA to examine the

influence of aperture size and shape, thickness of the stencil, surface finish of the board,

solder paste type and print speed on the solder paste deposition. Their analysis has shown

that thickness of the stencil and size of the aperture are the two most critical variables that

influence the solder paste deposited.

24

Liu, Y., and Johnson, W. (2007), employed a Taguchi DOE approach to

investigate the effect of the stencil thickness, the squeegee pressure, the PCB separation

speed, and the squeegee speed on the stencil printing process. The transfer efficiency of

solder paste volume was considered as a response variable in the experiment. Out of the

four factors studied, stencil thickness had an obvious effect on the volume transfer

efficiency. The PCB separation speed and the squeegee printing speed had a minor effect,

and squeegee pressure had no significant effect on the response variable. Quicker

separation of the PCB contributed towards a higher transfer efficiency.

2.3 SMT defects due to poor solder paste printing

The usage of miniature components continues to increase as the demand for small

handheld devices is increasing day-by-day. The manufacturing defects that occur during

the assembly of the components can affect the service life of the small handheld devices.

Hence, there is a requirement to understand these defects and stop/control these defects at

the assembly level. According to Ladani, et al. (2008), the most frequent defects such as

smear, insufficient solder, component shift, tombstoning, and solder bridging, are directly

related to solder paste printing and solder reflow process. The following section of this

report includes a brief description of several defects that are related to poor solder paste

printing.

2.3.1 Smear

This defect occurs when the solder paste is deposited in a quantity higher than the

amount required during the solder paste printing process. Smear may appear as “solder

25

paste smudged around pads or as solder paste bridges between neighboring pads” (Lee,

2001). This defect is usually caused by the smear of solder paste around the stencil

aperture opening that is left after processing the previous board. According to Lee (2001),

the (1)aperture orientation (2) stencil thickness (3) poor gasketing of the stencil on the

PCB (4) pitch dimension (5) taper treatment are a few of the factors that contribute to

smear. Figure 2.8 illustrates that the smear usually decreases with increase in stencil

thickness. As the thickness of the stencil increases, the driving force for the solder paste

to slide underneath the stencil becomes weaker.

26

Figure 2.8: Effect of stencil thickness on print defect (Lee, 2001)

27

2.3.2 Insufficient solder

Insufficient solder is a common problem at the stencil printing stage. Here the

aperture clogging does not allow complete transfer of solder paste and, as a result, the

deposited solder volume is less than target solder volume. Insufficiency is caused by a

few factors such as (1) Inadequate paste rheology (2) stencil thickness (3) aperture

orientation (4) pitch dimension (5)improper aperture design (6) insufficient squeegee

pressure (7) powder size (8) poor aperture quality. According to Lee ( 2001), as the pitch

decreases below 30mils, the print defect rate increases very rapidly. At a pitch below 30

mils, insufficiency becomes a dominant defect because clogging of the stencil aperture

increases with decreasing aperture size.

2.3.3 Slump

The slump is usually categorized as the cold slump and the hot slump. The hot

slump is caused by high temperature and usually occurs during the solder reflow stage.

Cold slump refers to the spread of solder paste, “from a brick shape into a smooth dome-

shaped deposit at ambient conditions” (Lee, 2001). Hot slump is caused by (1) low

viscosity of solder paste (2) small particle size (3) low metal or solid content (4) low

thixotropy of solder paste (5) low surface tension of flux (6) wide particle size

distribution (7) high humidity, and (8) high component placement pressure.

28

2.3.4 Solder Bridging

Formation of an interconnection between neighboring pads due to the presence of

excess solder is known as solder bridging. This defect may occur due to a variety of

reasons such as (1) deposition of excessive solder paste (2) smearing of solder paste (3)

excessive component placement pressure, and (4) slumping of solder paste (Lee, 2001).

Figure 2.9 shows the way solder bridging happens. Solder bridging can be controlled by

using the appropriate stencil, by selecting optimal print parameters, and by using a reflow

with a slower ramp-up rate (Lee, 2001).

29

Figure 2.9: Bridging Mechanism (Lee, 2001)

Figure 2.10: Tombstoning model analysis (Lee, 2001)

30

2.3.5 Tombstoning

The phenomenon of the lifting of one end of a two leaded component is known as

tombstoning. This defect is caused by uneven wetting forces at the two ends of the

component during the reflow process. Figure 2.10 shows the forces exerted onto the

component during reflow. The force F1 is exerted by the weight of the component, and

the force F2 is exerted by the surface tension of molten solder underneath the component

and the force F3 is the force exerted by the surface tension of the molten solder that is

present on the right side of the component. The forces F1 and F2 tend to push the

component downward, whereas force F3 tends to force the component to its corner.

When the force F3, overrides the summation of the forces F1 and F2, the situation leads

to a tombstoning defect (Lee, 2001). Tombstoning is affected by factors such as spacing

between the pads, the size of the pads, dimensions of end terminations and most

importantly thermal mass distribution. Spacing that is too wide between the pads can lead

to easy detachment of the component from one end, and too little spacing between the

pads leads to floating of the component during reflow. Both issues eventually lead to

tombstoning. Misprinting of the solder paste can also lead to tombstoning. In this case,

the force F3 (explained above) will be more on one end than the other end. This

imbalance in forces will eventually lead to tombstoning.

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2.4 Solder Paste Inspection

2.4.1 Need for Solder Paste Inspection

The solder paste printing process is a crucial assembly process in SMT that

determines the quality of the solder joints. According to Burr (1997), the solder paste

printing process is considered a “black art” because there are 39 variables involved in the

solder paste printing process and the relationship between those 39 variables is not

completely understood. The volume of the solder paste deposited onto the PCB is

considered to be a good predictor of solder joint reliability and for this reason; an ideal

printing process is aimed at achieving consistent volume on a repeatable basis (Biemans,

2011).

The Boards rejected due to defects would either be reworked or scrapped. Rework

is a non-value adding process, and it requires excessive cost and resources. If not

properly controlled, reworked solder joints can be less reliable and susceptible to fail.

Reworked solder joints are less reliable and are vulnerable to fail at customer site which

can lead to expensive warranty repairs. Scrapping a board incurs additional cost to the

manufacturer and also affects their product delivery timelines. The excess cost of rework

and constant market pressure to reduce cycle time has driven the manufacturer to look for

ways to reduce or eliminate defects upstream in the process (Burr, 1997).

Value added to the board increases as the board moves from one stage to another.

Because of this reason, it is desirable to catch and prevent defects at an early stage.

Washing a misprinted board consumes much less cost and resources than the resources

consumed in reworking a fully processed board. Rework cost can be estimated by using

32

the 10X rule, which states that the rework cost at each stage will be ten times greater than

that in the previous stage. For instance if correcting a misprint of solder paste is

calculated to be $0.50, correcting the failure after reflow would cost $5.00 and correcting

the same failure after the board is integrated into the system would cost $50.00. If

somehow the defect escapes from all the inspection stages and the board fails at the

customer site, the cost to recall the product and correct it could be as high as $500.00 or

even more (Riddle, 2007). The 10X rule could easily justify the cost and resources

invested in setting up a SPI machine and implementing an in-line solder paste inspection.

The 10X rule explained in Figure 2.11. Many electronics manufacturing services

providers have a market requirement to perform 100% solder paste inspection. “These

factors combined with the ongoing need for continuous process improvement drives the

need for solder paste inspection” (Gunn, 2001).

33

Figure 2.11: Rework cost and the 10X rule (Riddle, 2007)

34

Inspection of the solder paste after printing is a potential way to eliminate or

reduce most of the defects. Numerous publications are available online which reiterate

the importance of an in-line SPI machine. According to Johnson (2003), if a SPI machine

is useful for stopping at least a few customer site board failures, the investment made on

the SPI machine would be recovered within a short period. According to Daniels (1996),

EMS providers believe that their profit margins can be increased by increasing the

process quality but not by quoting higher prices or by lowering quality standards. The

profit that manufacturers gain by supplying products with long term reliability is

immeasurable. For these reasons, many manufacturers are starting to give importance to

inspecting boards immediately after solder paste printing by deploying in-line SPI

machines. However, SPI does not eliminate the need for post-reflow inspection stages

such as visual inspection, AOI, Automatic X-ray Inspection (AXI), and In-Circuit Test

(ICT) (Burr, 1997).

2.4.2 Determining Solder Paste Inspection (SPI) Tolerance Limits

Chen, et al. (2011), worked on determining reasonable SPI tolerance limits based

on solder paste volume distribution obtained from mass production data collection. The

SPI tolerance limits were determined for certain packages on three different production

boards. To determine SPI tolerance limits, the authors collected SPI data of certain

packages on three production boards and related the data to inspection feedback from

Automatic X-ray Inspection (AXI). The SPI tolerance limits for different packages are

summarized in Tables 2.1, 2.2, and 2.3.

35

Table 2.1: SPI solder volume % information for X board (Chen, 2011)

Package Average Minimum Maximum StDev SPI tolerance limits

BGA 137.0% 102.0% 191.0% 11.00% 105% - 180%

QFP 124.0% 84.3% 171.0% 13.90% 85% - 165%

0402 85.8% 63.7% 137.0% 9.56% 65% - 130%

0603 115.0% 85.0% 150.0% 8.87% 85% - 145%

0805 109.0% 89.8% 163.0% 6.93% 90% - 140%

1206 108.0% 90.6% 167.0% 7.47% 95% - 140%

2512 94.2% 81.0% 133.0% 6.05% 80% - 125%

SO8 115.0% 85.7% 154.0% 7.94% 90% - 145%

SOP8 115.0% 93.9% 139.0% 5.64% 95% - 135%

Table 2.2: SPI solder volume % information for Y board (Chen, 2011)


0402 & 0603 116.0% 78.9% 191.0% 10.2% 85% - 146%

0805 & Above 114.1% 83.9% 156.8% 10.7% 82% - 146%

SOP <=20 mils pitch 102.3% 76.7% 131.0% 7.9% 78% - 126%

SOP >20 mils pitch 103.5% 79.5% 138.1% 9.6% 75% - 130%

BGA <=20 mils pitch 108.1% 59.4% 131.9% 5.4% 92% - 124%

BGA >20 mils pitch 102.4% 94.5% 111.7% 2.6% 95% - 110%

QFN < = 12 mils 98.2% 75.7% 125.4% 8.6% 73% - 124.1%

QFP < = 20 mils 112.3% 32.8% 152.7% 13.6% 72% - 153%

Table 2.3: SPI solder volume % information for Z board (Chen, 2011)


BGA 0.4 mm pitch 87.7% 52.3% 115.8% 9.9% 57% - 110%

BGA 0.5 mm pitch 73.1% 46.4% 109.6% 9.2% 50% - 100%

0201 71.2% 43.3% 113.9% 10.7% 50% - 120%

0402 92.1% 70.4% 137.7% 11.1% 65% - 135%

Shield Frame 85.7% 63.1% 135.7% 9.9% 60% - 135%

36

It can be noticed from Tables 2.1, 2.2 and 2.3 that the SPI tolerances vary not just

from package to package but also from one board to another. The variation of the

tolerance limits highlights the need for adopting a similar approach when determining the

SPI tolerance limits. So a similar approach is adopted in the fourth chapter of this report

to determine the SPI tolerance limits. The limits are then statistically validated. Later a

DOE approach is employed to find optimal print parameters that can help to achieve

solder paste deposition within the SPI tolerance limits. The optimal print parameters are

validated in validation runs.

2.4.3 Functioning of Solder Paste Inspection machine

2.4.3.1 2D Area Measurement Techniques

Initially, conventional Automated Optical Inspection (AOI) machines were used

for verifying the correctness of solder paste deposit after the solder paste printing. Later

special inspection algorithms were developed to measure important parameters such as

shape, smearing, offset, coverage, slumping and bridging by using stencil Gerber data as

the input file for inspection programming. Later, better algorithms were developed for 2D

SPI inspection that dramatically increased the inspection capabilities of 2D SPI.

However, the disadvantage of 2D technology is that it cannot be used to obtain height and

volume of the solder paste deposit (Biemans, 2011).

In 2D area measurement technique, the method used to collect an image of the

solder paste deposit highly influences the solder paste area measurement. Usually, an

image is acquired through two schemes: contrast based and texture based inspection.

After the image is acquired, image processing algorithms are applied to the image to

37

separate the image of solder paste from its background images such as solder mask, silk

screen, copper traces and bare FR4. A gray scale comparison technique, shown in Figure

2.12a, is employed in the contrast base image processing analysis. In the texture base

analysis, shown in Figure 2.12b, the solder paste is discriminated from its surroundings

by using a special image texture of the solder paste (Marantz Business Electronics, 2012).

38

Figure 2.12(a): Contrast base, gray scale image Figure 2.12(b): Textured base image (Mohanty, 2008)

Figure 2.13(a): 2D image of solder deposits Figure 2.13(b): Segmented 2D image of solder deposits

(Mohanty, 2008)

39

2.4.3.2 3D area measurement technique

In this technique, the image representing the height of the solder deposit at each

pixel is the basis for 3D area measurements. The most common methods used to measure

the solder paste height in 3D SPI are Phase shift moiré and Laser triangulation methods.

In both the techniques, only the height of the solder paste deposit is measured. Area and

volume of each deposit are obtained by integrating the height data of each XY pixel. The

accuracy of the height of the deposit depends on choosing a correct reference, which is

called a ‘zero reference.’ Ideally the solderable pad of the PCB is used as a zero

reference. But as solder paste covers the pad after printing, the pad surface cannot be

used as a zero reference. For this reason, the area surrounding the circumference of the

pad is taken as a zero reference. As the area surrounding the circumference of the pad is

slightly higher than the pad surface, the height offset is applied to the measured value.

The height offset is calculated using a golden board (Biemans, 2011).

Laser triangulation method

Laser triangulation method is one of the oldest technologies used to measure the

height of the solder paste deposit. In this method, “a laser slit beam is projected by a laser

head, and a camera is used to capture the reflected laser lines. The laser head is moved in

defined pitches to cover the target area” (Marantz Business Electronics, 2012).

40

Moiré topography

This is a method used for solder height measurement. This method uses

tridimensional measurement by phase modulation. In this method, “lines are projected on

an object as of modulated inference fringes” (Biemans, 2011). The height of the object is

calculated “by moving the observation grating that creates the lines” (Biemans, 2011).

The height calculation using Moiré topography is shown in Figure 2.14.

41

Figure 2.14: Height calculation using Moiré topography (Biemans, 2011)

42

Dual multisampling laser systems

Dual multisampling laser system combines the advantages of both the Laser

triangulation method and the Moiré topography. The lasers used in this method can

inspect the PCBs with different colors and can also eliminate shadow effects. This

method of inspection is much faster and accurate than either of the methods explained

above (Biemans, 2011).

2.4.4 Importance of true height measurement

The accurate measurement of height is critical to SPI measurement because it has

a direct correlation with solder volume and defects (Kulkarni, 2014). Huang, et al.

(2004), showed that the accurate inspection of solder volume aids in improving the final

quality of the product.

2.4.4.1 Possible causes of Incorrect Volume

Usually, the actual volume of the solder paste deposited is different from the target

volume because “solder paste printing is a complicated process and many factors can

contribute to variation in solder paste deposition” (CyberOptics, 2013). Rheology and

composition of solder paste, stencil and squeegee used and process parameters are the

primary factors that affect the solder paste deposition. Detailed descriptions of all factors

that affect the solder printing process have been mentioned in Sections 2.2.1 and 2.2.2.

The solder paste deposits do not have perfect square edges, especially in the case of fine

pitch packages. Precise volume measurement becomes difficult when the solder deposits

43

do not have perfect square edges, and if the SPI image acquisition system adopts the

image filtering technique, the calculated volume would not be an accurate representation

of actual volume (Kulkarni, 2014). The effect of image filtering is shown in Figure 2.15.

44

Figure 2.15: Solder Paste Height Value under normal condition and after filtering Source: (Kulkarni, 2014)

45

Chapter 3: Research Methodology

3.1 Introduction

As mentioned earlier in Chapter 1, this thesis is focused on determining SPI

tolerance limits for different fine pitch packages. Chapter 2 highlights the several factors

that are involved in solder paste printing and the defects that arise due to the variation in

those factors. The functioning of SPI machine and the necessity of using it in controlling

the solder paste print related defects has also been shown in Chapter 2 of this report.

Electronics manufacturing service (EMS) providers assemble products that belong

to different Original Equipment Manufacturers (OEMs). The products mix would usually

range from a high mix and high complexity to a low mix and low complexity. This is the

rationale behind choosing target packages from the yield analysis of a Tier I New Product

Introduction [NPI] Electronics Manufacturing Services [EMS] provider. A detailed

description of the methodology adopted in completing this research is given in the

following sections of this chapter.

46

3.2 Methodology Overview

This research is performed in two stages. The details of the steps involved in each

stage are described below:

Stage 1:

Analysis of the SMT yield data of an EMS provider to find out the distribution of

defects and identify the proportion of print related defects.

Identification of the different packages on which the defects are occurring on a

recurring basis.

Analysis of the range of the solder paste deposition on the pads of the concerned

packages.

Using the feedback from post-reflow inspection of the concerned packages to

determine the ideal range of solder paste deposition that does not lead to defects.

The ideal range of solder paste deposition would be used as a basis for

determining the SPI tolerance limits.

Stage2:

Two assemblies, which contain all packages chosen in step1, will be selected to

perform a specific DOEs.

Using the design of experiments approach to determine optimal print parameters

that can help in achieving the desired ideal range of solder paste deposition on

concerned packages.

47

3.3 Selection of Packages

The following section gives the list of selected packages and their detailed

descriptions.

3.3.1 0.4 mm pitch Package on Package

Package on Package (PoP) is one of the key technologies used for developing

advanced smart electronic products. Due to several advantages offered by the PoP, it has

been widely used in the electronics industry to meet the never ending drive for smaller,

lighter and more advanced electronic products (Guo, 2013). Despite the success achieved

in PoP technology, there are still some reliability issues in the assembly of the PoP.

Warpage of the package is the most popular issue among the issues related to PoP

assembly. A solution for PoP warpage is provided in this research by optimizing the

stencil design. Along with the optimized stencil design, appropriate SPI tolerance limits

and optimal print parameters to achieve a good transfer efficiency of solder paste are also

provided in this report.

During the assembly of Package on Package (PoP), the solder paste is deposited

for the substrate using the solder paste printing machine and the solder paste deposition is

inspected using the SPI machine. The top package or component is mounted on top of the

substrate using a special module of the component placement machine. As the component

is not related to the solder paste printing, only the substrate package has been considered

as a part of this research.

48

Substrate Package (Processor) (Texas Instruments, 2010)

Package Description : CBP s-PBGA-N515 Package

Package Dimensions : 12mm*12mm

Ball Pitch : 0.4 mm

Solder Ball Diameter : 0.31 mm

I/O count : 515

Solder ball alloy : SAC 305

Manufacturer : Texas Instruments

Manufacturer Part Number : DM3725CBP100

The concerned package is a typical TMV (Through Molding Via) structure as shown in

Figure 3.1(a), which displays the component package and the substrate package of a PoP.

A detailed view of the substrate is shown in Figure 3.1(b). The component, which is a

memory device, is mounted on the I/O pads that are present on the top of the substrate

package, which is the logic processor.

49

Figure 3.1(a) PoP configuration (Lin, 2007)

Figure 3.1(b) PoP Substrate Package (Lin, 2007)

Bottom View of the Substrate Package

Figure 3.2: DM3730/25 Digital Media Processor CBC s-PBGA-515 Package (Bottom View) (Texas

Instruments, 2010)

50

Figure 3.3: Mechanism of warpage in PoP (Lin, 2007)

Figure 3.4: Open joints induced in PoP due to warpage (Lin, 2007)

Figure 3.5: Typical head-in-pillow failure between PoP substrate package and PCB (Lin, 2007)

51

3.3.1.1 Adapting solder volume through aperture design to compensate for warpage in PoP

Warpage is a significant factor that controls the yield of the Package on Package

(PoP) stacking. According to Dreiza, et al. (2005), the assembly of the PoP has unique

requirements. The package may undergo severe warpage during its assembly if the

package materials are not well balanced. As shown in Figure 3.3, the CTE (Coefficient of

Thermal Expansion) mismatch among the die, the mold compound, and the substrate

materials causes the warpage of the package. If the warpage of the bottom package is too

high, it either induces open solder joint defects or head-in-pillow defects between the

substrate package and the PCB. Figure 3.4 and Figure 3.5 shows a typical open solder

joint defect and a head-in-pillow (HIP) defect induced in the PoP due to warpage. Since

the warpage in the PoP is inevitable, the approach of optimizing stencil design is adopted

in this research. Guo, et al. (2013), also adopted stencil design optimization approach to

compensate for package warpage. The goal of the approach used in this research is to

adapt the solder volume deposition at every pad in the PoP array to accommodate for

expected package warpage at each pad. The details of the approach used are explained in

the following steps

Step 1: Determination of warpage shape of the PoP

The PoP considered in this research was subjected to a Shadow Moiré test to

identify the shape of the package after it undergoes warpage. The detailed report of the

Shadow Moiré test is included in the fourth chapter of this report. The Shadow Moiré test

report indicated that the PoP is warping in the shape of an elliptical paraboloid.

Step 2: Modeling the package warpage

52

In this step, the warpage of the package and substrate assembly is modeled to

determine the standoff heights at every pad in the PoP array. Standoff height is the post-

reflow solder height at a pad. Since the Shadow moiré test reveals that the package is

warping in the form of an elliptical paraboloid, the general equation for an elliptical

paraboloid has been considered to define the distribution of standoff heights over the PoP

pad array.

The general equation for an elliptical paraboloid is z = ax2 + by2 (Rogness, n.d). In the

equation, z represents the standoff height at the co-ordinates (x,y). ‘a’ and ‘b’ are the

constants representing the curve.

Cross section analysis on samples from the previous run provided input data for solving

the equation mentioned above. The final equation obtained was used for calculating

standoff heights at every pad of the package

Step 3: Pad area measurement.

Step 4: Calculation of desired solder volume.

Step 5: Aperture size calculation

As the stencil is of constant thickness, dividing the desired volume at each pad,

obtained in step 4, with the stencil thickness gave the aperture area for each pad to be cut

on the stencil. The calculated aperture area is used for finding the aperture size.

53

3.3.2 0.4mm Pitch SMT Connector

The concerned connector is a dual row SMT connector with 40 pins, 0.4 mm

pitch. It is the fine pitch nature of this package that is behind the selection of this package

for analysis.

Package Category : PCB Receptacles

Pitch : 0.40 mm

Termination Interface: Style : Surface Mount

Plating Termination : Gold

Manufacturer : Molex

Manufacturer Part Number : 502426-4010 (Molex, n.d)

54

Recommended P.C.Board Pattern Layout:

Figure 3.6: Recommended PCB Pattern Layout for the concerned 0.4 mm pitch SMT connector (Molex,

n.d)

55

3.3.3 0.4 mm Pitch Quad Flat No-Leads (QFN) Package

The Quad flat no-lead (QFN) package has excellent thermal and electrical

performance, a small footprint, and a low manufacturing cost. For these reasons, the

usage of QFNs in the electronics industry has been increasing in recent years (How,

2013). The details of the 0.4 mm pitch QFN package studied in this report are given

below.

Package type : Quad flat No-Lead

Package dimensions : 1.7mm*2.0mm*0.5mm

Terminal pitch : 0.4mm

Manufacturer : Onsemi

Manufacturer Part Number : NLAS8252MUTAG (Onsemi, n.d)

56

Package Dimensions and Recommended PC Board Layout Pattern

Figure 3.7: Package Dimensions for the concerned 0.4 mm pitch Quad Flat No-Leads package (Onsemi,

n.d)

57

3.3.4 0.5 mm Pitch Surface Mount Connector

With the advanced solder paste printers in place, achieving an excellent transfer

efficiency of solder paste onto the PCB is not a significant challenge. However,

inappropriate solder paste printer settings may cause defects such as excess solder,

insufficient solder, and solder balls. Having the appropriate print parameters would avoid

defects from happening in the first place, and the SPI machine with reasonable tolerance

limits will act as a checkpoint for controlling the solder paste related defects. The details

of the 0.5 mm pitch SMT connector studied in this report are given below.

Connector Type : Board Connector

Terminal Type : Surface Mount

Terminal Pitch : 0.5 mm

Contact Finish Termination : Tin over Nickel

Manufacturer : KEL Corporation

Manufacturer Part Number : DCC01-20L3-C (IHS CAPS Universe, n.d)

58

Package Dimensions

Figure 3.8: Package dimensions for the concerned 0.5 mm pitch connector (IHS CAPS Universe, n.d)

59

3.3.5 0.5mm Pitch Quad Flat No-Leads (QFN) Package

The details of the 0.5 mm pitch QFN package studied in this report are given

below:

Package type : Quad flat No-Lead

Package dimensions : 4mm*4mm*0.85mm

Terminal pitch : 0.5mm

Manufacturer : Silicon Labs

Manufacturer Part Number : Si5338 (Silabs, n.d)

60

Package Outline and its Dimensions

Figure 3.9: Package outline of 0.5 mm pitch QFN (Silabs, n.d)

61

3.3.6 2525 Surface Mount Passives

With the advanced solder paste printers in place, achieving a proper solder paste

deposition for reliable assembly of a 2525 surface mount passive component is not a

significant challenge. However, while assembling components that have solderability

problems, even solder paste deposition within tolerance limits cannot avoid the

occurrence of defects such as non-wetting or open joint. The concerned package is

included in this thesis to show that adding additional solder paste becomes essential while

assembling old date code parts. A DOE approach has been adopted to determine the

significant factor that affects the strength of the solder joint. Details of the 2525 surface

mount passive included in this report are listed below.

Package type : Surface Mount Passive, Inductor

Manufacturer : Vishay Intertechnology Inc.

Manufacturer Part Number : IHLP2525CZER3R3M11

62

Package Outline and its Dimensions

Figure 3.10: View and Dimensions of 2525 Package (Vishay Intertechnology Inc., nd)

63

3.4 Test Vehicle Specifications

Three different PCBs, which consist of a pad layout that will accept all the

packages explained in section 3.3, have been used in this research. These PCBs are

assembled in high volume at the EMS facility where this research was performed. Solder

samples of the concerned PCBs have been used for the purpose of experimentation. A

solder sample is a close representation of the actual production board regarding board

thickness, cross sectional design, number of planes, and has exactly same pad layout, and

surface finish. It is assumed that the usage solder samples would not impact the results of

the experiment performed in this research. Although the PCBs are not Test Vehicles, for

the ease of explanation the PCBs are named as Test Vehicle1, Test Vehicle2 and Test

Vehicle3. The details of the test vehicles are given below:

3.4.1 Test Vehicle1

The Test Vehicle1 has eighteen layers and is 2.93 mm thick, Lead-Free FR-4

grade PCB. The dimensions of the PCB are 159.1 mm*118.97 mm. The pads are non

solder mask defined (NSMD), and the surface finish is electroless nickel immersion gold

(ENIG). This Test Vehicle accommodates the 0.4 mm pitch package on package (PoP),

the 0.4 mm pitch Quad Flat No-Leads (QFN) package, 0.5 mm pitch surface mount

connector, and 0.5 mm pitch Quad Flat No-Leads (QFN) package 3.3.1, 3.3.3, 3.3.4, and

3.3.5 respectively.

64

3.4.2 Test Vehicle2


grade PCB. The dimensions of the PCB are 178.1 mm*115.76 mm. The pads are non

solder mask defined (NSMD), and the surface finish is electroless nickel immersion gold

(ENIG). This Test Vehicle accommodates the 0.4 mm pitch surface mount connector that

is described in section 3.3.2.

3.4.3 Test Vehicle3


grade PCB. The dimensions of the PCB are 194.9 mm*181.18 mm. The pads are solder

mask defined (SMD), and the surface finish is electroless nickel immersion gold (ENIG).

This Test Vehicle accommodates the 2525 surface mount inductor that is described in

section 3.3.7.

3.5 Equipment and Chemistries Used

The equipment and chemistries utilized in this research are summarized in Table

3.1

65

Table 3.1: Equipment and Chemistries Used

Manufacturer Make and Model

Solder Paste Printing Machine ESE/ Speedline Technologies US-8500X/ MPM

UP3000

Solder Paste Alpha OM350: SAC 305, Lead-

Free, No Clean, Type 4

Lead-Free Flux Gel Alpha OM338

Solder Paste Inspection (SPI)

Machine Cyber Optics SE 500X/ SE 350

Component Placement Machine FUJI NXT III

Reflow Oven Conceptronic

Profile 160: 11 Heating

Zones and 2 Cooling

Zones

Automatic Optical Inspection YESTECH F1/ FX

Automatic X-ray Inspection Agilent Technologies V 810, Series 5000

3D X-ray Inspection Nordson Dage XD7500NT

66

3.6 Finding Optimal Print Parameters

As already mentioned in Chapter 2, the stencil printing process is considered to be

one of the most important processes among the surface mount assembly processes.

Review of Literature indicates that printing of Lead-Free solder paste through fine pitch

aperture openings results in poor transfer efficiency of the solder paste due to clogging of

the stencil apertures.

Various studies, as mentioned in Chapter 2, have studied the interactions between

each of the adjustable print parameters and determined the optimal print parameters. For

this research purpose, three different DOEs have been performed. Two of these DOEs

were performed to determine optimal print parameters on Test Vehicle1 and Test

Vehicle2. DOE 3 has been performed to show the significant factor that affects the

solderability of a component that was exhibiting slow wetting behavior. The factors and

levels considered for performing the DOEs are mentioned below. The factors mentioned

below were chosen based on the Literature Review and the fact that these are the most

commonly adjusted print parameters in the production environment.

67

3.6.1 Factors and Levels for DOE 1

Table 3.2: Factors and levels considered for DOE 1

Factors Low level High level

Squeegee Pressure 2 kgf 3 kgf

Squeegee Speed 25 mm/sec 40 mm/sec

Snap off off on

Print Stroke 1 2

68

Squeegee pressure is the pressure applied by the metal squeegee while moving the

solder paste. Squeegee speed is the speed at which the squeegee rolls the solder paste.

Snap off ‘on’ is the condition where the board is mechanically separated from the stencil

at a controlled speed for a certain distance downward.

DOE 1 was performed on Test Vehicle1. The solder paste printing machine used

for this experiment is an ESE, Model US-8500X. A stainless steel laser cut stencil was

used along with a 12-inch metal squeegee blade. The thickness of the stencil used was

0.1016 mm (4 mils), and aperture openings have rounded corners. The pad design of the

Test Vehicle1 is Non Solder Mask Defined.

A full factorial DOE with two replications that accounts for 32 runs (24 * 2 = 32)

were conducted and the corresponding Solder paste deposition was recorded using a

CyberOptics make, SE 500X model SPI machine. The transfer efficiency of the solder

paste was used as the response variable for this experiment.

69


Table 3.3: Factors and Levels used for DOE 2

Factors Low level High level

Squeegee Pressure 10 pounds/inch2 12 pounds/inch2

Squeegee Speed 0.8 inches/second 1 inches/second

Snap off Standard Stepped

Wipe Frequency Alternate Board Every Board

70

Squeegee Pressure and Squeegee Speed factors are explained in Section 3.6.1.

The corresponding units are different from those mentioned in Table 3.2, as the solder

paste printing machine used for performing this experiment is a different one. When the

printer is set at ‘Standard’ Snap off level, the PCB is separated downward from the

stencil in continuous motion for 0.1 mm at a speed of 0.05mm/second. When the printer

is set at ‘Stepped’ Snap off level, the PCB is separated downward from the stencil in

steps for 0.1 mm at a speed of 0.03mm/second. The step size is 0.0010 mm, and there is a

delay of 0.05 seconds between each step. Wipe frequency at low level corresponds to

cleaning underneath of stencil after printing two boards and wipe frequency at high level

corresponds to cleaning underneath of stencil after printing every board.

DOE 2 has been performed on Test Vehicle2. The solder paste printing machine

used for this experiment is a Speedline Technologies, Model MPM UP3000. A stainless

steel laser cut stencil was used along with a 10-inch metal squeegee blade. The thickness

of the stencil used is 0.1016 mm (4 mils), and aperture openings have rounded corners.

The pad design of Test Vehicle2 is Non Solder Mask Defined. A full factorial DOE with

16 runs (24 = 16) was conducted, and the corresponding solder paste deposition was

recorded using a CyberOptics, Model SE 350 SPI machine. The transfer efficiency of the

solder paste deposited for the package described in section 3.3.2 was used as the response

variable for this experiment.


The 2525 surface mount passive components described in section 3.3.8 have been

exhibiting slow to wet behavior, non-wetting or open terminations after reflow. A

71

solderability test performed on those components confirmed that solderability is possible,

but the result is out of specification. [IPC/JEDEC J- STD- 002C Test A1, B1 & G1

Solderability Tests for Components Leads, Terminations, Lugs, Terminals, and Wires ]

The objective behind this DOE is to evaluate different process changes to improve yield

and joint quality. Table 3.4 shows the experimental design.

In this experiment, the Reflow Profile was used as the first factor to see the effect

of the solder reflow peak temperature on the solder joint. The Date Code of the concerned

Inductors (2525 package) was used as the second factor. During solderability test, date

codes 1347 and 1348 exhibited similar wetting behavior; for this reason, both 1347 and

1348 Date Codes were considered on the same level. Paste Volume is the third factor,

where the level ‘Standard’ corresponds to depositing solder paste using the stencil

printing process and the level ‘Manual Addition’ corresponds to hand dispensing more

solder paste onto the pads before placement of the concerned component onto the PCB.

Tinning is the fourth factor where the level ‘Fresh’ refers to no tinning of the concerned

component and the level ‘Tinned’ refers to tinning the concerned component before

placing it onto the PCB. For tinning, the components were cleaned with sand paper,

fluxed and dipped in a solder pot. Flux Treatment is the fifth factor where the level

‘None’ refers to no treatment with flux and the level ‘Treated with flux’ refers to the

processing of the concerned component with flux before placing it onto the PCB. Lead-

Free No-Clean Flux Gel (Alpha OM 338) was used for flux treatment in this experiment.

Only one operator performed the solder paste addition, tinning and flux treatment

operations for all experimental runs.

72

This experiment was performed on Test Vehicle3. The solder paste printing

machine used for this experiment is an ESE, Model US-8500X. A stainless steel laser cut

stencil was used along with a 10-inch metal squeegee blade. The thickness of the stencil

used was 0.1016 mm (4 mils), and aperture openings have rounded corners. The pad

design of the Test Vehicle3 is Solder Mask Defined (SMD)

A full factorial DOE that accounts to 32 runs (25= 32) were conducted and the

concerned Inductors were hand placed onto the PCB. After the reflow, the solder joints

were subjected to shear test an “Instron Model 4450”. The peak force required to shear

off the component solder joints is considered as the response variable for this experiment.

The results and discussions of all three DOEs are presented in the fourth chapter

of this thesis.

73

Table 3.4: Experimental Design for DOE 3

Factor Level I Level II

1 Reflow Profile Original Hotter

2 Date Code 1347&1348 1402

3 Paste Volume Standard Manual Addition

4 Tinning Fresh Tinned

5 Flux Treatment None Treated with flux

74

Chapter 4: Results and Discussions

4.1 SMT yield analysis

As mentioned in the methodology section of this thesis, the yield data of a Tier I

New Product Introduction [NPI] Electronics Manufacturing Services [EMS] provider is

analyzed, and the distribution of SMT related defects is shown in Figure 4.1. Fourth

Quarter of 2015 (Q4’ 2015) SMT yield data of the EMS facility, where this research was

performed, was analyzed to obtain the results shown in Figure 4.1. It is evident from

Figure 4.1 that more than 60% of SMT defects can be related to the solder paste printing

process. Following is the list of packages that were identified to have more print-related

defects.

0.4 mm pitch Package on Package

0.4 mm pitch surface mount connector

0.4 mm pitch Quad Flat No-Leads Package

0.5 mm pitch surface mount connector

0.5 mm pitch Quad Flat No-Leads Package

75

Figure 4.1: SMT defect analysis

76

4.2 Determination of Solder Paste Inspection Tolerance Limits

The SPI tolerance limits for all the five different packages listed in section 4.1

were determined from data sets of limited size that are obtained from different production

runs at a Tier I NPI EMS provider. Since the data sets were obtained from different

production runs, the range of Transfer Efficiency (%) graphs shown in the further

sections of this report show bimodal distribution.

4.3 0.4 mm pitch Package on Package (PoP)

4.3.1 Stencil design optimization

The PoP included in this report has initially shown almost 90% yield loss after

SMT. Failure analysis of the concerned Assembly indicated that (a) no defects were

observed for the component. (b) Solder bridging defects were found on the substrate of

the PoP (on the center array of the package). X-ray images of the defects are shown in

Figure 4.2. The thickness of the stencil used for the concerned assembly was 0.1016 mm

(4 mils), and the stencil had the same aperture openings for all pads of the PoP. It was

found that the defects occurred due to excess solder deposition and can be avoided by the

stencil design optimization. The goal of the stencil design optimization approach is to

adapt the solder volume deposition at every pad in the PoP array to accommodate for

package warpage at each pad. The details of the approach used are explained in the

following steps

Step 1: Determination of warpage shape of the PoP

77

Lin, et al. (2007), measured the warpage of a PoP at different temperatures and

found that the PoP undergoes warpage in various ways at different temperatures. When

the PoP is processed along with the PCB, the warpage of the PoP gets locked in a

particular shape after solidification of the molten solder. To find the shape of the warpage

that gets locked between the PoP and the PCB, the concerned package along with the

PCB was subjected to Shadow Moiré test at AkroMetrix, LLC. The Shadow Moiré test

results showed that the package is warping in the shape of an elliptical paraboloid, and

the results of the test are shown in Figure 4.3.

78

Figure 4.2: Solder bridge defects detected in the inner row of the PoP

79

Figure 4.3: Shadow Moiré test results on the bottom package of the PoP (Source: Sanmina)

80

Step 2: Modeling the package warpage

In this step, the warpage of the package and substrate assembly is modeled to

determine the standoff heights at every pad in the PoP array. Standoff height is the post-

reflow solder height at a pad. The general equation for an elliptical paraboloid has been

considered to define the distribution of standoff heights over the PoP pad array.

The general equation for an elliptical paraboloid is z = ax2 + by2 (Rogness, n.d).

In the equation, z represents the standoff height at the co-ordinates (x,y). ‘a’ and ‘b’ are

the constants representing the curve. Cross section analysis on the samples from the

previous run provided input data for solving the equation mentioned above. Figure 4.4

shows the cross section location on the package. Figure 4.5 displays the images of cross-

sections that were used to calculate the standoff heights. The standoff heights measured

from the cross-section analysis were considered as ‘z’, and the coordinates of the

concerned location were considered as ‘x’ and ‘y.’ 22 data points were obtained from the

cross-section analysis and the corresponding x, y and z values are tabulated in Appendix

A1. Following equation is obtained for calculating standoff heights after using cross

section data points to solve the paraboloid equation:

z = 0.0015935 x2 + 0.0441497 y2

81

Figure 4.4: Cross sectional map used for 'z' calculation

Figure 4.5: Cross section images used for 'z' calculation

82

Step 3: Pad area measurement.

Pad area measurements of all pads in the PoP array were performed with a high

precision microscope using Vision Gauge software.

Figure 4.6: Pad area measurements using Vision Gauge software

83

Step 4: Calculation of desired solder volume

The desired solder volume at each pad was calculated by multiplying the standoff

height at each pad with its respective pad area.

Step 5: Aperture size calculation

As the stencil is of constant thickness, dividing the desired solder volume at each

pad, obtained in step 4, with the stencil thickness gave the aperture area for each pad to

be cut on the stencil. This calculated aperture area was used for finding the aperture size.

The methodology adopted for aperture size calculation is explained in Figure 4.6.

Aperture width is calculated using the following equation:

S*calculated = {(Measured Pad Area ×Standoff Height) ÷Stencil Thickness}1/2

Figure 4.7 gives a detailed explanation of the equation used for aperture width

calculation.

The methodology explained above yielded aperture openings that are smaller than 8.8

mils. Achieving a good transfer efficiency at aperture openings smaller than 8.8 mils is a

significant challenge. For this reason, the stencil aperture openings had to be normalized,

and the smallest aperture opening started from 8.8 mils. Finally, the aperture openings for

the concerned PoP were segregated into four sections with each section having a different

size. Figure 4.9 shows the detailed view of stencil design used for the concerned PoP. As

per IPC 7525B, the stencil aperture openings are considered to be square with rounded

corners. This stencil design helped to compensate for the package warpage.

84

Figure 4.7: Aperture size calculation

Figure 4.8: Expanded view for a single pad in the array

85

Figure 4.9: Final stencil design used for the concerned PoP (Dimensions in mils)

86

4.3.2 Solder Paste Inspection tolerance limits for 0.4 mm pitch PoP

The range of solder paste deposition for the 0.4 mm pitch PoP is shown in Figure

4.10, and it is expressed in terms of transfer efficiency of the solder paste deposition.

Transfer Efficiency is calculated as the solder paste volume deposition divided by its

concerned stencil aperture volume. The range of transfer efficiency leading to defects is

also shown in Figure 4.10. The transfer efficiency of the solder paste volume deposition

ranged from 19.2% to 134.6%. By correlating the post-reflow inspection with the transfer

efficiency of solder paste deposition, it was found that transfer efficiency less than 38%

lead to defects such as insufficient solder and head in pillow. No instances of solder

bridging were observed even with the transfer efficiency of 134.6%. So, 130% of the

stencil aperture volume is considered as a reasonable upper limit for the concerned PoP.

Therefore, the SPI tolerance limits for the concerned 0.4 mm pitch PoP are set as 40% -

130% of the stencil aperture volume. The decision on tolerance limits for the solder paste

volume deposition is determined by analyzing more than 164,000 data points. The data

points are obtained from solder paste deposition on 319 PCBs for the concerned PoP.

87

Figure 4.10: Range of Transfer Efficiency (%) of solder paste deposition for the 0.4 mm pitch PoP

88

4.3.3 Finding optimal print parameters for 0.4 mm pitch PoP

As explained in section 3.2, a DOE approach was adopted to determine optimal

print parameters. Optimal print parameters for the concerned PoP were found in DOE 1.

The methodology of performing DOE 1 is explained in detail in section 3.6.1. The

experimental design for DOE 1 is shown in Appendix A2.

The printing was executed using the following experimental conditions:

Printing Equipment : US-8500X (ESE)

Solder Paste : Alpha metals OM 350 (Type 4, SAC 305)

Stencil Thickness : 0.1016 mm (4 mils)

Stencil Type : Stainless Steel, Laser Cut

16 different runs, with two replications for each run that accounts for a total of 32

runs were executed for this experimental setup. An automated SPI (Cyber Optics, Model

SE 500X) was used to measure the solder paste deposited on the PCB. The transfer

efficiency of the solder paste volume deposition was considered as the response variable

for this experiment. The average transfer efficiency on 515 solder pads masked the lower

transfer efficiency values and, for this reason, each section of the PoP (the PoP has four

sections of aperture openings) was evaluated separately, and the final results were

compared. Out of the four evaluations, three of them yielded the same significant factors

and interactions. The fourth evaluation did not show any significant factors. The main

effects and interaction effects between each of the factors studied are shown in Figure

4.11 and Figure 4.12.

89

Figure 4.11: Main Effects Plot for DOE1

Figure 4.12: Interaction Effects Plot for DOE 1

90

Figure 4.13: Pareto Chart of the Standardized Effects

Figure 4.14: P values of all factors and their interactions in DOE 1

91

From Figure 4.11, it can be noticed that low Squeegee Pressure affected the

transfer efficiency positively. Squeegee Speed does not have a significant effect on the

transfer efficiency. Snap off ‘on’ resulted in improving the transfer efficiency. Figures

4.13 and 4.14 illustrate that ‘Print Stroke’ is the most significant factor among all of the

factors considered. As print stroke has a P-value (0.019) less than 0.05, at a confidence

level of 95%, it is considered as a significant factor.

To find optimal print parameters, a second level DOE (named as DOE 1-1) was

performed, by fixing Squeegee Speed at 40 mm/sec and Print Stroke at 2. Since DOE 1

indicated that Squeegee Speed is not affecting the transfer efficiency, it is kept constant at

40mm/sec. Since Print Stroke is the significant factor among all the factors considered in

DOE 1, there is impetus to further explore this variable. However, best practices in

electronics manufacturing do not encourage using more than two print strokes. As two

print strokes yielded high transfer efficiency of solder paste, print stroke is kept constant

at 2 for DOE 1-1. Squeegee Speed and Snap off are the two factors that are further

explored in DOE1-1. Table 4.1 summarizes the factors and their corresponding levels.

The experimental design for DOE 1-1 is shown in Appendix A3.

92

Table 4.1: Factors and Levels in DOE 1-1

Factors Level 1 Level 2 Level 3

Squeegee Speed (kgf) 1.5 2 2.5

Snap off 1 2 3

Snap off at Level 1 triggers the solder paste printing machine to separate the PCB

at 0.5 mm/sec for a distance of 2 mm. Snap off at Level 2 triggers the machine to lift the

squeegee at a speed of 2mm/sec for a distance of 4 mm. Snap off at Level 3 triggers

machine to lift the squeegee and separate the PCB at the same time. The main effects and

interaction effects between each of the factors studied are shown in the following plots.

93

Figure 4.15: Main Effects Plot for Transfer Efficiency in DOE 1-1

Figure 4.16: Interaction Plot for Transfer Efficiency in DOE 1-1

94

Figure 4.17: P values of factors in DOE 1-1

95

From Figure 4.15, it can be noticed that low squeegee pressure (1.5 kgf) favored

high transfer efficiency of solder paste and Snap off at Level 3 has affected the transfer

efficiency of solder paste positively. From Figure 4.17, it can be noticed that none of the

factors is significant as both the factors have a p-value greater than α (0.05) at 95%

confidence interval. So the optimal print parameters for the assembly of the Test Vehicle

1 are listed below:

Squeegee Pressure : 1.5 Kgf

Squeegee Speed : 40 mm/sec

Snap off : On at Level 3

Print Stroke : Two times

Wipe frequency : 1 (Stencil clean after every board)

4.3.4 Validation of optimal print parameters

By using the optimal print parameters found in DOE1, a trial run was conducted

on 42 boards of Test Vehicle1, which employs of the concerned PoP. The range of solder

volume transfer efficiency obtained by using the new print parameters is shown in Figure

4.18. By comparing Figure 4.10 and Figure 4.18, it can be noticed that in the validation

run, the mean of solder paste transfer efficiency has increased from 77.1% to 81.8% and

the standard deviation has decreased from 12 to 7.6. The transfer efficiency of solder

paste deposition is well within the tolerance limits defined for the 0.4 mm pitch PoP in

section 4.2.2.

96

Figure 4.18: Range of Transfer Efficiency (%) for the 0.4 mm pitch PoP in the validation run

97

4.4 Solder Paste Inspection tolerance limits for the 0.4mm pitch SMT

connector

The range of solder paste deposition for the 0.4 mm pitch SMT connector

expressed in terms of transfer efficiency of the solder paste deposition is shown in Figure

4.19. The figure shows a bimodal distribution, and it also highlights the range of transfer

efficiency leading to defects. As mentioned in section 4.2, the data points used for

constructing the histogram shown in Figure 4.19 are obtained from different production

runs. This is the reason behind the bi-modality observed in Figure 4.19.

The transfer efficiency of the solder paste volume deposition ranged from 34.5%

to 167.1%. By correlating the post-reflow inspection of the concerned connector with the

transfer efficiency of the solder paste deposition, it was found that transfer efficiency

less than 58% leads to an ‘insufficient solder’ defect and transfer efficiency more than

142% leads to a ‘solder bridge’ defect. Therefore, the SPI tolerance limits for the

concerned 0.4 mm pitch SMT connector are set as 60%-140% of the stencil aperture

volume. The decision on tolerance limits for solder paste deposition is determined by

analyzing 50,000 data points. The data points are obtained from solder paste deposition

on 1325 PCBs for the concerned connector.

98

Figure 4.19: Range of Transfer Efficiency (%) for 0.4 mm pitch SMT connector

99

4.4.1 Finding optimal print parameters

Optimal print parameters for the 0.4 mm pitch SMT connector were found in

DOE 2. The methodology for performing DOE 2 is explained in detail in section 3.6.2.

The experimental design for DOE2 is shown in Appendix A4

The printing was executed using the following experimental conditions:

Printing Equipment : Speedline Technologies, Model MPM UP3000

Solder Paste : Alpha metals OM 350 (Type 4, SAC 305)

Stencil Thickness : 0.1016 mm (4 mils)

Stencil Type : Stainless Steel, Laser Cut

Squeegee : Stainless steel squeegee

Squeegee angle : 45 degrees

Print Stroke : 1

A full factorial DOE that includes 16 different runs was executed for this

experimental setup. An automated SPI (Cyber Optics, Model SE 350) was used to

measure the amount of solder paste deposited on the PCB. Transfer Efficiency was the

response variable for this experiment. Although Print Stroke was identified as the most

significant factor in DOE 1, it is kept constant at 1 all throughout the DOE 2. This

decision was made using expert knowledge based on anecdotal evidence. The main

effects and interaction effects between each of the factors studied are shown in the

following plots.

100

Figure 4.20: Main Effects Plot for DOE 2

Figure 4.21: Interaction Effects Plot for DOE 2

101

Figure 4.22: Pareto Chart of the Effects for DOE 2

Figure 4.23: P-values for all factors considered in DOE 2

102

From Figure 4.20, it can be seen that at Print Stroke 1, Squeegee Pressure and

Snap off do not affect the transfer efficiency of the solder paste. Lower Squeegee Speed

slightly favors higher transfer efficiency. Figures 4.20, 4.22 and 4.23 collectively show

that Wipe Frequency is the significant factor among all four factors considered. Figure

4.23 show that the ‘Wipe Frequency’ has a P-value close to 0, which is less than α (0.05)

at 95% confidence interval. Based on the results from DOE 2, optimal print parameters

for the concerned 0.4 mm pitch connector are listed below:

Squeegee Pressure : 12 Pounds/inch2

Squeegee Speed : 0.8 inches/sec

Snap off : Stepped

Wipe frequency : 1 (Stencil clean after every board)



on 30 boards of Test Vehicle2, which includes the concerned 0.4 mm pitch SMT

connector. The range of solder volume transfer efficiency obtained by using the new print

parameters is shown in Figure 4.24. By comparing Figures 4.20 and 4.24, it can be

noticed that in the validation run, the transfer efficiency of the solder paste deposition is

well within the tolerance limits defined for the 0.4 mm pitch SMT connector in section

4.3.

103

Figure 4.24: Range Transfer Efficiency (%) for 0.4 mm pitch SMT connector in validation run

104

4.5 Solder Paste Inspection tolerance limits for 0.4 mm Pitch Quad Flat No-

Leads (QFN) Package

The range of solder paste deposition for the 0.4 mm pitch QFN is shown in Figure

4.24 and the range is expressed in terms of transfer efficiency of the solder paste volume

deposition. The transfer efficiency of the solder paste volume deposition ranged from

42.7% to 123.3%. By correlating the post-reflow inspection of the concerned QFN with

the transfer efficiency of the solder paste deposition, it was found that transfer efficiency

less than 54% lead to ‘insufficient solder’ defect. No solder bridging defects were

observed even for transfer efficiency of 123.3% Therefore, the SPI tolerance limits for

the concerned 0.4 mm pitch QFN is set as 55%-120% of the stencil aperture volume. The

decision on tolerance limits for solder paste deposition is determined by analyzing more

than 5000 data points. The data points are obtained from solder paste deposition on 450

PCBs for the concerned QFN. As the data points are part of different production runs, the

graph shown in Figure 4.24 is a bit bi-modal.

105

Figure 4.25: Range of Transfer Efficiency (%) for 0.4 mm pitch QFN Package

Figure 4.26: Range of Transfer Efficiency (%) for 0.4 mm pitch QFN Package in validation run

106



on 42 boards of Test Vehicle1, which includes the concerned 0.4 mm pitch SMT



noticed that the range of transfer efficiency of solder paste deposition is well within the

tolerance limits defined for the 0.4 mm pitch QFN in section 4.4

4.6 Solder Paste Inspection tolerance limits for 0.5 mm pitch surface mount

connector

The range of solder volume deposition for the 0.5 mm pitch SMT connector is

shown in Figure 4.27, and it is expressed in terms of transfer efficiency of the solder

paste volume deposition. The range of transfer efficiency leading to defects is also shown

in Figure 4.27. The transfer efficiency of the solder paste volume deposition ranged from

63.6% to 176.6%. By correlating the post-reflow inspection of the concerned connector

with the transfer efficiency of the solder paste deposition, it was found that transfer

efficiency less than 68% lead to ‘insufficient solder’ defects and solder volume

deposition more than 137% resulted in ‘solder bridge’ defects. Therefore, SPI tolerance

limits for the concerned 0.5 mm pitch SMT connector is set as 70%-135% of the stencil

aperture volume. The decision on tolerance limits for solder paste deposition is

determined by analyzing more than 6700 data points, which is obtained from 268 PCBs

that are part of different production runs. Data collected from different production runs is

the reason behind bi-modal nature of graph shown in Figure 4.27.

107

Figure 4.27: Range of Transfer Efficiency (%) for 0.5 mm pitch connector

Figure 4.28: Range of Transfer Efficiency (%) for 0.5 mm pitch connector in validation run

108



on 42 boards of Test Vehicle1, which consists of the concerned 0.5 mm pitch SMT



noticed that the range of solder volume deposition is well within the tolerance limits

defined for the 0.5 mm pitch SMT connector in section 4.5.

4.7 Solder Paste Inspection tolerance limits for 0.5 mm pitch Quad Flat No-

Leads (QFN) Package

The range of solder volume deposition for the 0.5 mm pitch QFN is shown in

Figure 4.29 and it is expressed in terms of transfer efficiency of the solder paste volume

deposition. The range of transfer efficiency leading to defects is also shown in Figure

4.29. The transfer efficiency of the solder paste volume deposition ranged from 48% to

135%. By correlating the post- reflow inspection of the concerned connector with the

transfer efficiency of the solder paste deposition, it was found that transfer efficiency less

than 50% resulted in ‘insufficient solder’ defects and transfer efficiency more than 130%

showed solder bridging defects. Therefore, the SPI tolerance interval for the concerned

0.5 mm pitch SMT connector is set as 50%-130% of the stencil aperture volume. The

decision on tolerance limits for solder paste deposition is determined by analyzing more

than 10000 data points. The data points are obtained from solder paste deposition on 402

PCBs for the concerned connector.

109

Figure 4.29: Range of Transfer Efficiency (%) for 0.5 mm pitch QFN

Figure 4.30: Range of Transfer Efficiency (%) for 0.5 mm pitch QFN in validation run

110



on 42 boards of Test Vehicle1, which consists of the concerned 0.4 mm pitch QFN. The

range of transfer efficiency (%) obtained by using the new print parameters is shown in

Figure 4.30.

4.8 Validation of the Solder Paste Inspection tolerance limits

The SPI tolerance limits that are determined in sections 4.2 to 4.7 are statistically

validated in this section. The methodology followed for validating SPI tolerance limits

for the 0.4 mm pitch PoP is explained below:

The SPI tolerance limits for the concerned PoP are determined as 40%-130%.

The probability of getting a solder paste deposition less than 40%, defined as

P(X<=40), was obtained by using the mean, the standard deviation (both are

shown in Figure 4.10) and the normal distribution table.

The number of estimated insufficient failures is calculated by multiplying

P(X<=40) with the total number of data points used for constructing the

histogram shown in Figure 4.10.

The estimated insufficient failure count is then compared with observed

insufficient failure count, which is obtained from the post-reflow inspection.

A similar approach was adopted for validating the SPI tolerance limits found for the

remaining four packages, and the validation results are summarized in Table 4.2.

111

Table 4.2: Validation of the Solder Paste Inspection tolerance limits

Following conclusions can be drawn the Table 4.2

The number of estimated failure count is close to the number of observed

insufficient failure count for all packages

Hence the solder paste inspection tolerance limits determined for each package

are statistically validated

112

4.9 2525 Surface Mount Passive

As explained in section 3.3.6, a 2525 surface mount passive package is included

in this research to show that while assembling components that have solderability

problems, even solder paste deposition within tolerance limits cannot avoid defects such

as non-wetting or open joint.

4.9.1 Solderability test on the components

Solderability test was performed on the concerned components. The solderability

test was evaluated as per IPC/JEDEC J- STD- 002C Test A1, B1 and G1 Solderability

Tests for Components Leads, Terminations, Lugs, Terminals, and Wires. Pass condition

was set to the minimum standard of acceptability where wetting action should be evident

within 5 seconds of the component coming in contact with molten solder. IPC type

Actiec 5 Flux was used as a part of the solderability test. The solderability test was

performed at Sanmina-SCI Failure Analysis Lab

Solderability test results have shown that the leads were difficult to wet and did

not achieve natural buoyancy before 5 seconds. The results indicate that either the

materials or surface of the contacts do not wet to a minimally acceptable standard.

Experimentally, to characterize the wetting force versus time, the test time was extended

to 30 seconds, the immersion depth of the terminations was increased to 3x the standard

depth (0.1mm), and the solder temperature was increased to 2650C. Figures 4.31 – 4.36

corresponds to solderability test performed on the concerned connectors. Figure 4.31

shows components of date code 1402, as they are received from the stock room. Figure

4.32 display the typical appearance of the same components after 5 seconds immersion

113

dip and look test. Figure 4.33 shows components of date code 1348, as they are received

from the stock room. Figure 4.34 display the typical appearance of the same components

after 5 seconds immersion dip and look test.

114

Figure 4.31: DC 1402 component as received from stock

Figure 4.32: Typical appearance of DC1402 after 5 seconds immersion dip and look test

Figure 4.33: DC 1348 component as received from stock

Figure 4.34: Typical appearance of DC 1348 after 5 seconds immersion dip and look test

115

Figure 4.35: Solderability test report on DC 1402 of the concerned component (Source: Sanmina)

116

Figure 4.36: Solderability test report on DC 1348 of the concerned component (Source: Sanmina)

117

4.9.2 Results of DOE 3

The methodology of performing DOE 3 is explained in detail in section 3.6.3. The

experimental design for DOE3 is shown in Appendix A5.

A five factor General Linear Model (GLM) with two replications that accounts to

32 runs (25= 32) was conducted as a part of this DOE. After the reflow, the solder joints

were subjected to the shear test on an “Instron Model 4450”. The size of anvil used was

0.5 inches wide, and the strain rate is 0.25 mm/second. The peak force required to shear

off the component solder joints is considered as the response variable for this experiment.

Following are some observations noticed from DOE 3:

The minimum peak force required to shear off the solder joint was 27.4 lbs

(Please refer to Appendix A5)

An ANOVA analysis describes the influence of controllable factors on results.

Considering all 5 factor effects shown in Figure 4.36, ‘paste addition’ is a

significant factor with P value =0.012 at 95% confidence.

Main Effects Plot for Peak Force shown in Figure 4.37, shows that the Profile

factor is not contributing to the variation. Eliminating profile as a factor changes

the model and lets us re-evaluate the interaction effects in a better way.

From Figures 4.39, paste addition is a significant with P value = 0 at 95%

confidence.

Adding solder paste is a significant factor that affects the strength of the solder

joint.

118

Figure 4.37: ANOVA for 5 factor model in DOE 3

Figure 4.38: Main Effects Plot for Peak Force

119

Figure 4.39: ANOVA for 4 factor model in DOE 3

Figure 4.40: 4 Factor Interaction Plot in DOE 3

120

Chapter 5: Summary and Future Scope

The usage of miniature packages in SMT has created opportunities for

manufacturing complex assemblies in much less real estate. However, the assembly of

such small packages has posed many challenges to the electronics assembly industry.

Several studies have also pointed out that effective inspection of solder paste deposition

is crucial for increasing productivity and for reducing rework. To increase their first pass

yield and to eliminate rework as a bottleneck, several electronics manufacturers are using

in-line SPI machines to inspect the quality of solder paste deposition.

To aid in this inspection, it has been observed that the pre-determination of

tolerance limits for specific types of parts would be helpful tool, and too often has been

ignored as a part of the inspection process.

5.1 Summary of Research

This research endeavor is divided into two stages. The first stage is focused on

determination of SPI tolerance limits for fine pitch packages. As a result of this work, the

SPI tolerance limits were determined for fine pitch packages that will be assembled onto

PCBs that have Non Solder Mask Defined (NSMD) pads with an electroless nickel

121

immersion gold surface finish. Lead-Free, No Clean, SAC 305 alloy, Type 4 solder paste

was used for the assembly of the concerned, fine pitch packages. Feedback from post-

reflow inspection of assemblies was used to determine effective, statistically significant

SPI tolerance limits.

The second stage is focused on finding optimal print parameters that will help to

obtain solder paste deposition within the defined tolerance limits for each of the fine pitch

packages considered in fist stage.

As a secondary objective beyond the determination of SPI tolerance limits and

finding optimal print parameters, this research was also focused on optimization of the

stencil design for a 0.4 mm pitch Package on Package (PoP). This was to avoid solder

bridge defects in the center row of the package and to compensate for warpage at the

corner of the package. A detailed description of the methodology adopted for stencil

design optimization is provided in Section 3.3.1. The results of the stencil design

optimization are included in Section 4.2.1.

Throughout this research, it has been reiterated that a SPI machine with

appropriate tolerance limits would help in identifying and preventing defects related to

solder paste printing. However, while assembling components that have solderability

problems, even solder paste deposition within tolerance limits cannot avoid defects such

as a non-wetting or an open joint. The research work done on a 2525 surface mount

passive that is described in section 4.7 shows that while assembling parts that have

solderability problems, dispensing additional solder paste is a significant factor that

affects the strength of the solder joints. However, adding additional solder paste just

122

masks the problem but does not address the root cause of the issue. Although the solder

joints achieved through such process are conductive at time zero, they are susceptible to

fail in the field. So it is suggested not assemble parts that have oxidation problems.

The SPI tolerance limits determined in this research are summarized in Table 5.1.

In Table 5.1, T.E stands for Transfer Efficiency; Std. Dev stands for Standard Deviation;

ENIG stands for Electroless Nickel Immersion Gold pad surface finish, and NSMD stand

for Non Solder Mask Defined pad layout.

123

Table 5.1: Summary of Solder Paste Inspection Tolerance Limits

124

5.2 Future Research

This research endeavor demonstrated a methodology to correlate post-reflow

inspection with SPI and determine tolerance limits for the inspection. Chris, et al. (2011),

suggest to set the initial tolerance limits as 50% - 150% of theoretical volume and then

use post-reflow inspection feedback to fine tune the tolerance limits for each package

accordingly. The tolerance limits shown in Table 5.1 can be used as a starting point for

inspecting the concerned packages. However the proposed tolerance limits are limited to

assemblies using Type 4, Lead-Free No Clean Solder Paste with NSMD pad layout and

ENIG pad surface finish. The spread of the solder paste varies with different chemistries

and pad surface finish (Zheng, 2010). Some of the ideas for future research work are

listed below.

SPI tolerance limits for height, area and print misregistration for different fine

pitch packages can be studied.

Determination of SPI tolerance limits for different fine pitch packages assembled

using different leaded/lead-free solder paste formulations can be studied.

The effect of rigid/flex board warpage on SPI can be assessed.

The methodology used for determining SPI tolerance limits and finding optimal

print parameters can be used for different complex assemblies and achieve

significant yield improvements.

In light of growing dependence upon solder paste inspection, there is a need for

improved inspection algorithms which can lead to faster and more accurate

inspection of PCBs.

125

Research the possibility of establishing a closed loop, “real time” approach

including the solder paste printing, solder paste inspection, and post-reflow

inspection processes. The aim of such a closed loop system should be automated

on line adjustment of solder paste printing parameters and SPI tolerance limits.

126

Appendix

Appendix A1: Standoff heights obtained from cross sectional analysis

Data Point Z Measured (mm) X co-ordinate (mm) Y co-ordinate (mm)

1 0.1849 -5.4 1.8

2 0.1833 -5 1.8

3 0.1792 -4.6 1.8

4 0.1756 -4.2 1.8

5 0.1578 -2.6 1.8

6 0.1515 -2.2 1.8

7 0.1491 -1.8 1.8

8 0.1458 -1.4 1.8

9 0.1457 -1 1.8

10 0.1410 -0.6 1.8

11 0.1449 -0.2 1.8

12 0.1409 0.2 1.8

13 0.1435 0.6 1.8

14 0.1402 1 1.8

15 0.1468 1.4 1.8

16 0.1484 1.8 1.8

17 0.1520 2.2 1.8

18 0.1590 2.6 1.8

19 0.1767 4.2 1.8

20 0.1832 4.6 1.8

21 0.1888 5 1.8

22 0.1917 5.4 1.8

127

Appendix A2: Experimental Setup for DOE1

Std

Order

Run

Order

Center

Pt Blocks

Squeegee

Pressure

(kgf)

Squeegee

Speed

(mm/sec)

Snap

off

Print

Stroke

Transfer

Efficiency

3 1 1 1 2 40 On 1 0.8

27 2 1 1 2 40 On 2 0.76

6 3 1 1 3.5 25 Off 1 0.649

4 4 1 1 3.5 40 On 1 0.62

1 5 1 1 2 25 On 1 0.67

29 6 1 1 2 25 Off 2 0.709

23 7 1 1 2 40 Off 1 0.57

13 8 1 1 2 25 Off 2 0.764

11 9 1 1 2 40 On 2 0.66

14 10 1 1 3.5 25 Off 2 0.75

9 11 1 1 2 25 On 2 0.779

19 12 1 1 2 40 On 1 0.604

24 13 1 1 3.5 40 Off 1 0.64

22 14 1 1 3.5 25 Off 1 0.692

28 15 1 1 3.5 40 On 2 0.75

25 16 1 1 2 25 On 2 0.69

8 17 1 1 3.5 40 Off 1 0.627

16 18 1 1 3.5 40 Off 2 0.68

12 19 1 1 3.5 40 On 2 0.77

26 20 1 1 3.5 25 On 2 0.67

32 21 1 1 3.5 40 Off 2 0.68

17 22 1 1 2 25 On 1 0.697

18 23 1 1 3.5 25 On 1 0.56

2 24 1 1 3.5 25 On 1 0.66

15 25 1 1 2 40 Off 2 0.63

20 26 1 1 3.5 40 On 1 0.71

10 27 1 1 3.5 25 On 2 0.77

5 28 1 1 2 25 Off 1 0.64

31 29 1 1 2 40 Off 2 0.79

7 30 1 1 2 40 Off 1 0.638

30 31 1 1 3.5 25 Off 2 0.57

21 32 1 1 2 25 Off 1 0.626

128

Appendix A3: Experimental Setup for DOE1-1

StdOrder RunOrder PtType Blocks

Squeegee

Pressure

(kgf)

Snap

Off

Transfer

Efficiency

8 1 1 1 2.5 2 0.74

3 2 1 1 1.5 3 0.76

2 3 1 1 1.5 2 0.73

1 4 1 1 1.5 1 0.73

9 5 1 1 2.5 3 0.75

7 6 1 1 2.5 1 0.68

5 7 1 1 2 2 0.71

4 8 1 1 2 1 0.737

6 9 1 1 2 3 0.74


Std

Order

Run

Order

Center

Pt Blocks

Squeegee

Pressure

(lbs/sq.inch)

Squeegee

Speed

(inches/se

c) Snap off Wipe Frequency

Transfer

Efficiency

2 1 1 1 12 0.8 Standard Alternate Board 85.64

14 2 1 1 12 0.8 Stepped Every Board 104.05

4 3 1 1 12 1 Standard Alternate Board 92.6

3 4 1 1 10 1 Standard Alternate Board 80.45

1 5 1 1 10 0.8 Standard Alternate Board 90.18

16 6 1 1 12 1 Stepped Every Board 107.5

11 7 1 1 10 1 Standard Every Board 95.52

7 8 1 1 10 1 Stepped Alternate Board 79.82

6 9 1 1 12 0.8 Stepped Alternate Board 86.3

8 10 1 1 12 1 Stepped Alternate Board 76.52

5 11 1 1 10 0.8 Stepped Alternate Board 94.25

9 12 1 1 10 0.8 Standard Every Board 102.11

12 13 1 1 12 1 Standard Every Board 105.43

10 14 1 1 12 0.8 Standard Every Board 93.61

15 15 1 1 10 1 Stepped Every Board 103.39

13 16 1 1 10 0.8 Stepped Every Board 101.2

129


StdOrder Profile DCf Pastef Tinningf Fluxf

Peak

Force

1 Original 1402 Standard NoTin NoFlux 31.48

2 Original 1347-8 Standard NoTin NoFlux 42.36

3 Original 1347-8 Standard NoTin NoFlux 66

4 Original 1402 Standard NoTin NoFlux 36.08

5 Original 1402 AddPaste W/Tin W/Flux 54.76

6 Original 1347-8 AddPaste W/Tin W/Flux 55.25

7 Original 1347-8 AddPaste W/Tin W/Flux 62.01

8 Original 1402 AddPaste W/Tin W/Flux 55.09

9 Original 1402 Standard W/Tin W/Flux 27.54

10 Original 1347-8 Standard W/Tin W/Flux 36.24

11 Original 1347-8 Standard NoTin W/Flux 50.41

12 Original 1402 Standard NoTin W/Flux 32.7

13 Original 1402 AddPaste W/Tin NoFlux 52.76

14 Original 1347-8 AddPaste W/Tin NoFlux 49.77

15 Original 1347-8 AddPaste NoTin NoFlux 43.17

16 Original 1347-8 AddPaste NoTin NoFlux 63.46

17 Hotter 1402 Standard NoTin NoFlux 42

18 Hotter 1347-8 Standard NoTin NoFlux 44.24

19 Hotter 1347-8 Standard NoTin NoFlux 42.84

20 Hotter 1402 Standard NoTin NoFlux 34.15

21 Hotter 1347-8 AddPaste W/Tin W/Flux 59.76

22 Hotter 1347-8 AddPaste W/Tin W/Flux 48

23 Hotter 1402 AddPaste W/Tin W/Flux 57.34

24 Hotter 1402 AddPaste W/Tin W/Flux 61.21

25 Hotter 1402 Standard W/Tin W/Flux 38.98

26 Hotter 1347-8 Standard NoTin W/Flux 59.11

27 Hotter 1347-8 Standard W/Tin W/Flux 46.55

28 Hotter 1402 Standard NoTin W/Flux 40.75

29 Hotter 1402 AddPaste W/Tin NoFlux 45.42

30 Hotter 1347-8 AddPaste NoTin NoFlux 40.11

31 Hotter 1347-8 AddPaste W/Tin NoFlux 57.5

32 Hotter 1402 AddPaste NoTin NoFlux 38.66

130

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