development of a new-generation rohs igbt module structure

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Transactions of The Japan Institute of Electronics Packaging Vol. 1, No. 1, 2008

Development of a New-Generation RoHS IGBT Module Structure

for Power ManagementYoshitaka Nishimura*, Tatsuo Nishizawa*, Eiji Mochizuki**, Tomoaki Goto**, Yoshikazu Takahashi**

and Shinobu Hashimoto***

*Fuji Electric Device Technology Co., Ltd., 4-18-1, Tsukama, Matsumoto, Japan

**Electron Device Laboratory, Fuji Electric Device Technology Co., Ltd., 4-18-1, Tsukama, Matsumoto, Japan

***Nagoya Institute of Technology Showa-ku, Nagoya, Japan

(Received September 3, 2008; accepted November 25, 2008)

Abstract

This paper describes the design considerations for a high electric power density IGBT module structure mounted with

smaller, new-generation chips. We have investigated heat flow depending on the copper foil thickness of an alumina based

direct-copper-bonding (DCB) substrate, junction temperature rise in relation to the chip arrangement, electromagnetic

noise dominated by the cupper circuit pattern, and lead-free solder layer stress as affected by the coefficient of thermal

expansion (CTE) of DCB.

Low thermal resistance was obtained by using a 0.6 mm thick copper DCB substrate; consequently the CTE of the DCB

increased to 16 ppm/K, which is nearly equal to that of the Cu base as a heat sink. The thick copper DCB substrate can

lower the junction temperature of a small chip with a high electric power density and can improve the thermal cycling

capability of the DCB substrate mounted with a lead-free solder on the Cu base. Moreover the thick copper circuit effec-

tively reduces the electromagnetic noise generated on the DCB substrate. Thus we have successfully realized a high elec-

tric power density IGBT module structure.

Keywords: IGBT Module, Thermal Management, Electromagnetic Noise, Thermal Cycling Capability, Lead Free

Solder

1. IntroductionInsulated gate bipolar transistor (IGBT) modules are

widely used in power electronics applications such as auto-

mobiles and household appliances as well as industry[1] to

realize energy savings with higher efficiency, smaller size,

lower cost, higher reliability, and more environmental

safety from acoustic and electromagnetic noise generation

and lead usage. These various requirements will be satis-

fied not only by creating smaller IGBT chips with superior

performance characteristics, but also by improving the

module structure based on thermal, noise, and environ-

mental management techniques.

Although chip size reduction is an extremely effective

way to realize smaller size and lower cost IGBT modules,

the chip junction-to-case temperature rise, ΔTj-c, becomes

more severe as the size decreases, as in the following

equation:

ΔTj-c = PIGBT × Rth(j-c) (1)

where PIGBT is the power dissipation of the chip and

Rth(j-c) the thermal resistance from junction to case. If the

chip size is decreased, the thermal resistance must be

increased due to an increase in heat density, and then the

junction temperature must be highly elevated even to

maintain the same power dissipation as that of a large size

chip.

A field-stop junction structure on the back-surface, com-

bined with a trench-gate structure on the device surface,

has been shown to reduce power dissipation in smaller

size chips.[2] On the other hand, an improved IGBT mod-

ule structure for such a small, new-generation chip must

be designed based on the following considerations:

a) Reduce thermal resistance, by optimizing a direct-

copper-bonding (DCB) ceramic substrate with thick Cu foils.

b) Reduce noise radiation below the level specified by

the European standard EN61800-3,[3, 4] by optimizing the

P–N current loop area on the DCB substrate.

c) Change from lead-based solder to lead-free solder in

41

order to comply with the European RoHS directive[5]

while maintaining or increasing the thermal cycling capa-

bility.

Thus we have experimentally investigated how the

structural parameters of an IGBT module affect heat,

noise, and reliability. The design considerations men-

tioned above and the experimental results obtained have

been successfully applied to the development of a smaller,

next-generation package structure which can manage an

electrical power density higher than that of a conventional

module.

2. Experimental Procedures2.1 Thermal evaluation

Steady-state thermal resistance analysis was carried out

using FEM analysis (ADINA). Figure 1 shows the thermal

analysis model. An analysis of IGBT chips energized by

80A DC was performed under the following steady state

conditions: chip size of 9.25 mm, DCB ceramic size of 33

× 30 × t0.32 mm, copper circuit area size of 25 × 17 mm,

copper plate thickness of 0.25 mm and 0.6 mm, and copper

base size of 60 × 38 × t3 mm. The thermal conductivity of

the ceramic was changed from 18 to 170 W/m•K.

A heat measurement sample was produced in the same

size as the FEM analysis model. Alumina (thermal conduc-

tivity: 28 W/m•K) and aluminum nitride(thermal conduc-

tivity: 170 W/m•K) were used for the DCB substrate. The

thickness of the copper plate was 0.25 mm and 0.6 mm.

Chip temperature measurements were carried out using

an IR camera (AVIONICS TVS-8500). Carbon was applied

to the measurement side of the sample and the rate of ther-

mal radiation was set to be constant.

Two or more chips are used in an actual IGBT module.

This can be expected to affect the thermal interference

among chips. We therefore investigated the effect of chip

spacing on chip temperature. Figure 2 shows a three-

dimensional FEM analysis model. A steady-state thermal

analysis on IGBT chips energized by 20A DC was per-

formed under the conditions of: chip size of 6.4 mm × 6.4

mm, DCB substrate size of 25 mm × 25 mm, and copper

base size of 35 mm × 3 mm. Chip spacing was changed

from 0.5 mm to 6 mm.

2.2 Noise evaluationRadiation noise was measured using a dipole antenna

(ADVANTEST 3753B) and spectrum analyzer (ADVANTEST

R3261A) at the frequency range of 30 to 230 MHz. The dis-

tance between the dipole antenna and IGBT module was

3 m.

2.3 CTE measurementsThe coefficient of thermal expansion (CTE) of the

copper circuit was measured by a laser displacement

sensor (Keyence:LT-8100) at temperatures between 25°C

and 300°C.

2.4 Thermal cycling testIn thermal cycling tests, an IGBT module was put in a

tank maintained at a constant temperature and the ambient

temperature was changed from –40°C to 125°C .

During thermal cycling, failure was analyzed by non-

destructive observation of the solder joint with a scanning

acoustic microscope (SAM) (the frequency of the ultra-

sonic transducer was a nominal 25 MHz ).

3. Results and Discussion3.1 Heat dissipation design

Figure 3 shows the structure and thermal conductivity

of each component of the IGBT modules (Fuji Electric).

The heat generated at the IGBT chips is conducted

through the insulating ceramic substrate (DCB: Direct

Bonding Copper) and the copper base, and dissipated by

the radiation fins. Table 1 presents the characteristics of

the ceramic used for the DCB substrate.

The thermal conductivity of the ceramic material used

as an insulating layer in the DCB substrate is 18 to 170

W/m•K. Although alumina ceramic has lower thermal

conductivity than aluminum nitride and silicon nitride, it is

less expensive and more ductile; its CTE is closer to that

of the copper base; and because temperature changes dur-

ing operation cause less stress, it improves reliability. Con-

Fig. 1 Thermal analysis model (single chip). Fig. 2 Thermal analysis model (multiple chips).

Nishimura et al.: Development of a New-Generation RoHS IGBT (2/8)

42


sequently, we studied how to improve the heat dissipation

characteristics of IGBT modules made using alumina

ceramic.

The steady-state thermal resistance of a substance is

expressed by:

(2)

where t is the thickness of the substance through which

heat flows, S is the cross-section area through which the

heat passes, and λ is the thermal conductivity of the

substance. Equation (2) suggests that reducing Rth is

essential to improve heat dissipation. Figure 4 shows the

cross-sectional structure and thermal conductivity of the

IGBT modules. Alumina has a higher Rth than copper and

solder because of its lower thermal conductivity, therefore

the thermal conductivity of the ceramic layer is expected

to have a larger effect on the chip temperature. Equation

(2) shows that Rth can be reduced by increasing the cross-

section area S of the ceramic layer which heat passes

through. It may be possible to increase that area S by

increasing the copper circuit thickness as shown in the

drawing on the right in Fig. 2, because heat is conducted

radially from chips. Accordingly, we performed an FEM

analysis by varying the thermal conductivity of the ceramic

layer and the thickness of the copper material, and exam-

ined the relationship between their values and the chip

temperature.

Figure 5 presents the thermal analysis results. With a

copper thickness of 0.25 mm, when the thermal conductiv-

ity of a ceramic substrate is changed from 15 W/m•K to

60 W/m•K chip temperature falls by about 20°C. However,

even if the thermal conductivity of the ceramic is increased

Fig. 3 IGBT module structure and specifications.

Table 1 Characteristics of ceramics used for insulating substrate

Ceramics

Thermalconductivity

W/m•K

Thermalexpansioncoefficient× 10–6/K

Young’smodulus

GPa

Ceramicthickness

mm

Alumina 18 7 360 0.25–0.32

Aluminium nitride 170 4 310 0.635

Silicon nitride 70 3 296 0.32–0.635

Copper 390 16 112 base thickness3

Rth =t

Sλ

Fig. 4 Cross-sectional structure of IGBT modules.

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to 170 W/m•K from 70 W/m•K, chip temperature falls by

only about 4°C. This implies that the thermal conductivity

of the solder also has an effect; the heat resistance layer

changes from the ceramic layer to the solder layer. The

thermal conductivity of solder is 60 W/m•K. Tin is the

main ingredient in lead free solder material, and its ther-

mal conductivity is 68 W/m•K. Thus, we cannot expect a

large improvement in the thermal conductivity of the sol-

der material. Therefore, we conclude that the optimal

value of the thermal conductivity of the ceramic substrate

in a conventional IGBT module structure is 60 W/m•K.

Chip temperature is also reduced by increasing the

thickness of the copper circuit from 0.25 mm to 0.6 mm.

When the thermal conductivity of ceramic substrate is

20 W/m•K, chip temperature is reduced by 10°C. How-

ever, when the thermal conductivity of the ceramic is 170

W/m•K, the fall in chip temperature is about 6°C. This

suggests that thickening the copper circuit has an effect

when the thermal conductivity of the ceramic substrate is

low.

From these results, we would expect a ceramic material

with thermal conductivity of 30 W/m•K and copper circuit

with thickness of 0.6 mm to achieve a chip temperature

equivalent to that of an existing aluminum nitride sub-

strate. Therefore, we performed a thermal assessment

under the same conditions as the FEM analysis, using two

test pieces: one made of alumina ceramic with thermal

conductivity of 28 W/m•K and a copper circuit with a

thickness of 0.6 mm, and the other made of aluminum

nitride ceramic with thermal conductivity of 170 W/m•K

and a copper circuit with a thickness of 0.25 mm.

Figure 6 shows the temperature distribution on the chip

surface after being energized by 80A DC for 5 minutes. By

increasing the thermal conductivity of the alumina ceramic

material to 28 W/m•K and the copper circuit thickness to

0.6 mm, the difference in temperature between the new

chip and the AIN substrate was decreased by approxi-

mately 3 degrees. This value is almost the same as the

value calculated by the FEM analysis shown in Fig. 5.

Packaging density has increased in recent years, with one

package containing plural IGBTs in actual IGBT modules.

This is expected to affect the thermal interference among

chips, so we investigated the effect of chip spacing on chip

temperature. Figure 7 shows the chip spacing and tem-

perature distribution and Fig. 8 shows the relationship

between the chip spacing and maximum chip tem-

peratures. These figures show that as the chip spacing

becomes smaller, the chip temperature rises. The temper-

ature distribution conditions in Fig. 7 show that at the cen-

ter of the products with chip spacing of 0.5 mm or 2 mm,

the chip edges have the maximum temperature and their

thermal interferences are high. This means that there is a

trade-off between lower chip temperature and higher pack-

aging density. The temperature distribution on the chip

surface should be made as even as possible because an

uneven temperature distribution may cause thermal run-

away or decrease reliability. Since the central part of the

chips reaches the maximum temperature in products with

chip spacing of 4 mm or more and the thermal interference

of the chips is smaller, products with higher density

mounting should be designed with a chip spacing of at

least 4 mm.

Based on the above results, we optimized the new pack-

age to consider the effect of thermal interference. Figure 9

compares the results of the FEM analysis for the temper-

ature distributions of the conventional and new packages.

Fig. 5 Relationship between thermal conductivity of ceramic,copper circuit thickness, and chip temperature.

Fig. 6 Chip temperature (steady state).


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In the conventional package, since the IGBT chips are con-

centrated near the center of the package, the temperature

of the central part of the chips is higher. On the other

hand, the new package with optimal chip layout and chip

spacing provides an almost even temperature distribution

and its Tj was reduced by up to 10°C.

3.2 Noise characteristicsAn inverter must be designed so that the level of noise

radiation in the frequency range of 30 MHz to 1 GHz con-

forms to certain standards. It has been reported that oscil-

lation from a resonant closed loop circuit between IGBT

module and snubber circuit constitutes a radiation source

and is a mechanism by which noise radiation is generated

in this frequency region.[6] Maxwell’s equation for a dis-

tant field is expressed as:

E = 1.32 × 10–14 × f2 × S × I/r (3)

where f is the frequency, I is current, S is current loop

area, and r is distance; a distant field is dependent on the

current closed loop area of the snubber circuit and switch-

ing element. Accordingly, in order to reduce the P–N cur-

rent loop area inside the package, we improved the DCB

copper circuit pattern wiring configuration, and studied not

only element characteristics in the conventional way, but

also the package itself for the purpose of reducing noise.

Figure 10 shows the P–N current loop areas of the conven-

tional and new package structures. We designed the new

package so that the P–N current loop area was reduced by

50% compared to the conventional package. Figure 11

gives the noise radiation results. The peak value of the

noise radiation was reduced by approximately 5 dB. Con-

sequently, the turn-on speed can be increased further,

which is expected to reduce switching loss.

3.3 RoHS-compliant IGBT module structureLead solder is used in IGBT modules, mainly as a solder

material. Major technical challenges in changing to lead-

free solder are ensuring reliability after changing the

solder material, and the higher temperature of devices

mounted with lead-free solders.[7] To address the higher

temperature of mounted devices, we changed the material

to increase the heatproof temperature and also changed

the mounted device. Solder material is used in the follow-

Fig. 7 Temperature distribution of various chip spacing con-figurations.

Fig. 8 Relationship between chip spacing and chip tempera-ture.

Fig. 9 Comparison of temperature distribution by FEM anal-ysis.

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ing parts in IGBT modules: (1) IGBT chips, joining areas

of the copper circuit and (2) DCB substrate, joining areas

of the copper base. As for (1), Fuji Electric has been using

lead-free solder[8] since 1998 and has succeeded in

improving power cycle reliability.[9] In this new package,

we developed a DCB substrate that complies with the lead-

free requirement. As shown in Fig. 1, there is a major dif-

ference in the CTEs of the ceramic material and copper

base used in the DCB substrate. Consequently, the stress

in the solder layers is concentrated during the heat cycle,

causing fracture. In order to reduce stress, we propose a

method for making a small CTE difference by using Cu–

Mo, ALSIC,[10] and Cu–Cu2O[11] in the DCB substrate.

These composite materials have low thermal conductivity

and high cost as compared with copper. Therefore, they

are used only for hybrid vehicles and electric railroad

equipment that need high reliability. We investigated the

CTE of a DCB substrate close to copper. The horizontal

CTE in the complex which is a three-layer composite

material of copper/ceramic/copper-like ceramic insulation

board is expressed as the following equation.

(4)

where α1 is the ceramic CTE, t1 is ceramic thickness, E1

is the ceramic Young’s module, α2 is the copper CTE , t2

is copper circuit thickness, and E2 is the copper Young’s

module.

Equation (4) and Table 1 show that increasing copper

circuit thickness t2 can increase the CTE of DCB sub-

strate. The copper thickness was evaluated for its impact

on the CTE on the DCB substrate surface.

Figure 12 shows the results of measuring the CTE of the

copper circuit surface with the alumina ceramic material

(t = 0.32 mm) and copper circuits of various thicknesses.

The CTE of the DCB substrate surface with a copper cir-

cuit of 0.25 mm was almost the same as that of alumina, 7

× 10–6/K. By increasing the copper circuit thickness to 0.4

mm, the CTE of the DCB substrate surface was increased

to 10 × 10–6/K.

This result shows that the difference in the CTEs of the

copper circuit surface of the DCB substrate and the copper

base can be decreased by increasing the copper circuit

thickness to more than its usual value, 0.25 mm.

We performed thermal cycle tests on the samples with

a copper circuit thickness of 0.5 mm at temperatures rang-

ing from –40°C to 120°C. Figure 13 shows the test results.

In the conventional DCB substrates, cracks of approxi-

mately 1.5 mm occurred after 1000 cycles, whereas in the

sample with a copper circuit thickness of 0.5 mm, no

cracks were observed after 1000 cycles. This result shows

that the resistance characteristics in the heat cycle test are

improved by increasing the copper circuit thickness.

Since a thicker solder means that less stress is gener-

ated per unit of thickness, the solder thickness underneath

the DCB substrate is specified in order to ensure reli-

ability. The results in Fig. 13 show that reliability was

Fig. 10 Internal layout with lower noise.

Fig. 11 Comparison of noise radiation.a)conventional package structure; b)new package structure.

α αα α

=t E

(t E t E2 2

1 1 2 21

2 1+ −+

( ))


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improved by increasing the copper circuit thickness.

We investigated the reliability of conventional packages

and new packages in which solder thickness was reduced

to two-thirds that of the conventional products. Figure 14

shows the thermal cycling test results. Solder cracks occ-

urred at the corner of the conventional package after 300

cycles, whereas no cracks were observed in the new pack-

age in which the copper circuit thickness was increased to

0.6 mm. These results confirm the amount of lead-free

solder in the new package can be reduced to two-thirds of

that in conventional products.

4. ConclusionWe have investigated a new IGBT module structure for

power management, considering heat dissipation, electro-

magnetic noise reduction, and environmental resistance

such as higher thermal cycling capability, with lead-free

soldering. The design can reduce junction temperature to

almost the same value as that on an aluminum nitride

substrate by increasing the copper circuit thickness of

the DCB substrate to 0.6 mm in thickness and by improv-

ing the thermal conductivity of the alumina material to

28 W/m•K. Moreover, we investigated the effect of the

chip layout on thermal interference and confirmed the

most effective chip mount spacing is 4 mm or more.

In the experiments, we confirmed a reduction of 10

degrees in the junction temperature, good performance in

thermal cycling capability, and a 5 dB noise reduction due

to a decrease of 50% of the P–N current loop area of Cu foil

circuit, compared with the conventional package structure.

Thus we have successfully developed a new IGBT package

structure using a lead-free solder by increasing the copper

circuit thickness on the alumina based-ceramic substrate.

References

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Fig. 12 Relationship between copper circuit thickness andCTE.

Fig. 13 Relationship between copper circuit thickness andresistance characteristics in heat cycle test.

Fig. 14 Temperature cycle test results after 300 cycles: solder thickness was two-thirds of that used in conventional products.

47

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development of a new-generation rohs igbt module structure

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