device research conference 2006 erik lind, zach griffith and mark j.w. rodwell department of...
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Device Research Conference 2006
Erik Lind, Zach Griffith and Mark J.W. RodwellDepartment of Electrical and Computer EngineeringUniversity of California, Santa Barbara, CA, 93106-9560, USA
Xiao-Ming Fang, Dmitri Loubychev, Ying Wu, Joel M. Fastenau, and Amy LiuIQE Inc. 119 Bethlehem, PA 18015, USA
[email protected], 805-893-3273, 805-893-3262 fax
250 nm InGaAs/InP DHBT with 650 GHz fmax and 420 GHz ft,
operating above 30 mW/μm2
InP/InGaAs Double Heterostructure Bipolar Transistor
• Mesa DHBTs for high speed applications
•Abrubt InP-InGaAs emitter base junction•InGaAs base provides good hole mobility•Setback and Grade used for BC junction
•InP collector
Subcollector
•Base
Emitter
Collector
S.I. InP
• Objective: Improve DHBT performance by lateral scaling of emitter-base junction!
Fast bipolar transistors
0
100
200
300
400
500
600
700
800
0 100 200 300 400 500 600 700 800
RSC
UIUC DHBT
NTT
Fujitsu HEMT
SFU
UIUC SHBT
UCSB
NGST
Pohang
HRL
IBM SiGe
Vitesse
f ma
x (G
Hz)
ft (GHz)
500 GHz400 GHz300 GHz200 GHz maxff
Updated June 2006
600 GHz
UCSB 0.25μm
UCSB 0.6μm
Standard figures of merit / Effects of Scaling
Small signal current gain cut-off frequency (from H21)
bccexbcjec
Bcb CRRCC
qI
Tnk
f
2
1
icbCR
ff
bb ,8max
VI
C
c
cb
Charging time for digital logic
•Power gain cut-off frequency (from U)
Thinning epitaxial layers (vertical scaling) reduces base and collector transit times… But increases capacitances
Increase current density and reduce resistances.
Reduce Rbb and Ccb,i through lateral scaling
Higher Jkirk, dimished self-heating due to current increased current spreading
Fabrication I – Epitaxial Stack: 150 nm Collector
Title
Thickness (nm) Material Doping cm-3 Description
5 In0.85Ga0.15As 51019 : Si Emitter cap
15 InxGa1-xAs > 41019 : Si Emitter cap grading
20 In0.53Ga0.47As 41019 : Si Emitter
80 InP 31019 : Si Emitter
10 InP 81017 : Si Emitter
40 InP 81017 : Si Emitter
30 InGaAs 7-41019 : C Base
15 In0.53Ga0.47 As 3.51016 : Si Setback
24 InGaAs / InAlAs 3.51016 : Si B-C Grade
3 InP 2.751018 : Si Pulse doping
108 InP 3.51016 : Si Collector
5 InP 11019 : Si Sub Collector
6.5 In0.53Ga0.47 As 21019 : Si Sub Collector
300 InP 21019 : Si Sub Collector
Substrate SI : InP
• 150 nm collector
• 30 nm base, graded carbon doping
• Thin, 6.5nm InGaAs subcollector
•High fmax device with moderate fτ
• High Vceo
• Investigate Jmax increase due to improved thermal capabilities and current spreading – increase in fτ
-2
-1
0
1
2
100 150 200 250 300 350 400
Ene
rgy
(eV
)
Position (nm)
Vbe
=0.9V
Vcb
=0.6V
Grade
Setback
Emitter Base Collector
Sub-collector
Fabrication II – Lateral Scaling
Fabrication Details:
• I-line optical lithography
• All wet etch, lift-off based process
• 250 nm emitter / base junction
• Reduction in Cbc by removing semiconductor under base pad
• BCB passivation
DHBT before BCB passivation Emitter Metal Removed
Base contact
Emitter Mesa
We=250 nm
Base contact
Emitter Contact
We=400nm
RF and DC performance
• Summary of device parameters—
• Average 25, VBR, CEO ~ 5 V (@ 1kA/μm2)
• fmax=650 GHz
• ft=420 GHz
• Operates at power densities above 30mW/μm2
0
5
10
15
20
0 1 2 3 4 5 6
J e (m
A/
m2 )
Vce
(V)
Ajbe
= 0.25 x 2.1 m2
Ib step
= 100 uA
Peak ft, f
max
30 mW/m2
10-12
10-10
10-8
10-6
10-4
0.01
0 0.2 0.4 0.6 0.8 1
I b, I c (
A)
Vbe
(V)
VCB
= 0.0 V
Ic
Ib
nc = 1.15
nb = 1.6
Ajbe
= 0.5 x 7.1 m2
0
5
10
15
20
25
30
35
109 1010 1011 1012
Gai
ns
(dB
)
Frequency (Hz)
ft = 420 GHz, f
max = 650 GHz
U
H21A
jbe = 0.25 x 3.1 um2
Ic = 9.0 mA, V
ce = 1.58 V
Je = 12.0 mA/um2, V
cb= 0.6 V
MSG/MAG
650 GHz
420 GHz
Vceo
ft, fmax and CCb variation
0.0
100.0
200.0
300.0
400.0
500.0
600.0
700.0
0 3 6 9 12 15
f max
(G
Hz)
Je (mA/m2)
Vcb
=-0.3V
Aje = 0.25 x 3.1 m2
0.0V
0.2V
0.6V
0.4V
0.0
100.0
200.0
300.0
400.0
500.0
0 3 6 9 12 15
f t (G
Hz)
Je (mA/m2)
Vcb
=-0.3V
Aje = 0.25 x 3.1 m2
0.0V
0.2V
0.6V
• Jkirk 12 mA/μm2 (@ Vcb=0.6V)
• Limited by collector doping and thermal effects
• Ccb/Ic=0.30 pS
ft fmax
Aje
= 0.25 x 3.1 m2
Vcb
= -0.3 V
2
4
6
8
10
12
0 4 8 12 16
2
3
4
5
6
7
8
9
Ccb
/Aje (
fF/
m2 )
Je (mA/m2)
Ccb (fF
)
0.0 V
0.2 V
Vcb
= 0.6 V, A
jc= 1 x 5 m2
0.4 V
Cbc
Small signal equivivalent circuit at maximum ft, fmax
Summary resistive elements
• Emitter contact (from RF extraction), Rcont 5.0 m2
• Base (from TLM) : Rsheet = 635 /sq, Rcont < 5.0 m2
• Collector (from TLM) : Rsheet = 12.7 /sq, Rcont = 10.0 m2
freq (1.000GHz to 67.00GHz)
S22
dS
11d
S21
d/20
S12
d*5
_403
_610
GH
z_ex
trac
tion_
revi
sed.
.S(1
,1)
_403
_610
GH
z_ex
trac
tion_
revi
sed.
.S(1
,2)*
5_4
03_6
10G
Hz_
extr
actio
n_re
vise
d..S
(2,1
)/20
_403
_610
GH
z_ex
trac
tion_
revi
sed.
.S(2
,2)
S21/20S12x5
S11 S22
Ccb,ex= 2.34 fF
Rcb= 55 k
Ccb,ex= 0.96fFRbb= 45.5
Rbe= 110
Rex= 6.7
Rc= 1.5
Collector
Emitter
Base
Cje+Cdiff= 27.3+56 fF
gme-jf
0.20e-j0.29pS
1-67 GHz Aje=0.253.1μm2
Ic=9mA
Vce=1.56V
• Total delay time: 1/2πfτ= 0.38 pS
• Base and collector transit times = 0.29pS
• Terms related to Ccb = 38 fS
• Larger bandwidth through vertical scaling
Breakdown mechanism for Type-I InP DHBTs
10-9
10-8
10-7
10-6
10-5
10-4
-1 0 1 2 3 4 5 6
Aje=0.45x7.1m2, A
jc=1.4x10.1m2
|Ib
as
e|
Vcb
Ie=120A
Ie=5.6A
Ie=250nA
Ib=Ib(Vcb=0) - (M-1) αIe – Izener
• Breakdown essentially set by tunneling through setback region
• BVceo ~ 5V
• Proper design of setback and grade is needed for vertical scaling of the collector
zenercbb IIMII 10
-2
-1.5
-1
-0.5
0
0.5
1
1.5
100 150 200 250
Energ
y (e
V)
Position (nm)
Vbe
=0.9V
Vcb
=5.1V
EmitterInP
BaseInGaAs
Grade
SetbackInGaAs
10-3
10-2
10-1
100
101
102
103
0 1 2 3 4 5 6
I cbo (
A/c
m2 )
Vcb
(V)
Simulation
Ajc = 1.5 x 10 m2
Measured Data
Impact Ionization
Band to band tunneling
Comparison with 0.6μm 150nm Tc UCSB DHBT
0
5
10
15
20
25
30
35
109 1010 1011 1012
Gai
ns
(dB
)
Frequency (Hz)
ft = 391 GHz, f
max = 505 GHz
U
h21
Ajbe
= 0.6 x 4.3 um2
Ic = 13.2 mA, V
ce = 1.54 V
Je = 5.17 mA/um2, V
cb= 0.6 V
200
300
400
500
1 2 3 4 5 6
GH
z
Je (mA/um2)
ft
fmax
Vcb
= 0.6 V
• Emitter Width – 0.6 m
• Emitter contact - Rcont 10.1 m2
• Base Contact - Rcont 9.6 m2
• Jkirk ~ 5.5 mA/m2 (Pmax ~ 15 mW/m2)
• f / fmax = 391,505 GHzGriffith et al., IEEE Electron Device Letters, Vol. 26, Jan 2005
2004 2006
• Emitter Width – 0.25 m
• Emitter contact - Rcont 5.0 m2
• Base Contact - Rcont < 5.0 m2
• Jkirk ~ 12 mA/m2 (Pmax ~ 30 mW/m2)
• f / fmax = 420,650 GHz
0
5
10
15
20
25
30
35
109 1010 1011 1012
Ga
ins
(dB
)
Frequency (Hz)
ft = 420 GHz, f
max = 650 GHz
U
H21A
jbe = 0.25 x 3.1 um2
Ic = 9.0 mA, V
ce = 1.58 V
Je = 12.0 mA/um2, V
cb= 0.6 V
MSG/MAG
0
5
10
15
20
0 1 2 3 4 5 6
J e (m
A/
m2 )
Vce
(V)
Ajbe
= 0.25 x 2.1 m2
Ib step
= 100 uA
Peak ft, f
max
30 mW/m2
Comparison with SHBT and GaAsSb technologies
• Type I InP DHBTs combines high f / fmax with high power densities and breakdown voltages
• InP SHBTs (utilizing InGaAs collector) have very high ft and fmax, but low breakdown voltages.
• InP Type-II DHBTs (InP/GaAsSb/InP) have high breakdown, but fmax is low due to base resistance.
InP SHBT—InGaAs base and collector (55nm)
Type-II DHBT—GaAsSb base, InP collector (150nm)
H.G. Liu et al., IEEE TED, Vol. 53, No. 3, 2006
W. Hafez et al., APL, Vol. 87, 2006
f / fmax = 710 / 340 GHz Type-I DHBT—InGaAs base, InP collector, ternary B-C grading
f / fmax = 420 / 650 GHz
f / fmax = 380 / 250 GHz
BVceo ~ 1.75V
Parameter scaling law
Gen. 2 Gen. 3 Gen. 4
MS-DFF speed 158 GHz 230 GHz 330 GHz
Emitter Width 1/ 500 nm 250 nm 125 nm Resistivity 1/ 15 -m2 7.5 -m2 5 -m2
Base Thickness 1/ 300Å 250 Å 212 Å Doping 7 1019 /cm2 7 1019 /cm2 7 1019 /cm2 Sheet resistance 500 600 Contact 1/ 20 -m2 10 -m2 -m2
Collector Width 1/ 1.1 m 0.54 m m Thickness 1/ 1500 Å 1060 Å 750 Å Current Density 5
mA/m2 10 mA/m2
20 mA/m2
Acollector/Aemitter 2.8 2.8 2.8
f 371 GHz 517 GHz 720 GHz
maxf 483 GHz 724 GHz 1.06 THz
EE LI / 2.4 mA/m
2.4 mA/m
2.4 mA/m
f 1/ 340 fs 250 fs 170 fs
ccb IC / 1/ 440 fs/V 310 fs/V 220 fs/V
ccb IVC /logic 1/ 130 fs 94 fs 66 fs
)//( logic cbb IVR 0.66 0.51 0.41
)/( logic Cje IVC 1/ 350 fs 250 fs 180 fs
)//( logic cex IVR 0.24 0.24 0.24
Bipolar Transistor Scaling Laws & Scaling Roadmaps
key device parameter required change
collector depletion layer thickness decrease 2:1
base thickness decrease 1.414:1
emitter junction width decrease 4:1
collector junction width decrease 4:1
emitter resistance per unit emitter area decrease 4:1
current density increase 4:1
base contact resistivity (if contacts lie above collector junction)
decrease 4:1
base contact resistivity (if contacts do not lie above collector junction)
unchanged
Scaling Laws:design changes required to double transistor bandwidth
WE
WBC
WEB
x
L E
base
emitter
base
collector
WC
key figu
res of m
erit
for lo
gic sp
eed
Technology Roadmap through 330 GHz digital clock rate
• The current device is Gen 2.5.
• Key enabling technologies for the THz transistor
0
100
200
300
400
500
600
700
800
0 100 200 300 400 500 600 700 800
RSC
UIUC DHBT
NTT
Fujitsu HEMT
SFU
UIUC SHBT
UCSB
NGST
Pohang
HRL
IBM SiGe
Vitesse
f ma
x (G
Hz)
ft (GHz)
500 GHz400 GHz300 GHz200 GHz maxff
Updated June 2006
600 GHz
Present Status of Fast Transistors
)(
),/(
),/(
),/(
hence ,
:digital
gain, associated ,F
:amplifiers noise low
mW/
gain, associated PAE,
:amplifierspower
)11(
2/) (
alone or
min
1max
max
max
max
cb
cbb
cex
ccb
clock
ττ
VIR
VIR
IVC
f
m
ff
ff
ff
ff
:metrics better much
:metrics popular
UCSB 0.25μm
UCSB 0.6μm
Conclusion
• First generation of UCSB 250nm DHBT device
• ft/fmax = 420/650 GHz
• Record fmax for a DHBT
• High power density ~ 30 mW/ μm2
• High Kirk threshold ~ 12 mA/ μm2
• High BVeco ~ 5V
• Further scaling is feasible
This work was supported by the DARPA SWIFT program, the ONR under N0001-40-4-10071, DARPA TFAST program N66001-02-C-8080, and a grant by the Swedish Research Council.