8/10/2019 Dic File -7 sem

1/22

SUBMITTED BY

XYZ

ROLLNO

COE-I

SEM-VII

8/10/2019 Dic File -7 sem

2/22

Table of Contents

S.No Assignment Page

1

Characterization of Logic Family. Find out logicthreshold values and noise margins. Delay time

measurement of inverter using ring oscillator.

2 Design of combinational circuit 2!" Decoder "!2 encoder#inary to gray code converter using $%DL.

& 'odel fli(!flo( register latch in $%DL. )m(lement

Asynchronous and synchronous reset

" Design traffic light controller using $%DL.

* #inary and #CD counter using $%DL.

+ Data demulti(le,er. Data is re-uired on a high s(eed"!bit in(ut bus out(ut to one of the three "!bit out(ut bus.

Serial in (arallel out register using $%DL.

/ AL0 using $%DL

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Assignment 2

Design of 2," Decoder

--code for 2x4 decoder

library ieee;use ieee.std_logic_1164.all;

entity Decoder2x4 isport(i :in std_logic_vector(1 downto !;e :in

std_logic;o std_logic_vector(" down to !!;end Decoder2x4;

arc#itecture $e#v of Decoder2x4 isbeginprocess(i%e!begin

if(e&'1'! t#eno(!& (not i(!! and (not i(1!!;o(1!& i(! and (not i(1!!;o(2!& (not i(!! and i(1!;o("!& i(! and i(1!;

elseo-)****+;

end if;end process;end arc#itecture;

Test Bench

--test benc#

entity ,$ isend ,$;

arc#itecture ,$_arc# of ,$ is

coponent Decoder2x4 isport(i :in std_logic_vector(1 downto !;e :in

std_logic;o std_logic_vector(" down to !!;end coponent;signal i:std_logic_vector(1 downto !;signal e:std_logic;signal o:std_logic_vector(" downto !;begin

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inst:Decoder2x4 port ap(i%e%o!;processbegin

e& not e after ns;i& transport )+;

wait for 2ns;i& transport )1+;wait for 2ns;i& transport )1+;wait for 2 ns;i& transport )11+;wait for 2 ns;

end process;end arc#itecture;

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Design of ",2 ncoder

--code for 4x2 encoder

library ieee;

use ieee.std_logic_1164.all;

entity encoder4x2 isport(i:in std_logic_vector(" downto !;o:out

std_logic_vector(1 downto !;e:in std_logic!;end encoder4/2;

arc#itecture be#v of encoder4x2 isbeginprocess(i%e!begin

if e&'1' t#encase i is

w#en )1+&0 o&++;w#en )1+&0 o&+1+;w#en )1+&0 o&+1+;w#en )1+&0 o&+11+;w#en ot#ers&0 o&+**+;

elseo&+**+;

end if;end process;

end arc#itecture;

Test Bench

-- test benc#

entity tb isend tb;

arc#itecture tb_arc# of tb iscoponent encoder4x2 is

port(i:in std_logic_vector(" downto !;o:outstd_logic_vector(1 downto !;e:in std_logic!;end coponent;signal i:std_logic_vector(" downto !;signal o:std_logic_vector(1 downto !;signal e:std_logic;begin

inst:encoder4x2 port ap(i%o%e!;

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processbegin

e& not e after 4 ns;i&+1+;wait 1 ns;

i&+1+;wait 1 ns;i&+1+;wait 1 ns;i&+1+;wait 1 ns;

end process;end arc#itecture;

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Design of #inary to 3ray Code Converter

-- code for binary to gray converter

library ieee;

use ieee.std_logic_1164.all;entity b2g is

port(i:in std_logic_vector(" downto !;o:out std_logic_vector(" downto !;e:in std_logic!;

end b2g;arc#itecture be#v of b2g isbeginprocess(i%e!begin

if e&'1' t#eno(!& i(! xor i(1!;

o(1!& i(1! xor i(2!;o(2!& i(2! xor i("!;o("!& i("!;

elseo&+****+;

end if;end process;end arc#itecture;

Test Bench

-- test benc#entity tb isend tb;arc#itecture tb_arc# of tb iscoponent b2g is

port(i:in std_logic_vector(" downto !;o:out std_logic_vector(" downto !;e:in std_logic!;

end coponent;signal i:std_logic_vector(" downto !;signal o:std_logic_vector(" downto !;signal e:std_logic;begin

inst:b2g port ap(i%o%e!;processbegin

e&not e after " ns;i&++;wait for 1 ns;i&+11+'wait for 1 ns;

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i&+11+;wait for 1 ns;

end process;end arc#itecture;

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Assignment &

Design of Synchronous and Asynchronous 4egister

--sync#ronous register

library ieee;use ieee.std_logic_1164.all;entity syn__reg is

port(d:in std_logic_vector( downto !;:out std_logic_vector( downto !;cl3:in std_logic;rst:in std_logic!;

end syn__reg;arc#itecture be#v_syn of syn__reg isbeginprocess(cl3!begin

if cl3&'1' t#enif rst&'1' t#en

&++;else

&d;end if;

end if;end process;end arc#itecture;

--async#ronous register

library ieee;use ieee.std_logic_1164.all;entity asyn__reg is

port(d:in std_logic_vector( downto !;:out std_logic_vector( downto !;cl3:in std_logic;rst:in std_logic!;

end asyn__reg;arc#itecture be#v_asyn of asyn__reg isbegin

process(cl3%rst!begin

if rst&'1' t#en&++;

elsif cl3&'1' t#en&d;

end if;end process;

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end arc#itecture;

Test Bench

--test benc#

entity tb isend tb;

arc#itecture tb_arc# of tb iscoponent syn__reg is

port(d:in std_logic_vector( downto !;:out std_logic_vector( downto !;cl3:in std_logic;rst:in std_logic!;

end coponent;coponent asyn__reg is

port(d:in std_logic_vector( downto !;:out std_logic_vector( downto !;cl3:in std_logic;rst:in std_logic!;

end coponent;signal d:std_logic_vector( downto !;signal syn%asyn:std_logic_vector( downto !;signal cl3:std_logic;signal rst:std_logic;begininst1:syn__reg port ap(d%syn%cl3%rst!;inst2:asyn__reg port ap(d%asyn%cl3%rst!;cl3&not cl3 after 1 ns;rst&not rst after 1 ns;

processbegin

d&++;wait for " ns;d&+111+;wait for " ns;

end process;end arc#itecture;

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Design of Synchronous and Asynchronous D Fli(!flo(

--sync#ronous D flip-floplibrary ieee;use ieee.std_logic_1164.all;

entity syn_d_ff isport(d:in std_logic;:out std_logic;cl3:in std_logic;

rst:in std_logic!;end syn_d_ff;arc#itecture be#v_syn of syn_d_ff isbeginprocess(cl3!begin

if cl3&'1' t#enif rst&'1' t#en

&'';else

&d;end if;

end if;end process;end arc#itecture;

--async#ronous D flip-floplibrary ieee;

use ieee.std_logic_1164.all;

entity asyn_d_ff isport(d:in std_logic;:out std_logic;cl3:in std_logic;

rst:in std_logic!;end asyn_d_ff;arc#itecture be#v_asyn of asyn_d_ff isbeginprocess(cl3%rst!begin

if rst&'1' t#en

&'';elsif cl3&'1' t#en&d;

end if;end process;end arc#itecture;

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Test Bench

--test benc#

entity tb is

end tb;arc#itecture tb_arc# of tb is

coponent syn_d_ff isport(d:in std_logic;:out std_logic;cl3:in std_logic;

rst:in std_logic!;end coponent;coponent asyn_d_ff is

port(d:in std_logic;:out std_logic;cl3:in std_logic;rst:in std_logic!;

end coponent;

signal d%syn%asyn%rst%cl3: std_logic;begininst1: syn_d_ff port ap(d%syn%cl3%rst!;inst2: asyn_d_ff port ap(d%asyn%cl3%rst!;processbegin

d&'1';wait for " ns;d&'';wait for " ns;

end process;

cl3&not cl3 after 1 ns;rst&not rst after 1 ns;end arc#itecture;

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Design of Latch

--dlatc#library ieee;use ieee.std_logic_1164.all;

entity dlatc# isport(d:in std_logic;:out std_logic;cl3:in std_logic;

rst:in std_logic!;end dlatc#;arc#itecture be#v_latc# of dlatc# isbeginprocess(d%rst!begin

if rst&'1' t#en&'';

elsif cl3&'1' t#en&d;end if;

end process;end arc#itecture;

Test Bench

--test benc#

entity tb isend tb;arc#itecture tb_arc# of tb iscoponent dlatc# is

port(d:in std_logic;:out std_logic;cl3:in std_logic;rst:in std_logic!;

end coponent;

signal d%%rst%cl3: std_logic;begininst: dlatc# port ap(d%%cl3%rst!;processbegin

d&'1';wait for " ns;d&'';wait for " ns;

end process;cl3&not cl3 after 1 ns;rst&not rst after 1 ns;end arc#itecture;

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Assignment "

Design of 5raffic Light Controller

--traffic lig#t controller

library ieee;use ieee.std_logic_1164.all;

entity tlc isport(cl3:in std_logic;red:out std_logic;yellow:out

std_logic;green:out std_logic!;end tlc;

arc#itecture tlc_arc# of tlc istype state is (57D%58799%5

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count:&;else

count:&count>1;red&'';yellow&'';

gree&'1';w#en ot#ers&0 tlcstate:&57D;count:&;

end case;end if;

end process;end arc#itecture;

Test Bench

--test benc#entity tb isend tb;

arc#itecture tb_arc# of tb iscoponent tlc is

port(cl3:in std_logic;red:out std_logic;yellow:outstd_logic;green:out std_logic!;

end coponent;

signal cl3:std_logic:&'';signal red% yellow% green : std_logic;begin

cl3&not cl3 after 1 ns;inst:tlc port ap(cl3%red%yellow%green!;end arc#itecture;

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Assignment *

Design of #inary Counter and #CD Counter

--binary counterlibrary ieee;use ieee.std_logic_1164.all;entity bincnt is

port(count:out std_logic_vector(" downto !;cl3:instd_logic;rst:in std_logic!;

end bincnt;

arc#itecture bincnt_arc# of bincnt isbeginprocess(cl3%rst!begin

if rst&'1' t#encount&++;

elsif cl3'event and cl3&'1' t#encount&count>1;

end if;end process;end arc#itecture;

--bcd counterlibrary ieee;

use ieee.std_logic_1164.all;entity bcdcnt is

port(count:out std_logic_vector(" downto !;cl3:instd_logic;rst:in std_logic!;

end bcdcnt;

arc#itecture bcdcnt_arc# of bcdcnt isbeginprocess(cl3%rst!begin

if rst&'1' t#en

count&++;elsif cl3'event and cl3&'1' t#en

if count&+11+ t#encount&++;

elsecount&count>1;

end if;end if;

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end process;end arc#itecture;

Test Bench

--testbenc#

entity tb isend tb;arc#itecture tb_arc# of tb iscoponent bincnt is

port(count:out std_logic_vector(" downto !;cl3:instd_logic;rst:in std_logic!;

end coponent;coponent bcdcnt is

port(count:out std_logic_vector(" downto !;cl3:instd_logic;rst:in std_logic!;

end coponent;signal cl3%rst:std_logic:&'';signal bcdcount%bincount:std_logic_vector(" downto !;begincl3&not cl3 after 2 ns;rst&not rst after 4 ns;inst1: bincnt port ap(bincount%cl3%rst!;inst2: bcdcnt port ap(bcdcount%cl3%rst!;end arc#itecture;

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Assignment +

Design of " #it Data Demulti(le,er

--Deultiplexer 4 bit data on t#ree 4 bit output bus

library ieee;use ieee.std_logic_1164.all;

entity deux isport(din:in std_logic_vector(" downto !;sel:in

std_logic_vector(1 downto !;dout1% dout2%dout":outstd_logic_vector(" downto !!;

end deux;

arc#itecture deux_arc# of deux isbeginprocess(din%sel!begin

case sel isw#en )+&0 dout1&din;

dout2&+????+;dout"&+????+;

w#en )1+&0 dout1&+????+;dout2&din;

dout"&+????+;w#en ot#ers&0dout1&+????+;

dout2&+????+;dout"&din;

end case;end process;end arc#itecture;

Test Bench

-- testbenc#

entity tb isend tb;arc#itecture tb_arc# of tb iscoponent deux is

port(din:in std_logic_vector(" downto !;sel:instd_logic_vector(1 downto !;dout1% dout2%dout":out

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std_logic_vector(" downto !!;end coponent;signal din%dout1%dout2%dout":std_logic_vector(" downto !;signal sel:std_logic_vector(1 downto !;begin

inst:deux port ap(din%sel%dout1%dout2%dout"!;p1:processbegin

din&+1+;wait for 2 ns;din&+11+;wait for 2 ns;

end process;p2:processbegin

sel&++;wait for 2 ns;sel&+1+;wait for 2 ns;sel&+1+;wait for 2 ns;sel&+1+;wait for 2 ns;sel&+11+;wait for 2 ns;

end process;end arc#itecture;

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Assignment

AL0 Design

--serial in parallel out register

library ieee;use ieee.std_logic_1164.all;

entity sipo isport(sin%cl3%rst%enable:in std_logic; o:out

std_logic_vector(" downto !!;end sipo;

arc#itecture sipo_arc# of sipo issignal tep:std_logic_vector(" downto !;beginprocess(cl3!begin

if rst&'1' t#entep&++;

elseif cl3&'1' and enable&'1' t#en

tep("!&tep(2!;tep(2!&tep(1!;tep(1!&tep(!;

tep(!&sin;end if;

end if;end process;o&tep;end arc#itecture;

--testbenc#

entity tb isend tb;

arc#itecture tb_arc# of tb iscoponent sipo is

port(sin%cl3%rst%enable:in std_logic; o:outstd_logic_vector(" downto !!;

end coponent;signal sin%cl3%rst%enable:std_logic;signal o:std_logic_vector(" downto !;begin

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inst: sipo(sin%cl3%rst%enable%o!;cl3&not cl3 after 1 ns;processenable&'1';rst&'';

sin&'1';wait for 1 ns;sin&'1';wait for 1 ns;sin&'';wait for 1 ns;sin&'1';wait for 1 ns;end process;end arc#itecture;

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Assignment /

--@9A

library ieee;

use ieee.std_logic_1164.all;use ieee.std_logic_arit#.all;use ieee.std_logic_unsigned.all;

entity alu isport(a%b:in std_logic_vector(6 downto !;

?:out std_logic_vector( downto !;sel:in std_logic-vector(" downto !;c:in std_logic!;

end alu;arc#itecture alu_d_arc# of alu is

beginprocess(a%b%sel!begin

case sel isw#en )+&0 ?(6 downto !&a and b;w#en )1+&0 ?(6 downto !&a or b;w#en )1+&0 ?(6 downto !&a xor b;w#en )11+&0 ?(6 downto !&not a;w#en )1+&0 ?&a>b;w#en )11+&0 ?&a-b;w#en )11+&0 ?&a>1;w#en )111+&0 ?&a-1;w#en )1+&0 ?(6 downto 1!&a( downto !;

?(!&'';w#en )11+&0 ?( downto !&a(6 downto 1!;

?(6!&'';w#en ot#ers&0 ?&(ot#ers&0'?'!;

case end;end process;end arc#itecture;