digital circuits systems
DESCRIPTION
Digital Circuit Systems by Parul Garg MamTRANSCRIPT
INDEX
S.NO Experiment Signature
1 Design of combinational circuit, 2-4 Decoder, 4-2 encoder, Binary to gray code converter using VHDL
2 Model flip-flop, register, latch in VHDL. Implement Asynchronous and synchronous reset
3 Design of Traffic Light Controller system
4 Binary and BCD counter using VHDL.
5 Data demultiplexer : Data is required on a high speed 4-bit input bus, output to one of the three 4-bit output bus.
6 Serial in parallel out register using VHDL.
7 ALU using VHDL
8 FSM To check divisibility by 5.
9 Characterization of Logic Family. Find out logic Threshold values and noise margins. Delay time measurement of inverter using ring oscillator.
EXPERIMENT 2 AIM: Design of combinational circuit, 2-4 Decoder, 4-2 encoder, Binary to gray code converter using VHDL CODE:
a) 2 X 4 decoder: library ieee;
use ieee.std_logic_1164.all;
entity Decoder2x4 is
port(a :in std_logic_vector(1 downto 0);e :in
std_logic;ostd_logic_vector(3 down to 0));
end Decoder2x4;
architecture Behv of Decoder2x4 is
begin
process(i,e)
begin
if(e=’1’) then
o(0)<= (not a(0)) and (not a(1));
o(1)<= a(0) and (not a(1));
o(2)<= (not a(0)) and a(1);
o(3)<= a(0) and a(1);
else
o<=“ZZZZ”;
end if;
end process;
end architecture;
b) 4 X 2 encoder: library ieee; use ieee.std_logic_1164.all; entity encoder4x2 is port(a:instd_logic_vector(3 downto 0);o:out std_logic_vector(1 downto 0);e:instd_logic); end encoder4X2; architecture behv of encoder4x2 is begin process(a,e) begin if e=’1’ and a(3)=’1’ then o<=”11”; elsif e=’1; and a(2)=’1’ then o<=”10”; elsif e=’1’ and a(1)=’1’ then o<=”01”; elsif e=’1’ and a(0)=’1’ then o<=”00”; else o<=”ZZ”; end if; end process; end architecture;
c) Binary to Gray code converter library ieee; use ieee.std_logic_1164.all; entity b2g is port(b:instd_logic_vector(3 downto 0); g:out std_logic_vector(3 downto 0)); end b2g; architecture behv of b2g is begin process(b) begin
g(0)<= b(0) xor b(1); g(1)<= b(1) xor b(2); g(2)<= b(2) xor b(3); g(3)<= b(3);
end process; end architecture;
EXPERIMENT 3 AIM: Model flip-flop, register, latch in VHDL. Implement Asynchronous and synchronous reset CODE:
a) Synchronous and Asynchronous register --synchronous register library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg is Port ( data_in : in STD_LOGIC_VECTOR (3 downto 0); data_out : out STD_LOGIC_VECTOR (3 downto 0); reset : in STD_LOGIC; clk : in STD_LOGIC); end reg; architecture Behavioral of reg is begin process(clk,reset) begin if reset = '1' then data_out <= "0000"; else if (reset= '0' and clk='1') then data_out <= data_in; end if; end if; end process; end Behavioral;
--asynchronous register library ieee; use ieee.std_logic_1164.all; entity asyn_8_reg is port(d:instd_logic_vector(7 downto 0); q:out std_logic_vector(7 downto 0); clk:instd_logic;rst:instd_logic); end asyn_8_reg; architecture behv_asyn of asyn_8_reg is begin process(clk,rst) begin if rst=’1’ then q<=”00000000”; elsifclk=’1’ then q<=d; end if; end process; end architecture;
b) Synchronous and Asynchronous D flip flop --synchronous D flip-flop library ieee; use ieee.std_logic_1164.all; entity syn_d_ff is port(d:instd_logic;q:outstd_logic;clk:instd_logic; rst:instd_logic); end syn_d_ff; architecture behv_syn of syn_d_ff is begin process(clk) begin if clk=’1’ then if rst=’1’ then q<=’0’; else q<=d; end if; end if; end process; end architecture;
--asynchronous D flip-flop library ieee; use ieee.std_logic_1164.all; entity asyn_d_ff is port(d:instd_logic;q:outstd_logic;clk:instd_logic; rst:instd_logic); end asyn_d_ff; architecture behv_asyn of asyn_d_ff is begin process(clk,rst) begin if rst=’1’ then q<=’0’; elsifclk=’1’ then q<=d; end if; end process; end architecture;
c) Latch --dlatch library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity latch is
Port ( D : in STD_LOGIC; Q : out STD_LOGIC; en : in STD_LOGIC; rst : in STD_LOGIC); end latch; architecture Behavioral of latch is begin process(en,D,rst) begin if(rst='1')then Q<='0'; else if(en='1') then Q<=D; end if; end if; end process; end Behavioral;
EXPERIMENT 4 AIM: Design of Traffic-light Controller system The state diagram is as under:
CODE: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Traffic_Light is Port ( clk : in STD_LOGIC; R : out STD_LOGIC; Y : out STD_LOGIC; G : out STD_LOGIC); end Traffic_Light; architecture Behavioral of Traffic_Light is type STATE is (RED,YELLOW,GREEN); begin
process(clk) variable TLCSTATE : STATE := RED; variable count : integer := 0; begin if clk='1' then case TLCSTATE is when RED => if count=10 then TLCSTATE:=GREEN; count:=0; else count:=count+1; R<='1'; Y<='0'; G<='0'; end if; when YELLOW => if count=2 then TLCSTATE:=RED; count:=0; else count:=count+1; R<='0'; Y<='1'; G<='0'; end if; when GREEN => if count=10 then TLCSTATE:=YELLOW; count:=0; else count:=count+1; R<='0'; Y<='0'; G<='1'; end if; end case; end if; end process; end Behavioral;
EXPERIMENT 5 AIM: BCD and Binary counter using VHDL CODE:
--binary counter library ieee; use ieee.std_logic_1164.all; entitybincnt is port(q2: out std_logic_vector(3 downto 0); q: inout std_logic_vector(3 downto 0); clk:in std_logic;rst:in std_logic); end bincnt; architecture bincnt_arch of bincnt is begin process(clk,rst) begin if rst=’1’ then q<=”0000”; elsifclk’event and clk=’1’ then q<=q+”0001”; q2<=q; end if; end process; end architecture;
--bcd counter
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bcdcount is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; op : out STD_LOGIC_VECTOR (3 downto 0)); end bcdcount; architecture Behavioral of bcdcount is constant s0:STD_LOGIC_VECTOR (3 downto 0):="0000"; constant s1:STD_LOGIC_VECTOR (3 downto 0):="0001"; constant s2:STD_LOGIC_VECTOR (3 downto 0):="0010"; constant s3:STD_LOGIC_VECTOR (3 downto 0):="0011"; constant s4:STD_LOGIC_VECTOR (3 downto 0):="0100"; constant s5:STD_LOGIC_VECTOR (3 downto 0):="0101"; constant s6:STD_LOGIC_VECTOR (3 downto 0):="0110"; constant s7:STD_LOGIC_VECTOR (3 downto 0):="0111"; constant s8:STD_LOGIC_VECTOR (3 downto 0):="1000"; constant s9:STD_LOGIC_VECTOR (3 downto 0):="1001"; signal ps,ns: STD_LOGIC_VECTOR (3 downto 0):="0000"; begin process(clk,reset) begin if (clk='1' and clk'event) then if (reset='0') then if (ps=s0) then ns<=s1; elsif (ps=s1) then ns<=s2; elsif (ps=s2) then ns<=s3; elsif (ps=s3) then ns<=s4; elsif (ps=s4) then ns<=s5; elsif (ps=s5) then ns<=s6; elsif (ps=s6) then
ns<=s7; elsif (ps=s7) then ns<=s8; elsif (ps=s8) then ns<=s9; elsif (ps=s9) then ns<=s0; end if; elsif (reset='1') then ps<=s0; ns<=s0; end if; end if; ps<=ns; op<=ps; end process; end Behavioral;
EXPERIMENT 6 AIM: Design of 4-bit data demultiplexer CODE: library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Data_Demux is
Port ( Sel : in STD_LOGIC_VECTOR (1 downto 0);
Data_In : in STD_LOGIC_VECTOR (3 downto 0);
Data_Out1 : out STD_LOGIC_VECTOR(3 downto 0);
Data_Out2 : out STD_LOGIC_VECTOR(3 downto 0);
Data_Out3 : out STD_LOGIC_VECTOR(3 downto 0));
end Data_Demux;
architecture Behavioral of Data_Demux is
begin
process(Sel,Data_in)
begin
case Sel is
when "00" => Data_Out1<=Data_In;
Data_Out2<="ZZZZ";
Data_Out3<="ZZZZ";
when "01" => Data_Out1<="ZZZZ";
Data_Out2<=Data_In;
Data_Out3<="ZZZZ";
when "10" => Data_Out1<="ZZZZ";
Data_Out2<="ZZZZ";
Data_Out3<=Data_In;
when others => Data_Out1<="ZZZZ";
Data_Out2<="ZZZZ";
Data_Out3<="ZZZZ";
end case;
end process;
end Behavioral;
EXPERIMENT 7 AIM: Serial-In-Parallel-Out register using VHDL CODE: library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SIPO_Register is
Port ( clk : in STD_LOGIC;
D : in STD_LOGIC;
Reset : in STD_LOGIC;
Q : inout STD_LOGIC_VECTOR (3 downto 0));
end SIPO_Register;
architecture Behavioral of SIPO_Register is
begin
process(Reset,clk)
begin
if Reset='1' then
Q <= "0000";
elsif (rising_edge(clk)) then
Q(3 downto 1) <= Q(2 downto 0);
Q(0) <= D;
end if;
end process;
end Behavioral;
EXPERIMENT 8 AIM: Design an ALU using VHDL DESCRIPTION:
The function table for ALU is as follows:
Here, A and B are 8-bit inputs.
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
Port ( Sel : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
Cout : out STD_LOGIC;
Z : out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Behavioral of ALU is
begin
process(Sel,A,B,Cin)
variable temp : STD_LOGIC_VECTOR(8 downto 0);
begin
temp := "000000000";
case Sel is
when "0000" => temp:=('0'&A)+Cin;
when "0001" => temp:=('0'&A)+('0'&B)+Cin;
when "0010" => temp:=('0'&A)+('0'&(not B))+Cin;
when "0011" => temp:=('0'&A)-1+Cin;
when "0100" => temp(7 downto 0):=A and B;
when "0101" => temp(7 downto 0):=A or B;
when "0110" => temp(7 downto 0):=A xor B;
when "0111" => temp:=('0' & (not A));
when others => if Sel(2)='0' then
temp(6 downto 0):=A(7 downto 1);
elsif Sel(2)='1' then
temp(7 downto 1):=A(6 downto 0);
end if;
end case;
Z <= temp(7 downto 0);
Cout <= temp(8);
end process;
end Behavioral;
EXPERIMENT 9
AIM: Design a Finite State Machine to check divisibility by 5.
DESCRIPTION:
The circuit detects if an incoming serial number is divisible by 5. The state diagram for a Divide-by-5 FSM is:
Each state represents the remainder when divided by 5. So the output is 1 only when the remainder is 0, i.e., the number is completely divisible by 5.
CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FSM is
Port ( X : in STD_LOGIC;
Reset : in STD_LOGIC;
clk : in STD_LOGIC;
Z : out STD_LOGIC);
end FSM;
architecture Behavioral of FSM is
type STATE_TYPE is (S0,S1,S2,S3,S4);
signal CURRENT_STATE,NEXT_STATE : STATE_TYPE;
begin
--Process to hold synchronous elements (flip-flops)
SYNCH: process(Reset,clk)
begin
if Reset='1' then
CURRENT_STATE <= S0;
elsif (rising_edge(clk)) then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
--Process to hold combinational logic
COMBIN: process(CURRENT_STATE,X)
begin
case CURRENT_STATE is
when S0 => Z<='1';
if X='0' then
NEXT_STATE <= S0;
elsif X='1' then
NEXT_STATE <= S1;
end if;
when S1 => Z<='0';
if X='0' then
NEXT_STATE <= S2;
elsif X='1' then
NEXT_STATE <= S3;
end if;
when S2 => Z<='0';
if X='0' then
NEXT_STATE <= S4;
elsif X='1' then
NEXT_STATE <= S0;
end if;
when S3 => Z<='0';
if X='0' then
NEXT_STATE <= S1;
elsif X='1' then
NEXT_STATE <= S2;
end if;
when S4 => Z<='0';
if X='0' then
NEXT_STATE <= S3;
elsif X='1' then
NEXT_STATE <= S4;
end if;
end case;
end process;
end Behavioral;
EXPERIMENT 1
AIM: Characterization of Logic Family. Find out logic Threshold values and noise margins. Delay time measurement of inverter using ring oscillator. DIAGRAM:
For N=5 i.e no.of inverters used=5 OBSERVATION TABLE: (a) Delay time of an inverter: S. NO. No of inverters (N) Frequency observed (f) Delay of inverter
(tpd) 1 3 30.3 MHz 5 ns
2 5 20MHz 5ns
3 7 13MHz 5ns
Using the formula 𝑓 = 1/(2 ∗ 𝑁 ∗ 𝑡𝑝𝑑)
(b) Logic threshold values and Noise margins:
Input (in V) Output (in V)
0.015 4.971
0.016 4.968 0.018 4.962
0.022 4.962 0.102 4.962
0.140 4.9652
0.204 4.9647 0.316 4.9632
0.405 4.9632 0.636 4.9641
0.773 4.9672
0.943 4.9640 1.196 4.9671
1.220 4.9627 1.332 0.5108
1.430 0.0072 1.692 0.0068
2.071 0.0063
2.271 0.0061 2.782 0.0051
3.102 0.0039 3.651 0.0075
4.091 0.0084
4.532 0.0078 4.731 0.0071
GRAPH:
VOH = 4.9627V VOL = 7.1mV VIH = 1.43V VIL = 1.22V Result: For IC – 74HC04 the delay time of a single inverter comes out to be 5ns and the logic threshold values and noise margins are NML = VIL – VOL = 1.2130V NMH = VOH – VIH = 3.5327V