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ECE124 Digital Circuits and Systems Page 1
ECE124 Digital Circuits and Systems Page 2
Chip level timing
Have discussed some issues related to timing analysis.
Talked briefly about longest combinational path for a combinational circuit.
Talked briefly about timing with flip-flops; i.e.,
Data input must be stable before active clock edge (setup time).
Data input must be stable after active clock edge (hold time).
Data output doesn’t change immediately after the active clock edge (clock-to-output time).
When we build an entire circuit (one with both flip-flops and combinational logic), there are other important timing concepts to understand.
ECE124 Digital Circuits and Systems Page 3
Cycle times (1)
Consider flip-flop outputs being used to generate flip-flop inputs:
D Q D Qcombinatorial
logic (and delay)clk
Tco TsuTdata
Tclk1Tclk2
It takes time for signals to arrive where they need to be…
ECE124 Digital Circuits and Systems Page 4
Cycle times (2)
Sequence of events in “transfer of data between flip-flops”:
Takes time for active clock edge to arrive at first FF (Tclk1).
Once active clock edge arrives, takes time for output of first FF to change (+Tco).
Takes time for output of first FF to cause changes in the input value to the second FF due to combinatorial logic between FF (+Tdata).
Input at second FF must be present prior to active clock edge at second FF (Tsu).
Takes time for clock to arrive at second FF (Tclk2).
Must be some limit of how fast we can clock the circuit (i.e., the frequency of clock signal):
Data output from first FF must “get” to data input of second FF prior to the next active clock edge.
ECE124 Digital Circuits and Systems Page 5
Cycle times (3)
For the data output of the first FF to “get” to the data input of the second FF in sufficient time, the following must be true:
The minimum period (maximum frequency) of the circuit is:
ECE124 Digital Circuits and Systems Page 6
Cycle times (4)
D Q D Qcombinatorial
logic (and delay)clk
Tco TsuTdata
Tclk1Tclk2
The equation for Tcycle tells us a minimum clock period (or maximum frequency) at which our circuit can operate without violating the setup time at the second FF input.
ECE124 Digital Circuits and Systems Page 7
Cycle times (5)
CLK
FF1 CLK
FF2 CLK
FF1 Q
FF2 D
Tclk1Tco
Tdata
Tclk1 Tcycle
Tsu
ECE124 Digital Circuits and Systems Page 8
Clock skew
If we look at our equation for maximum frequency:
The term (Tclk1 – Tclk2) that measures the difference in time between the arrival of the active clock edge at the two flip-flops.
This difference is called clock skew and it can be positive or negative.
In general, clock skew is a big hassle, and we would like to avoid it if possible.
Circuit frequency <= 1/Tcycle
ECE124 Digital Circuits and Systems Page 9
Inverted clocks (1)
Sometimes we might have flip-flops clocked on different edges of the clock; some flip-flops trigger on the rising edge and others on the falling edge.
This can limit the maximum frequency of the circuit too since we have less time to get data to where it needs to be!
D Q D Qcombinatorial
logic (and delay)clk
Tco TsuTdata
Tclk1Tclk2
Falling edge Rising edge
ECE124 Digital Circuits and Systems Page 10
Inverted clocks (2)
Since the second FF is triggered on the falling edge, either Tdata must be short enough, or the cycle time for the clock needs to be lengthened (lower frequency) to allow the data to get to the second FF.
CLK
FF1 CLK
FF2 CLK
FF1 Q
FF2 D
Tclk1Tco
Tdata
Tclk1 Tcycle
Tsu
ECE124 Digital Circuits and Systems Page 11
CLK
FF1 CLK
FF2 CLK
FF1 Q
FF2 D
Tclk1Tco
Tdata
Tclk1 Tcycle
Tsu
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Duty cycles
Sometimes the clock signal is not symmetric; It has a non-uniform duty cycle.
If we use both rising and falling edge triggering, this can also affect the clock frequency.
CLK
2/3 high (66% duty cycle)
1/3 low
ECE124 Digital Circuits and Systems Page 13
Setup and hold times at the pins of a chip (1)
Say we have a circuit implemented inside of an integrated circuit (IC) chip.
The circuit and IC now looks like a black-box.
Timing at the pins of the chip are now important.
Suppose you have a data present at at input pin on the IC.
The signal might go through some logic inside the IC prior to reaching a flip-flop input inside of the IC.
The flip-flop inside of the IC is clocked by another clock signal applied at another pin of the IC.
ECE124 Digital Circuits and Systems Page 14
Setup and hold times at the pins of a chip (2)
There is a setup and hold time at the flip-flop inside of the IC and a relationship between the FF-D input and the FF-CLK input.
Therefore, there must be a relationship between the data input and the clock input at the chip pins.
D Qcombinatorial
logic (and delay)
Tsu/Th
Tdata
Tclk
clk
data
pins at ICboundary
logicinside IC
flip-flopinside IC
Tsu
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Setup and hold times at the pins of a chip (3)
Let:
cf - time when active clock edge arrives at FF CLK INPUT.
cc - time when active clock edge arrives at CLK PIN.
df - time when data input at FF D INPUT makes a transition.
dc - time when data input at DATA PIN makes a transition.
Let:
Tsu - the setup time of the FF D input w.r.t. the FF CLK input.
Th - the hold time of the FF D input w.r.t. the FF CLK input.
Let:
Tsetup - the setup time of the DATA PIN input w.r.t. the CLK PIN.
Thold - the hold time of the DATA PIN input w.r.t. the CLK PIN.
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Setup and hold times at the pins of a chip (4)
The following must be true at the flip-flop: df not in [cf-Tsu,cf+th] otherwise the flip-flop might not work correctly (data must be stable around the active clock edge).
Two inequalities: df not in [cf-Tsu,cf+Th] implies:
df < cf – Tsu but:
dc+Tdata = df and:
cc + Tclk = cf so:
dc+Tdata < cc+Tclk-Tsu and:
dc < cc – (Tsu-Tclk+Tdata).
df not in [cf-Tsu,cf+Th] implies:
df > cf + Th but:
dc+Tdata = df and:
cc + Tclk = cf so:
dc+Tdata > cc+Tclk+Th and:
dc > cc + (Th+Tclk-Tdata).
Recall: cf - time when active clock edge arrives at FF CLK INPUT. cc - time when active clock edge arrives at CLK PIN. df - time when data input at FF D INPUT makes a transition. dc - time when data input at DATA PIN
makes a transition. cc cf
Tsu cf-Tsu
df can occur here
dc+Tdata
cc+Tclk
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Setup and hold times at the pins of a chip (5)
We find a relationship between the data input and clock input at the IC PINS due to the relationship at the FF inputs inside the chip:
dc < cc – (Tsu-Tclk+Tdata). dc > cc + (Th+Tclk-Tdata).
So, we have the relationship: dc not in [cc-Tsetup,cc+Thold]
There are setup and hold times at the IC inputs.
When we use an IC, we must pay attention to these times to make sure that the IC will work correctly.
ECE124 Digital Circuits and Systems Page 18
Setup and hold times at the pins of a chip (6)
CLK
FF CLK
FF D
DATA
Tclk
Tsu Th
Tdata
Tdata
Tseup Thold
D Qcombinatorial
logic (and delay)
Tsu/Th
Tdata
Tclk
clk
data
pins at ICboundary
logicinside IC
flip-flopinside IC
Tsu
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Setup and hold times at the pins of a chip (7)
When active clock edge arrives at a FF CLK input, the FF Q output changes after Tco.
Consider that the FF Q output drives OUTPUT PIN of IC.
Output will not appear for an amount of time called CLOCK-TO-OUTPUT TIME.
D Qcombinatorial
logic (and delay)
Tco
Tdata
Tclk
clk
pins at ICboundary
logicinside IC
flip-flopinside IC
data
Tclock_to_output = Tclk + Tco + Tdata
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Setup and hold times at the pins of a chip (8)
D Qcombinatorial
logic (and delay)
Tco
Tdata
Tclk
clk
pins at ICboundary
logicinside IC
flip-flopinside IC
data
CLK
FF CLK
FF D
FF Q
Tclk Tco Tdata
DATA
ECE124 Digital Circuits and Systems Page 21
Implementing logic gates in CMOS
Logic gates are implemented via transistors.
One popular technology for implementing transistors is Complementary Metal Oxide Semiconductor (CMOS) technology.
Transistors effectively implement switches. There are two types of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), namely the n-channel (NMOS) and p-channel (PMOS) transistor.
CMOS uses both NMOS and CMOS transistors to implement logic gates in a complementary way.
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Voltages and logic levels
Logic levels are represented with voltages.
The logic level “0” is represented by the lowest voltage (GND)
The logic level “1” is represented by the highest voltage (VDD)
Transistors are used as switches to “open” or “close” and connect wires to either VDD or GND.
ECE124 Digital Circuits and Systems Page 23
NMOS transistor
Simplified NMOS transistor has 3 terminals: 1) the Gate (G); 2) the Source (S) and 3) the Drain (D).
The source is at a lower voltage;
The drain is at a higher voltage.
When a high voltage is applied to G (w.r.t. to S) and VGS is above some threshold voltage VT the “switch” closes and D is connected to S (current flows from D to S). This “pulls down” the voltage at D to the voltage at S.
When the voltage between G and S is less than some threshold voltage VT the “switch” opens and D is disconnected from S (no current flows from D to S).
ECE124 Digital Circuits and Systems Page 24
PMOS transistor
Simplified PMOS transistor has 3 terminals: 1) the Gate (G); 2) the Source (S) and 3) the Drain (D).
The source is at a higher voltage;
The drain is at a lower voltage.
When a low voltage is applied to G (w.r.t. to S) and VSG is above some threshold voltage VT the “switch” closes and S is connected to D (current flows from S to D). This “pulls up” the voltage at D to the voltage at S.
When the voltage between S and G is less than some threshold voltage VT the “switch” opens and S is disconnected from D (no current flows from S to D).
ECE124 Digital Circuits and Systems Page 25
CMOS structure
CMOS combines NMOS and PMOS transistors in a structure which consists of a Pull-Up Network (PUN) and a Pull-Down Network (PDN) to implement logic functions.
PUN and PDN are duals of each other.
A current path (connection) from VDD to VF means VF is high (f is logic 1)
A current path (connection) from VF to GND means VF is low (f is logic 0).
“AND” corresponds to transistors in series…
“OR” corresponds to transistors in parallel…
!f
g
ECE124 Digital Circuits and Systems Page 26
CMOS inverter
When VX is high (logic 1): 1) NMOS is closed; 2) PMOS is open;3) current flows from VF to GND VF is GND (logic 0).
When VX is low (logic 0): 1) NMOS is open; 2) PMOS is closed;3) current flows from VDD to VF VF is VDD (logic 1).
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CMOS NAND
!(xy)
!x + !y
4 transistors
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CMOS NOR
!(x+y)
!x!y
4 transistors
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CMOS AND
Uses a CMOS NAND followed by a CMOS inverter
6 transistors
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What’s this?
A B C V0o
ut
0 0 0 Vdd
0 0 1 Vdd
0 1 0 Vdd
0 1 1 Vdd
1 0 0 Vdd
1 0 1 Gnd
1 1 0 Gnd
1 1 1 Gnd
ECE124 Digital Circuits and Systems Page 31
Transmission gates
When S is high (!S is low), both NMOS and PMOS are closed f = x.
When S is low (!S is high), both NMOS and PMOS are open f is disconnected from x (high impedence).
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XOR (using transmission gates)
8 transistors