digital design, 3e. - amazon s3s3.amazonaws.com/cramster-resource/662_n_8507.pdf · vcc pin 5 fig....

14 13 12 11 10 9 8

7654321

GND2-input NAND7400

VCC

14 13 12 11 10 9 8

7654321

GNDInverters7404

VCC

14 13 12 11 10 9 8

7654321

GND2-input NOR7402

VCC

14 13 12 11 10 9 8

7654321

GND2-input AND7408

VCC

Fig. 11-1 Digital Gates in IC Packages with Identification Numbers and Pin Assignments

© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.

14 13 12 11 10 9 8

7654321

GND3-input NAND7410

VCC

14 13 12 11 10 9 8

7654321

GND2-input OR7432

VCC

14 13 12 11 10 9 8

7654321

GND4-input NAND7420

VCC

14 13 12 11 10 9 8

7654321

GND2-input XOR7486

VCC

Fig. 11-1(cond) Digital Gates in IC Packages with Identification Numbers and Pin Assignments© 2002 Prentice Hall, Inc.

M. Morris ManoDIGITAL DESIGN, 3e.

14 13 12 11 10 9 8

7654321

VCC

7493

J QQA

K

C

CLR

12

Input A 14

J QQB

K

C

CLR

9

Input B 1

J QQC

K

C

CLR

8

J QQD

K

C

CLR

11

R1

R2

23

A

B

R1

R2 QD

QC

QB

QA

GND

7493

14

1

2

3

12

9

8

11

10

5

(c) Schematic diagram

(a) Internal circuit diagram

(b) Physical layout (NC: no connection)

A NC QA QD GND QB QC

B R1 R2 NC VCC NC NC

Fig. 11-2 IC Type 7493 Ripple Counter© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.

Push-buttonpulser or

clock

Indicatorlamps

VCCA

B

R1

R2

QD

QC

QB

QA

GND

7493

14

1

2

5

10

3

12

9

8

11

Fig. 11-3 Binary Counter


VCCA

B

R1

R2QD

QC

QB

QA

GND

7493

14

1

2

5

10

3

12

9

8

11

Inputpulses

Fig. 11-4 BCD Counter


Inputpulses F

QAA

QB

Fig. 11-3(counter)

QA

QB

F

0 1 0 1

0 0 1 1

1 1 1 0

Fig. 11-5 Waveforms for NAND Gate


F

x

y

z

Fig. 11-6 Logic Diagram for Experiment 3© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.

Fig. 11-7 IC Type 74155 Connected as a 3 8 Decoder

C

B

A

G

C1

C2

B

A

G1

G2

GND

1

15

3

13

2

14

9

10

11

12

7

6

5

4

74155

16

8

VCC

G

100000000

C

X00001111

B

X00110011

A

X01010101

2Y0

101111111

2Y1

110111111

2Y2

111011111

2Y3

111101111

1Y0

111110111

1Y1

111111011

1Y2

111111101

1Y3

111111110

Inputs Outputs

Truth table

2Y0

2Y1

2Y2

2Y3

1Y0

1Y1

1Y2

1Y3


7

1

2

6

A

B

C

D

GND

7447

7730

Vcc

Vcc 5 V

13

12

11

10

9

15

14

1

13

10

8

7

2

11

8

a

b

c

d

e

f

g

a

b

c

d

e

f

g

16

14

47 Ω

CA

fg

e

b

c

d

a

Fig. 11-8 BCD-to-Seven-Segment Decoder (7447) and Seven-Segment Display (7730)


Data Inputs

Strobe

74151

GNDVcc7

4

5

6

3

2

1

15

16 8

14

13

12

D0

S

Y

W

D1

D2

D3

D4

D5

D6

D7C B A

Output Y

W Y

Select inputs

9 10 11

S

100000000

C

X00001111

B

X00110011

A

X01010101

Y

0D0D1D2D3D4D5D6D7

Strobe Select OutputFunction table

Fig. 11-9 IC Type 74151 8 1 Multiplexer


7483

GND

Vcc16 14

15

1

2

6

9

4

3

7

8

5

11

10

13

B4

A4

B3

A3

B2

A2

B1

A1

C0

12

C4

S4

S3

S2

S1

Fig. 11-10 IC Type 7483 4-Bit Binary Adder


Data inputA

Data inputB

Data inputS

Output carry1

3

5

14

13 12

15

2

6

94

7

8

10

11

16

A4 C4

S4

S3

S2

S1

A3

A2

A1

B4

B3

B2

B1C0

7483

GND

Vcc

Mode select M

M 0 for addM 1 for subtract

Fig. 11-11 4-Bit Adder–Subtractor© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.

J Q

QK

CK

CLR

PR4

2

3

16

15

14

1

J Q

QK

CK

CLR

PR9

7

8

12

11

10

6

Function table

Inputs Outputs

No change

Toggle

GND pin 13

Preset

010

1111

Clear

100

1111

Clock

XXX

J

XXX

0011

K

XXX

0101

Q

101

Q

011

01

10

Vcc pin 5

Fig. 11-12 IC Type 7476 Dual JK Master–Slave Flip-Flops© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.

D Q

Q

CK

CLR

PR2

4

1

5

6

3

D Q

Q

CK

CLR

PR12

10

13

9

8

11

Function table

Inputs Outputs

No change

GND pin 7Vcc pin 14

Preset

010

111

Clear

100

111

Clock

XXX

↑↑0

D

XXX

01X

Q

101

Q

011

01

10

Fig. 11-13 IC Type 7474 Dual D Positive–Edge-Triggered Flip-Flops© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.

00

11

01 10

0/0 0/1

1/1

1/1

0/1

0/0

1/0

1/0

Fig. 11-14 State Diagram for Experiment 9


Data outputs

3

4

16

14

13

12

8

11

15

2

1

5

6

9

7

10

AQA

QB

QC

QD

B

C

D

L

P

T

CK

CLR

74161

GND

Vcc

Datainputs

Load

Count

Clock

Clear

COUT Carry out

Clear

0111

Clock

X↑↑↑

Load

X011

Count

XX10

Function

Clear outputs to 0Load input dataCount to next binary valueNo change in output

Function table

Fig. 11-15 IC Type 74161 Binary Counter with Parallel Load© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.

Data outputs

1

10

16

15

14

13

8

12

11

6

7

9

2

3

4

5

CLR

QA

QB

QC

QD

QD

CK

SH/LD

J

K

A

B

C

D

74195

GND

Vcc

Clock

Shift/load

Clear

Complement of QD

Serialinputs

Datainputs

Clear

01111

Shift/load

XX011

Clock

X0↑↑↑

Serial input

XXX01

J

XXX01

K

XXX01

Function

Asynchronous clearNo change in outputLoad input dataShift from QA toward QD, QA 0Shift from QA toward QD, QA 1

Function table

Fig. 11-16 IC Type 74195 Shift Register with Parallel Load© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.

Data outputs

2

5

16

4

7

9

8

12

10

13

11

14

36

1

15

Y1

A1

A2

A3

A4

B1

B2

B3

B4

Y2

Y3

Y474157

GND

SEL

STB

Vcc

Datainputs

B

Datainputs

A

Select

Strobe

Strobe100

SelectX01

Data outputs YAll 0'sSelect data inputs ASelect data inputs B

Function table

Fig. 11-17 IC Type 74157 Quadruple 2 1 Multiplexers


Data outputs

4

6

16

5

7

9

8

11

14

13

10

12

115

2

3

S1D1

D2

D3

D4

A0

A1

A2

A3

S2

S3

S4

74189

GND

CS

WE

Vcc

Addressinputs

Datainputs

Chip select

Write enable

CS001

WE01X

Data outputs High impedanceComplement of selected wordHigh impedance

OperationWriteReadDisable

Function table

Fig. 11-18 IC Type 74189 16 4 RAM


Mode controlinputs

74194

GNDSIL

SIR Vcc 15

12

13

144

3

5

6

10

162

9

11

1

B

A QA

QB

QC

QD

C

D

S1

S0

CK

CLR

7 8

Dataoutputs

Serial inputfor shift right

Serial inputfor shift left

Parallel datainputs

Clock

Clear

Clear011

1

1

ClockX↑↑

↑

↑

S1X00

1

1

S0X01

0

1

FunctionClear outputs to 0No change in outputShift right in the direction fromQA to QD. SIR to QA

Shift left in the direction fromQD to QA. SIL to QD

Parallel-load input data

Function table

Mode

Fig. 11-19 IC Type 74194 Bidirectional Shift Register with Parallel Load


74194

QA

CK CKS1 S1S0 S0

QB QC QD

SIRSIL

CLR CLR

A B C D A B C D

D Q

Q

CK

CLR

PR

74194

QA QB QC QD

SIRSIL

DQ

Q

CK

CLR

PR

CLK

Pulser

Reset

Start

Indicator lamps

Fig. 11-20 Lamp Handball Logic Diagram


Threshold

Trigger72555 Timer

Compare

Compare

GND

2

1

6

C

5 V

Vcc 8 5 Reset 4

Output

Discharge

3

7

RA

R

S

Q

Q

RB

0.01 µf

Fig. 11-21 IC Type 72555 Timer Connected as a Clock-Pulse Generator


10 µS

1 µS

Fig. 11-22 Output Waveform for Clock Generator


Count(pulser)

Addresscounter(7493)

RAM(74189)

MUX(74157)

Inverters(7404)

Select(switch)

4 switches

Output carry 4-bit adder(7483)

Sum

Register(74194)

Carry(7476)

Fig. 11-23 Block Diagram of a Parallel Adder for Experiment 16© 2002 Prentice Hall, Inc.M. Morris ManoDIGITAL DESIGN, 3e.

Parallel adder(7483)

Register A(74194)

C(7474)

Register Q(74194)

Multiplier Q(4 switches)

Multiplicand B(4 switches)

Counter P(74161)

PC 1 on count of 4

Q0

Cout

(a) Datapath block program

(b) Control state diagram

T0S 1

S 0

T1 T2 T3

Pc 1

Pc 0

T1: A ← 0, C ← 0, P ← 0, Q ← Multiplier T2: P ← P 1T2Q0 : A ← A B, C ← CoutT3: Shift right CAQ, C ← 0

Fig. 11-24 Binary Multiplier Circuit


digital design, 3e. - amazon s3s3.amazonaws.com/cramster-resource/662_n_8507.pdf · vcc pin 5 fig....

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