digital design: an embedded systems approach … s t −d s t+1 s t−d+1 clk audio_in audio_in_en...

Digital Design — Chapter 5 — Memories 7 September 2007

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Digital Design:An Embedded Systems Approach Using VHDL

Chapter 5Memories

Portions of this work are from the book, Digital Design: An Embedded Systems Approach Using VHDL, by Peter J. Ashenden, published by Morgan Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.

Digital Design — Chapter 5 — Memories 2

VHDL

General Concepts

A memory is an array of storage locations

Each with a unique addressLike a collection of registers, but with optimized implementation

Address is unsigned-binary encoded

n address bits ⇒ 2n locations

All locations the same size2n × m bit memory

0123456

2n–22n–1

m bits


2


VHDL

Memory Sizes

Use power-of-2 multipliersKilo (K): 210 = 1,024 ≈ 103

Mega (M): 220 = 1,048,576 ≈ 106

Giga (G): 230 = 1,073,741,824 ≈ 109

Example32K × 32-bit memoryCapacity = 1,025K = 1MbitRequires 15 address bits

Size is determined by application requirements


VHDL

Basic Memory Operationsa inputs: unsigned addressd_in and d_out

Type depends on applicationWrite operation

en = 1, wr = 1d_in value stored in location given by address inputs

Read operationen = 1, wr = 0d_out driven with value of location given by address inputs

Idle: en = 0

a(0)

… …a(1)

enwr

a(n–1)

d_in(0)

… …d_in(1)

d_in(m–1)

d_out(0)

…

…d_out(1)

d_out(m–1)


3


VHDL

Example: Audio Delay UnitSystem clock: 1MHzAudio samples: 8-bit signed, at 50kHz

New sample arrives when audio_in_en = 1Delay control: 8-bit unsigned ⇒ ms to delayOutput: audio_out_en = 1 when output ready

20µs

st

st−d

st+1

st−d+1

clk

audio_in

audio_in_en

audio_out

audio_out_en


VHDL

Audio Delay Datapath

Max delay = 255msNeed to store 255 × 50 = 12,750 samplesUse a 16K × 8-bit memory (14 address bits)

0

1a

d_in d_out

enwr

en Q

clk

×50–

audio_out

audio_in

delay

clk

count_en

addr_sel

mem_enmem_wr

8

14

14

14

16

16


4


VHDL

Audio Delay Control Section

Step 1: (idle state)audio_in_en = 0 ⇒ do nothingaudio_in_en = 1 ⇒ write memory using counter value as address

Step 2:Read memory using subtracter output as address, increment counter

11011Step 1–Step 2

00110Step 21Step 1

00000Step 10Step 1

audio_out_en

count_enmem_wrmem_enaddr_selNext stateaudio_in_en

State


VHDL

Wider Memories

Memory components have a fixed widthE.g., ×1, ×4, ×8, ×16, ...

Use memorycomponents inparallel to makea wider memory

E.g, three 16K×16components for a16K×48 memory

a(13…0)

enwr

d_in(15…0)

d_out(15…0)

a(13…0)

enwr

d_in(15…0)

d_out(15…0)

a(13…0)

enwr

d_in(15…0)

d_out(15…0)

d_out(31…16)

d_out(47…32)

d_out(15…0)

d_in(31…16)

d_in(47…32)

d_in(15…0)

a(13…0)

enwr


5


VHDL

More Locations

To provide 2n locations with 2k-location components

Use 2n/2k components

Address Aat offset A mod 2k

least-significant k bits of A

in component ⎣A/2k⎦most-significant n–k bits of Adecode to select component

01

2k–12k

2k+1

2×2k–12×2k

2×2k+1

3×2k–1

2n–2k

2n–2k +1

2n–1


VHDL

More Locations

Example:64K×8 memorycomposed of16K×8 components

a(13…0)

enwr

d_in(7…0)

d_out(7…0)

a(13…0)

enwr

d_in(7…0)

d_out(7…0)

a(13…0)

enwr

d_in(7…0)

d_out(7…0)

a(13…0)

enwr

d_in(7…0)

d_out(7…0)

d_out(7…0)

d_in(7…0)

a(13…0)

a(15…14)

en

wr

0123

0en 123


6


VHDL

Tristate DriversAllow multiple outputs to be connected together

Only one active at a timeRemaining outputs are high-impedance

Both output transistors turned off

Allow bidirectional input/output ports

output

+V

+V +V +V


VHDL

Memories with Tristate Ports

During writememory d drivers hi-Zmemory senses d

During readselected memory drives d

Fewer pins and wiresReduced cost of PCB

Usually not available within ASICs or FPGAs

a(13…0)

enwr

d(7…0)

a(13…0)

enwr

d(7…0)

a(13…0)

enwr

d(7…0)

a(13…0)

enwr

d(7…0)d(7…0)

a(13…0)

a(15…14)

en

wr

0en 123


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VHDL

Memory Types

Random-Access Memory (RAM)Can read and writeStatic RAM (SRAM)

Stores data so long as power is suppliedAsynchronous SRAM: not clockedSynchronous SRAM (SSRAM): clocked

Dynamic RAM (DRAM)Needs to be periodically refreshed

Read-Only Memory (ROM)CombinationalProgrammable and Flash rewritable

Volatile and non-volatile


VHDL

Asynchronous SRAM

Data stored in 1-bit latch cellsAddress decoded to enable a given cell

Usually use active-low control inputsNot available as components in ASICs or FPGAs

A

CEWEOE

D

WE

OE

CE

A

D stored data

tsu th

read data


8


VHDL

Asynch SRAM Timing

Timing parameters published in data sheetsAccess time

From address/enable valid to data-out valid

Cycle timeFrom start to end of access

Data setup and holdBefore/after end of WE pulseMakes asynch SRAMs hard to use in clocked synchronous designs


VHDL

Example Data Sheet


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VHDL

Synchronous SRAM (SSRAM)

Clocked storage registers for inputsaddress, data and control inputsstored on a clock edgeheld for read/write cycle

Flow-through SSRAMno register ondata output

clk

A

en

wr

D_in

D_out

a1

xx

xx M(a2)

a2


VHDL

Example: Coefficient Multiplier

Compute functionCoefficient stored in flow-through SSRAM

12-bit unsigned integer index for ix, y, ci 20-bit signed fixed-point

8 pre- and 8 post-binary point bits

Use a single multiplierMultiply ci × x × x

2xcy i ×=


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VHDL

Multiplier Datapath

D_in

A

SSRAM

en

wr

D_out

clkD

ce

Q

clk

D

ce

Q

clk

× y

ic_in

c_ram_wr

x_ce

c_ram_en

x

y_cemult_sel

clk

0

1

0

1


VHDL

Multiplier Timing and Control

step11, 1, 0, 0

01 step2

0, 0, 0, 1

step30, 0, 1, 1

y_ce

c_ram_en

start

clk

step1 step1 step2 step3 step1

x_ce

mult_sel


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VHDL

Pipelined SSRAM

Data output also has a registerMore suitable for high-speed systemsAccess RAM in one cycle, use the data in the next cycle

clk

A

en

wr

D_in

D_out

a1

xx

xx M(a2)

a2


VHDL

Memories in VHDL

RAM storage represented by an array signal

type RAM_4Kx16 is array (0 to 4095) of std_logic_vector(15 downto 0);signal data_RAM : RAM_4Kx16;...

data_RAM_flow_through : process (clk) isbeginif rising_edge(clk) thenif en = '1' thenif wr = '1' then

data_RAM(to_integer(a)) <= d_in; d_out <= d_in;else

d_out <= RAM(to_integer(a));end if;

end if;end if;

end process data_RAM_flow_through;


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VHDL

Example: Coefficient Multiplierlibrary ieee; use ieee.std_logic_1164.all,

ieee.numeric_std.all, ieee.fixed_pkg.all;

entity scaled_square isport ( clk, reset : in std_logic;

start : in std_logic;i : in unsigned(11 downto 0);c_in, x : in sfixed(7 downto -12);y : out sfixed(7 downto -12) );

end entity scaled_square;

architecture rtl of scaled_square is

signal c_ram_en, c_ram_wr, x_ce, mult_sel, y_ce : std_logic;signal c_out, x_out : sfixed(7 downto -12);signal y_out : sfixed(7 downto -12);

type c_array is array (0 to 4095) of sfixed(7 downto -12);signal c_RAM : c_array;

type state is (step1, step2, step3);signal current_state, next_state : state;


VHDL

Example: Coefficient Multiplier

begin

c_ram_wr <= '0';

c_RAM_flow_through : process (clk) isbeginif rising_edge(clk) thenif c_ram_en = '1' thenif c_ram_wr = '1' thenc_RAM(to_integer(i)) <= c_in;c_out <= c_in;

elsec_out <= c_RAM(to_integer(i));

end if;end if;

end if;end process c_RAM_flow_through;


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VHDL

Example: Coefficient Multipliery_reg : process (clk) isvariable operand1, operand2 : sfixed(7 downto -12);

beginif rising_edge(clk) thenif y_ce = '1' thenif mult_sel = '0' thenoperand1 := c_out; operand2 := x_out;

elseoperand1 := x_out; operand2 := y_out;

end if;y_out <= operand1 * operand2;

end if;end if;

end process y_reg;

y <= y_out;

state_reg : process ...next_state_logic : process ...output_logic : process ...

end architecture rtl;


VHDL

Pipelined SSRAM in VHDL

data_RAM_pipelined : process (clk) is

variable pipeline_en : std_logic;variable pipeline_d_out : std_logic_vector(15 downto 0);

beginif rising_edge(clk) thenif pipelined_en = '1' thend_out <= pipelined_d_out;

end if;pipeline_en := en;

if en = '1' thenif wr = '1' then

data_RAM(to_integer(a)) <= d_in; pipeline_d_out := d_in;else

pipeline_d_out := RAM(to_integer(a));end if;

end if;end if;

end process data_RAM_pipelined;

output register

SSRAM


14


VHDL

Generating SSRAM Components

Variations on SSRAM behaviorE.g., write-first, read-first or no-change on write cycleBurst accesses to successive locations

Not all synthesis tools recognize the same templatesUse a RAM core generator tool


VHDL

Example: RAM Core Generator


15


VHDL

Multiport Memories

Multiple address, data and control connections to the storage locationsAllows concurrent accesses

Avoids multiplexing and sequencing

ScenarioData producer and data consumer

What if two writes to a location occur concurrently?

Result may be unpredictableSome multi-port memories include an arbiter


VHDL

FIFO Memories

First-In/First-Out bufferConnecting producer and consumerDecouples rates of production/consumption

FIFOProducersubsystem

Consumersubsystem

Implementation usingdual-port RAM

Circular bufferFull: write-addr = read-addrEmpty: write-addr = read-addr

write

read


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VHDL

Example: FIFO Datapath

Equal = full or emptyNeed to distinguish between these states — How?

D_wr

A_wr A_rd

dual-portSSRAM

wr_en

D_rd

clk

rd_en

clk

counter8-bit

ce

reset

Q

clk

counter8-bit

ce

reset

Q

clk = equal

A_rd

A_wr

D_rd

clkwr_enD_wr

reset

rd_en


VHDL

Example: FIFO Control

Control FSM→ filling when write without concurrent read→ emptying when without concurrent writeUnchanged when concurrent write and read

full = filling and equal

empty = emptying and equalwr_en, rd_en

emptying

filling

1, 0 0, 1


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VHDL

Multiple Clock Domains

Need to resynchronize data that traverses clock domains

Use resynchronizing registers

May overrun if sender's clock is faster than receiver's clockFIFO smooths out differences in data flow rates

Latch cells inside FIFO RAM written with sender's clock, read with receiver's clock


VHDL

Dynamic RAM (DRAM)

Data stored in a 1-transistor/1-capacitor cellSmaller cell than SRAM, so more per chipBut longer access time

Write operationpull bit-line high or low (0 or 1)activate word line

Read operationprecharge bit-line to intermediate voltageactivate word line, and sense charge equalizationrewrite to restore charge

bit line

word line


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VHDL

DRAM Refresh

Charge on capacitor decays over timeNeed to sense and rewrite periodically

Typically every cell every 64ms

Refresh each location

DRAMs organized into banks of rowsRefresh whole row at a time

Can’t access while refreshingInterleave refresh among accessesOr burst refresh every 64ms


VHDL

Read-Only Memory (ROM)

For constant data, or CPU programsMasked ROM

Data manufactured into the ROMProgrammable ROM (PROM)

Use a PROM programmerErasable PROM (EPROM)

UV erasableElectrically erasable (EEPROM)Flash RAM


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VHDL

Combinational ROM

A ROM maps address input to data outputThis is a combinational function!Specify using a table

Example: 7-segment decoder

000000016–3111011015

100000010–1511001104

1101111910011113

1111111810110112

0000111700001101

1111101601111110

ContentAddressContentAddressabcdefg

BCD0BCD1BCD2BCD3blank

A0A1A2A3A4

D0D1D2D3D4D5D6


VHDL

Example: ROM in VHDLlibrary ieee; use ieee.numeric_std.all;

architecture ROM_based of seven_seg_decoder is

type ROM_array isarray (0 to 31) of std_logic_vector ( 7 downto 1 );

constant ROM_content : ROM_array:= ( 0 => "0111111", 1 => "0000110",

2 => "1011011", 3 => "1001111",4 => "1100110", 5 => "1101101",6 => "1111101", 7 => "0000111",8 => "1111111", 9 => "1101111"10 to 15 => "1000000",16 to 31 => "0000000" );

begin

seg <= ROM_content(to_integer(unsigned(blank & bcd)));

end architecture ROM_based;


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VHDL

Flash RAM

Non-volatile, readable (relatively fast), writable (relatively slow)Storage partitioned into blocks

Erase a whole block at a time, then write/readOnce a location is written, can't rewrite until erased

NOR FlashCan write and read individual locationsUsed for program storage, random-access data

NAND FlashDenser, but can only write and read block at a timeUsed for bulk data, e.g., cameras, memory sticks


VHDL

Memory Errors

Bits in memory can be flippedHard error

The chip is brokenE.g., manufacturing defect, wear (in Flash)

Soft errorStored data corrupted, but cell still worksE.g., from atmospheric neutrons

Soft-error ratefrequency of occurrence


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VHDL

Error Detection using Parity

Add a parity bit to each locationOn write access

compute data parity and store with dataOn read access

check parity, take exception on errorIf we could tell which bit flipped

correct by flipping it back, then write back to memory locationCan’t do this with parity


VHDL

Error-Correcting Codes (ECC)

Allow identification of the flipped bitHamming Codes

E.g., for single-bit-error correction of N-bit word, need log2N + 1 extra bits

Example: 8-bit word, d1... d812-bit ECC code, e1...e12e1, e2, e4, e8 are check bits, the rest data

d1d2d3d4d5d6d7d8

e1e2e3e4e5e6e7e8e9e10e11e12


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VHDL

Hamming Code Example

0011e12

1101e11

0101e10

1001e9

1110e7

0110e6

1010e5

1100e3

0001e8

0010e4

0100e2

1000e1

e1 = e3 ⊕ e5 ⊕ e7 ⊕ e9 ⊕ e11

e2 = e3 ⊕ e6 ⊕ e7 ⊕ e10 ⊕ e11

e4 = e5 ⊕ e6 ⊕ e7 ⊕ e12

e8 = e9 ⊕ e10 ⊕ e11 ⊕ e12

Every data bit covered by two or more check bitsOn write: Compute check bits and store with data

d1d2d3d4d5d6d7d8

e1e2e3e4e5e6e7e8e9e10e11e12


VHDL

Hamming Code Example

0011e12

1101e11

0101e10

1001e9

1110e7

0110e6

1010e5

1100e3

0001e8

0010e4

0100e2

1000e1

On read: Recompute check bits and XOR with read check bits

result called the syndrome

0000 => no errorIf data bit flipped

covering bits of syndrome are 1= binary code of flipped ECC bit

If stored check bit flippedthat bit of syndrome is 1

On error, unflip bit and rewrite memory location


23


VHDL

Multiple-Error Detection

What if two bits flipsyndrome identifies wrong bit, or is invalid

One extra check bit allowssingle-error correction, double-error detection

3.9%103.5%9256

7.0%96.3%8128

13%811%764

22%719%632

38%631%516

63%550%48

OverheadCheck bitsOverheadCheck bitsNDouble-bit detectionSingle-bit correction


VHDL

Summary

Memory: addressable storage locationsRead and Write operationsAsynchronous RAMSynchronous RAM (SSRAM)Dynamic RAM (DRAM)Read-Only Memory (ROM) and FlashMultiport RAM and FIFOsError Detection and Correction

Hamming Codes

digital design: an embedded systems approach … s t −d s t+1 s t−d+1 clk audio_in audio_in_en...

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