digital integrated circuits lecture 15: nonideal...

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Digital Integrated CircuitsLecture 15: NonidealTransistors

Chih-Wei Liu

VLSI Signal Processing LAB

National Chiao Tung University

[email protected]


Outline

Transistor I-V ReviewNonideal Transistor Behavior

Velocity SaturationChannel Length ModulationBody EffectLeakageTemperature Sensitivity

Process and Environmental VariationsProcess Corners


Ideal Transistor I-V

Shockley 1st order transistor models

( )2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V VVI V V V V V

V V V V

β

β

⎧⎪ <⎪⎪ ⎛ ⎞= − − <⎜ ⎟⎨ ⎝ ⎠⎪⎪

− >⎪⎩


Ideal vs. Simulated nMOS I-V Plot

180 nm TSMC process

Ideal Modelsβ = 155(W/L) μA/V2

Vt = 0.4 VVDD = 1.8 V

Ids (μA)

Vds0 0.3 0.6 0.9 1.2 1.5 1.8

100

200

300

400

Vgs = 0.6Vgs = 0.9

Vgs = 1.2

Vgs = 1.5

Vgs = 1.8

0 V ds

0 0 .3 0 .6 0 .9 1 .2 1 .5

V g s = 1 .8

Ids (μA )

0

50

100

150

200

250

V g s = 1 .5

V g s = 1 .2

V g s = 0 .9

V g s = 0 .6

BSIM 3v3 SPICE models


Simulated nMOS I-V Plot

180 nm TSMC processBSIM 3v3 SPICE modelsWhat differs?

Less ON currentNo square lawCurrent increasesin saturation

Vds

0 0.3 0.6 0.9 1.2 1.5

Vgs = 1.8

Ids (μA)

0

50

100

150

200

250

Vgs = 1.5

Vgs = 1.2

Vgs = 0.9

Vgs = 0.6


Velocity Saturation

We assumed carrier velocity is proportional to E-fieldv = μElat = μVds/L

At high fields, this ceases to be trueCarriers scatter off atomsVelocity reaches vsat

Electrons: 6-10 x 106 cm/sHoles: 4-8 x 106 cm/s

Better model

Esat00

slope = μ

Elat

ν

2Esat3Esat

νsat

νsat / 2

latsat sat

lat

sat

μ μ1

Ev v EEE

= ⇒ =+


Vel Sat I-V Effects

Ideal transistor ON current increases with VDD2

Velocity-saturated ON current increases with VDD

Real transistors are partially velocity saturatedApproximate with α-power law modelIds ∝ VDD

α

1 < α < 2 determined empirically

( ) ( )2

2

ox 2 2gs t

ds gs t

V VWI C V VL

βμ−

= = −

( )ox maxds gs tI C W V V v= −


α-Power Model

Ids (μA)

Vds0 0.3 0.6 0.9 1.2 1.5 1.8

100

200

300

400

Vgs = 0.6Vgs = 0.9

Vgs = 1.2

Vgs = 1.5

Vgs = 1.8

0

α-lawSimulated

Shockley

0 cutoff

linear

saturation

gs t

dsds dsat ds dsat

dsat

dsat ds dsat

V VVI I V VV

I V V

⎧ <⎪⎪= <⎨⎪⎪ >⎩

( )

( ) / 22dsat c gs t

dsat v gs t

I P V V

V P V V

α

α

β= −

= −


Channel Length Modulation

Reverse-biased p-n junctions form a depletion region

Region between n and p with no carriers

Width of depletion Ld region grows with reverse bias

Leff = L – Ld

Shorter Leff gives more current

Ids increases with Vds

Even in saturation n+

p

GateSource Drain

bulk Si

n+

VDDGND VDD

GND

LLeff

Depletion RegionWidth: Ld


Chan Length Mod I-V

λ = channel length modulation coefficientnot feature sizeEmpirically fit to I-V characteristics

( ) ( )21

2ds gs t dsI V V Vβ λ= − +

Ids (μA)

Vds0 0.3 0.6 0.9 1.2 1.5 1.8

100

200

300

400

Vgs = 0.6Vgs = 0.9

Vgs = 1.2

Vgs = 1.5

Vgs = 1.8

0


Body Effect

Vt: gate voltage necessary to invert channelIncreases if source voltage increases because source is connected to the channelIncrease in Vt with Vs is called the body effect


Body Effect Model

φs = surface potential at threshold

Depends on doping level NA

And intrinsic carrier concentration ni

γ = body effect coefficient

( )0t t s sb sV V Vγ φ φ= + + −

2 ln As T

i

Nvn

φ =

sioxsi

ox ox

2q2q A

A

Nt NCε

γ εε

= =


OFF Transistor Behavior

What about current in cutoff?Simulated resultsWhat differs?

Current doesn’t go to 0 in cutoff

Vt

Sub-threshold

Slope

Sub-thresholdRegion

SaturationRegion

Vds = 1.8

Ids

Vgs

0 0.3 0.6 0.9 1.2 1.5 1.8

10 pA100 pA

1 nA

10 nA

100 nA1 μA

10 μA100 μA

1 mA


Leakage Sources

Subthreshold conductionTransistors can’t abruptly turn ON or OFF

Junction leakageReverse-biased PN junction diode current

Gate leakageTunneling through ultrathin gate dielectric

Subthreshold leakage is the biggest source in modern transistors


Subthreshold Leakage

Subthreshold leakage exponential with Vgs

n is process dependent, typically 1.4-1.5

0e 1 egs t ds

T T

V V Vnv v

ds dsI I− −⎛ ⎞

= −⎜ ⎟⎜ ⎟⎝ ⎠

2 1.80 eds TI vβ=


DIBL

Drain-Induced Barrier LoweringDrain voltage also affect Vt

High drain voltage causes subthreshold leakage to ________.

ttdsVVVηt t dsV V Vη′ = −


DIBL

Drain-Induced Barrier LoweringDrain voltage also affect Vt

High drain voltage causes subthreshold leakage to increase.

ttdsVVVηt t dsV V Vη′ = −


Junction Leakage

Reverse-biased p-n junctions have some leakage

Is depends on doping levelsAnd area and perimeter of diffusion regionsTypically < 1 fA/μm2

e 1D

T

Vv

D SI I⎛ ⎞

= −⎜ ⎟⎜ ⎟⎝ ⎠

n well

n+n+ n+p+p+p+

p substrate


Gate Leakage

Carriers may tunnel thorough very thin gate oxidesPredicted tunneling current (from [Song01])

Negligible for older processesMay soon be critically important

VDD

0 0.3 0.6 0.9 1.2 1.5 1.8

JG (A

/cm2

)

10-9

10-6

10-3

100

103

106

109

tox

0.6 nm0.8 nm

1.0 nm1.2 nm

1.5 nm

1.9 nm

VDD trend


Temperature Sensitivity

Increasing temperatureReduces mobilityReduces Vt

ION decreases with temperatureIOFF increases with temperature

Vgs

dsI

increasingtemperature


So What?

So what if transistors are not ideal?They still behave like switches.

But these effects matter for…Supply voltage choice

Logical effort

Quiescent power consumption

Pass transistors

Temperature of operation


Parameter Variation

Transistors have uncertainty in parametersProcess: Leff, Vt, tox of nMOS and pMOSVary around typical (T) values

Fast (F)Leff: shortVt: lowtox: thin

Slow (S): oppositeNot all parameters are independentfor nMOS and pMOS

nMOS

pMO

S

fastslow

slow

fast

TT

FF

SSFS

SF


Environmental Variation

VDD and T also vary in time and spaceFast:

VDD: ____T: ____

70 C1.8TS

FTemperatureVoltageCorner


Environmental Variation

VDD and T also vary in time and spaceFast:

VDD: highT: low

70 C1.8T125 C1.62S

0 C1.98FTemperatureVoltageCorner


Process Corners

Process corners describe worst case variationsIf a design works in all corners, it will probably work for any variation.

Describe corner with four letters (T, F, S)nMOS speed

pMOS speed

Voltage

Temperature


Important Corners

Some critical simulation corners include

Pseudo-nMOS

Subthresholdleakage

Power

Cycle time

TempVDDpMOSnMOSPurpose


Important Corners

Some critical simulation corners include

??FSPseudo-nMOS

SFFFSubthresholdleakage

FFFFPower

SSSSCycle time

TempVDDpMOSnMOSPurpose

digital integrated circuits lecture 15: nonideal...

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