digital pulse processing for physics applications

Tools for Discovery

Digital Pulse Processing

for Physics Applications

Triumf – December 7th, 2011

Carlo Tintori

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited

Outline

• Overview on the CAEN Digitizer family

• Description of the hardware of the waveform digitizers

• Multi board systems

• Use of the digitizers with Digital Pulse Processing for physics applications

• Comparison between the traditional analog acquisition chains and the new fully digital approach

• DPP algorithms:

• Zero suppression

• Pulse Height Analysis

• Charge Integration

• Pulse Shape Discrimination

• Time measurement


• The principle of operation of a waveform digitizer is the same as the digital oscilloscope: when the trigger occurs, a certain number of samples is saved into one memory buffer (acquisition window)

• However, there are important differences:

– no dead-time between triggers (Multi Event Memory)

– multi-board synchronization for system scalability

– high bandwidth data readout links

– on-line data processing (FPGA or DSP)

PRE POST TRIGGER

ACQUISITION WINDOW

Sampling Clock

TRIGGER

Time

TIME STAMP

S[0]

S[n-1]

S[1]

S[2]

S[3]

Memory Buffer

Digitizers vs Oscilloscopes


CAEN Digitizers Highlights

• From 2 to 64 channels

• Up to 5 GS/s sampling rate - Up to 14 bit

• FPGA firmware for Digital Pulse Processing

• VME, NIM, Desktop form factors

• VME64X, Optical Link (CONET), USB 2.0

• Memory buffer: up to 10MB/ch (max. 1024 events)

• Multi-board synchronization and trigger distribution

• Programmable PLL for clock synthesis

• Programmable digital I/Os

• Analog output with majority or linear sum

• FPGA firmware for Digital Pulse Processing

• Software for Windows and Linux


Digitizers Table

Architecture


CLK-IN

TRG IN

TRG OUT (3)

S IN (3)

LO

CA

L B

US

SSRAM

VME (1)

PLL

CONET

INPUTi

SY

NC

GT

RG

ITR

G

TR

GR

EQ

GPIO (1)16

8 8

ADC14bit @

100MS/s

DAC CHANNEL

FPGA

(AMC)

INTERFACE

FPGA

(ROC)USB (2)

OSC

CLK-OUT (1)

(1) VME boards only

(2) Desktop/NIM boards only

(3) for Desktop/NIM baords, TRG-OUT = GPO, S-IN = GPI

50MHz

x1

SCLK

TRGCLK

xN

DACMON (1)


Multi-board Synchronization

What does synchronization mean?

1. same sampling clock propagated to all flash ADCs:

External clock in/out(1); first board can act as a clock master and distributes the clock to many slaves in daisy chain

PLL for clock synthesis from an external clock reference

Programmable Phase Adjust for cable delay compensation

2. same T zero for the time stamps: Sync Input for a simultaneous start/stop of the acquisition and/or for time

stamp reset

Sync Distribution through the boards in daisy-chain (via TrgOut)

Use of the first trigger to start the acquisition

3. trigger propagation and correlation: External Trigger In/Out (NIM/TLL on LEMO connectors)

Global or individual Trigger propagation through LVDS GPIOs(1)

Neighbour triggering options for segmented and clove detectors

4. readout synchronization and event alignment(2): Daisy Chainable Busy output (programmable almost full level) (1)

Daisy Chainable Veto input (trigger inhibit) (1)

Interrupt request on programmable memory occupancy level

(1) for VME modules only (2) New firmware currently under test


Multi-board Synchronization: example 1

• Requirements: N boards triggered by a common external trigger. All channels trigger at the same time.

• Setup: external trigger goes to TRGIN of the 1st board; daisy chain TRGIN-TRGOUT to propagate the trigger as well as the start of run

• Start of Run sequence: 1. External trigger vetoed on the 1st board (software setting)

2. All boards armed to start with TRGIN edge

3. SW trigger on the 1st board to start run through TRGIN-TRGOUT chain

4. Veto of External trigger disabled; triggers start to acquire events

(note: run can also start with the 1st hardware trigger)

• Event alignment: Busy signal (almost full) propagated to last board (on LVDS I/Os) and output on its TRGOUT (NIM or TTL), then used to inhibit external trigger (either at the external trigger source or at SIN of the 1st board used as trigger VETO)



GLOBAL

TRIGGER

TRGOUT

CLOCK DISTRIB.

Progr. Phase shift

TRGIN-TRGOUT

start of run + global trigger

TRGIN TRGIN

BUSYOUT

GBUSY

INHIBIT

VETO

TRGOUT = BUSY

Used to stop triggers

BUSYIN

BUSY IN-OUT

Used to propagate Busy



• Requirements: N boards with independent triggers (OR of the local channel self-triggers as well as N independent external TRGIN signals)

• Setup: daisy chain SIN-TRGOUT to propagate the start of run; TRGIN can be used for the external triggers (independent board by board)

• Start of Run sequence: 1. All boards armed to start when SIN=1

2. SW Start on the 1st board to start run through SIN-TRGOUT chain

(note: run can also start by an hardware signal going high at SIN of the 1st board)

• Event alignment: Busy signal (almost full) propagated to last board (on LVDS I/Os), fed into veto input of the 1st board and propagated to all the boards in daisy chain (on LVDS I/Os)



START

STOP

TRGOUT

CLOCK DISTRIB.

Progr. Phase shift

SIN-TRGOUT

Start/stop of run

TRGIN[0]

SIN

BUSYOUT

SIN

BUSYIN

BUSY IN-OUT


TRGIN[1] TRGIN[2]

VETOOUT

VETOIN

VETO IN-OUT

Used to propagate Veto

GBUSY fed back into

VETO daisy chain

GBUSY

VETOIN



• Requirements: N boards triggered by a global trigger = OR of all channel self-triggers (one channel triggers all)

• Setup: the TRGOUT of each board goes into an external OR logic, whose output goes back to the TRGIN of all boards (parallel fan-out)

• Start of Run sequence: 1. All boards armed to start with TRGIN edge

2. SW trigger on the 1st board to start run through the OR + fan-out

3. Self-triggers start to be ORed and acquire events in all boards

• Event alignment: Busy signal (almost full) propagated to last board (on LVDS I/Os), fed into veto input of the 1st board and propagated to all the boards in daisy chain (on LVDS I/Os)



TRGOUT[0]

CLOCK DISTRIB.

Progr. Phase shift GLOBAL TRIGGER =

OR of TRGOUT[n]

TRGIN[0]

BUSYOUT

BUSYIN

BUSY IN-OUT


TRGIN[1] TRGIN[2]

VETOOUT

VETOIN

VETO IN-OUT

Used to propagate Veto

GBUSY fed back into

VETO daisy chainGBUSY

VETOIN

ORFAN

OUT

xN



• Requirements: N boards with individual self-triggers; coincidence and/or propagation on channel basis (each channel can be triggered by a combination of any other)

• NOTE: individual triggers are only available with DPP firmware

• Setup: the individual TRGOUTs of each channel go into an external trigger logic (i.e. CAEN V1495) through the LVDS I/Os. The trigger logic generates the individual TRGINs of each channel and feeds them into the LVDS I/Os

• Start of Run sequence: 1. All boards armed to start when SIN=1

2. SW Start on the 1st board to start run through SIN-TRGOUT chain

(note: run can also start by an hardware signal generated by the external trigger logic sent to SIN of all the boards in parallel)

• Event alignment: usually not necessary; can be managed by the external logic that uses the Busy of each board (on TRGOUT) to inhibit individual triggers



TRGOUT

CLOCK DISTRIB.

Progr. Phase shiftSTART/STOP

SINSININDIVIDUAL TRGIN (TRG VALIDATION)

(one per channel)

INDIV.

TRGIN

INDIV.

TRGOUT

88

INDIV.

TRGIN

INDIV.

TRGOUT

88

INDIV.

TRGIN

INDIV.

TRGOUT

88

8

8

8

8

8

8

8

Nx8

8

8

8

8

8

8

8

8

Nx8

V1495

CLOCK going into

one V1495 input

REFCLK

REFCLK

INDIVIDUAL SELF-TRIGGER

(one per channel)

SIN-TRGOUT

Run propagation


Coincidence and Event correlation (HW)

Hardware approach

• Propagate local triggers from each channel to the others within the board

• TR-TV mode: triggers from other channels (trigger requests) can be used as trigger validation

• Apply individual trigger masks and simple combinatorial logics on board (AND, OR, Majority)

• Use GPIOs on the front panel to propagate individual trigger inputs/outputs from/to external logic boards (e.g. V1495)

ADCCOMP

Threshold

Inputs

FPGA

CHANNELS

Lo

ca

l B

us

FPGA

TRIGGER

LOGIC

(AND, OR, MAJ)I/Os

ACQ

MEM

EXTERNAL

TRIGGER

LOGIC

V1495

LOCAL TRG

DIGITIZER

from/to other

Digitizers

FILTERS


Trigger Logic Block Diagram

TRG IN

TRG OUT

S IN

RUN

GTRG

ITRG(n)MA

SK

-Ci

MA

SK

-Ci

MA

SK

-Cn

MA

SK

-O

AN

D/O

RA

ND

/OR

AN

D/O

RA

ND

/OR

AN

D/O

R

TIME_RESET

SYNC

Channel

Trigger

Logic

MA

SK

-G

EITRG(n)

OVTHTHRESHOLD(n)

ADC

CHnTRGREQ(n)

TT

FILTER

SSRAM

8

8

GPIO

CTRL

SWTRG

16

RUN

CTRL

+

COMMUNICATION

INTERFACE

GPIO

VME/USB

CONET

Acquisition

Logic

GP

CL

EA

R

GP

TR

GO

GP

TR

GI

GP

ST

AR

T

SW

ST

AR

T

DATA

PROCESSING

READOUT DATA

ACQTRG

ACQRUN

x8x8

DRDY,

BUSY...

READOUT

CONTROLLER

DRDY,

BUSY...


Coincidence and Event correlation (SW)

Software approach

• Read all events as long as you have enough bandwidth (i.e. make data suppression as late as you can): preserve the information!

• In list mode, the bandwidth requirement is very low (e.g. 8 bytes per event). Example: 8 channels at 100 KHz trigger rate gives 6.4 MB/s.

• In a modern multi-core computers, the readout process takes a small fraction of the CPU resources

• Time stamped events allow for easy and flexible software coincidence, anticoincidence, correlation, etc.


A real setup using SW coincidence

ILL Grenoble (ref. Paolo Mutti):

New Trigger-Less Acquisition System for Large Detector Arrays

Readout CPU for Data

Concentrator Digitizers

(V1724) Sync Logic


Time Frame Spectroscopic Imaging (I)

Need to get subsequent spectroscopic images of a sample (1024 frames)

• For each frame multichannel spectra collection with coincidence capabilities is required

• Once a frame has been acquired, the system has to save the spectra, reset the histograms and get ready to restart the measurement with no dead time between frames

• The frame change is synchronous with an external signal


Time Frame Spectroscopic Imaging (II)

CHANNEL A

CHANNEL B

1 2 3 4 5 6 7 8

1 2 3 4 6 7 85 9 10

FRAME1EXT SYNC

FRAME2

T1A E1A

T2A E2A

T3A E3A

T4A E4A

T5A E5A

T6A E6A

T7A E7A

T8A E8A

T1B E1B

T2B E2B

T3B E3B

T4B E4B

T5B E5B

T6B E6B

T7B E7B

T8B E8B

T9B E9B

T10B E10B

LIST - A LIST - B

EOF Marker

EOF Marker

EOF Marker

EOF Marker

• On-board DPP-PHA processes the input pulses and produces a list of events (Energy & Timestamp)

• The DAQ software looks for coincidence using the timestamps and generates histos

• The External Sync signal forces the boards to produce a “End of Frame” marker in the data list

• The DAQ software recognizes the marker and closes the current frame opening the next one

E1B

E5B

E2A

E4AFRAME 1 - CHA

FRAME 1 - CHB

E8B

E10B

E5A

E8AFRAME 2 - CHA

FRAME 2 - CHB

DPP-PHA

DAQ

SW

Time Frame Spectroscopic Imaging (III)

32 channels, 14 bit 100 MS/s

with DPP-PHA (N6724)

HV power supply

High-throughput readout via

optical link (300 kcps/ch)

Synchronous Histograms

collection and frame switch via

daisy chain

TEST SETUP


Traditional chain for spectroscopy

DECAY TIMERISE TIME

TIME Q = ENERGY

PEAK AMPLITUDE = ENERGY

ZERO CROSSING

This delay doesn’t depend

on the pulse amplitude

DETECTOR

PREAMPLIFIER

SHAPING AMPLIFIER

TIMING AMPLIFIER

CFD

CFD OUTPUT

• Typically used with semiconductor detectors (Si, Ge)

• The preamp. output signal is rather slow (typ. decay time = 50us)

• Very high energy resolution (good S/N ratio)


TIME Q = ENERGY

ZERO CROSSING

DETECTOR

CFD

GATE

DELAYED SIGNALCHARGE

INTEGRATION

• Typ. used with scintillators + PMTs or SiPMs

• The preamplifier is optional (the gain is already in the PMT)

• Fast signals (typ. 10-100ns)

Transimpedance

Preamplifier

(optional)

SPLITTER

DETECTOR

ENERGY

POSITION,

IDENTIF.

TIMING

COUNTINGTHRESHOLDS

DISCRIMINATOR

TDC

SCALER

LOGIC

UNIT

Gate

QDCDelay

Line

Traditional chain: another example trans-impedance (current sensitive) preamplifier


• Traditionally, the acquisition chains for radiation detectors are made out of mainly analog circuits; the A to D conversion is performed at the very end of the chain

• Nowadays, the availability of very fast and high precision flash ADCs permits to design acquisition systems in which the A to D conversion occurs as close as possible to the detector

• Once digitized, the signal can be processed using a variety of algorithms and filters in order to extract the information related to the physic events

• The data throughput is extremely high: it is no possible to transfer row data to the computers and make the analysis off-line!

Digitizers for Physics Applications

Example 1 with Mod720 (continuous acq.)

1 sample = 12 bit = 1.5 byte

1 channel = 1.5 byte @ 250MHz = 375 MB/s

1 VME board = 8 channels = 3 GB/s !!!

Example 2 with Mod720 (triggered acq.)

Record length = 2s (500 smp) = 750 Bytes/ch

Trigger Rate = 10 KHz

1 VME board = 60 MB/s


• Using digitizers as waveform recorders can produce a large amount of data to be transferred from the acquisition board to a mass storage device

• The data throughput can be extremely high: it may be no possible to transfer raw data to computers and make the analysis off-line!

• On-line Digital Pulse Processing is needed to extract only the information of interest reducing the data throughput

• The aim of the DPP is to provide FPGA algorithms able to make in digital the same functions of analog modules such as Shaping Amplifiers, Discriminators, QDCs, Peak Sensing ADCs, TDCs, Scalers, Coincidence Units, etc.

• Three main DPP firmware have been developed so far:

DPP-PHA (Pulse Height Analysis)

DPP-CI (Charge Integration)

DPP-PSD (Pulse Shape Discrimination)

Raw waveform mode: Limits


• One single board can do the job of several analog modules

• Full information preserved: A/D conversion as early as possible, data reduction as late as possible

• Reduction in size, cabling, power consumption and cost per channel

• High reliability and reproducibility

• Flexibility (different digital algorithms can be designed and loaded at any time into the same hardware)

Benefits of the digital approach


• With the standard firmware, the digitizer operates in oscilloscope mode: with the trigger, the list of samples (raw data) belonging to the acquisition window is saved to the memory of the board

• The trigger can be external or internal (threshold crossing); in both cases, it is common to all the channels

With the DPP Firmware, you can:

• Identify input pulses and generate a local trigger on them

• Calculate the time of arrival of the trigger

• Subtract the baseline

• Calculate the energy (usually pulse height or charge)

• Build an event made of a configurable combination of Trigger Time Stamp, Pulse Height/Charge and raw waveforms (i.e. series of ADC samples belonging to a programmable size acquisition window)

• Save events into a memory buffer and manage the readout through the Optical Link, USB or VME

• Detect pile-up conditions and manage count loss (dead-time)

• Implement coincidences between channels within the board as well as across different boards

Purpose of the DPP firmware


Acquisition mode: raw waveform vs DPP

INPUT

TIMING

FILTER

MEAN

ZCROSS

SUM

Trigger

TIME STAMP

CHARGE

BASELINE

S1

S2

S3

S4

TIME STAMP

BASELINE

CHARGE

EVENT DATA

Threshold

Leading Edge

TRAPEZ HEIGHT

SAMPLES

HEIGHT

INPUT

S1

S2

S3

S4

S5

S6

S7

Sn

Threshold

Trigger

Acquisition Window

EVENT DATASTD FW

DPP FW

Typ. Nsample > 1K

Typ. Nsample < 100


ZLE


ZLE topics

• The zero suppression (Zero Length Encoding) in a waveform digitizer consists in removing from the acquisition window the parts or the waveform that don’t contain useful information

• DPP only used for the pulse identification (Region Of Interest) and not to extract relevant quantities from the waveforms

• Typically used in beam experiments where the trigger is common to all channels, but only few of them contains events

• Available in the standard firmware of the x724, x720, x721 and x731; current version of the ZLE suffers from a readout bandwidth reduction

• A new ZLE algorithm that guarantees the best readout performances has been development in the x751 for the XMASS experiment

• The same algorithm will be developed for the x720


ZLE example

ROI-2suppressed ROI-3

LBW OVT LAW

ROI-1suppressed suppressed suppressed

Acquisition Window (programmable size with pre and post trigger)

T0 NS1

LBW

OVT

LAW

Look Back Window: programmable size

OverThreshold: lasts as long as the signal is over threshold

Look Ahead Window: programmable size; can be retriggered

ZLE threshold

T0

NS1

NG1

samples

of

ROI-1

NG1 NS2 NG2 NS3 NG3

NS2

NG2

samples

of

ROI-2

NS3

NG3

samples

of

ROI-3

Readout Data

NS Number of skipped samples belonging to the suppressed region

NG Number of good samples belonging to the ROI

T0 Time Stamp of the first sample of the Acquisition Window

NS4

NS4


XMASS: ZLE + GB/s Readout

• 64 V1751 modules in 4 VME crates • 512 channels (10 bit @ 1GHz) • 4 A3818s 4 link PCIe cards • 16 parallel CONET links • 4 digitizers daisy chained • Readout Bandwidth = ~2 MB/s/ch • Total aggregate throughput = ~ 1GB/s

A3818 PCIe 8x CONET Controller

A3818

A3818

A3818

A3818


DPP-PHA


DPP-PHA topics

• Digital implementation of the shaping amplifier + peak sensing ADC (Multi-Channel Analyzer)

• Charge sensitive preamplifier directly connected to the digitizer

• Implemented in the 14 bit, 100MSps digitizers (mod. 724)

• Provides pulse height, time stamp (10ns) and optionally raw data

• Pile-up rejection, Baseline restoration, ballistic deficit correction

• Low dead time => high counting rate (up to 1Mcps)

• Best suited for high resolution spectroscopy (HPGe and Si detectors)

• Also suitable for homeland security and biomedical applications

• Can work with segmented detectors (synchronizations, coincidences and neighbour triggering)


DPP-PHA Block Diagram

DECIMATOR

RC-(CR)2

COMP

TRAPEZOIDAL

FILTER

TRG & TIMING

FILTER

ARMED

TRIGGER

BASELINE

Threshold

SUB

INPUT

TIME STAMP

ENERGY

CLK

PEAK

COUNTER

Polarity

stop

Sync

reset

MEMORY

BUFFERS

ADC

MEMORY

MANAGER

READOUT

INTERF.

ZERO

CROSS

enable

wa

ve

form

s

• Decimator: reduces sampling rate and increases resolution

• Trigger & Timing Filter: indentifies pulses and generates triggers and time stamps

• Energy Filter: shapes the input signal (trapezoid), restores the baseline and calculates the pulse height

• Memory Manager: builds the events as a combination of time stamp, energy and waveforms (samples)


DPP-PHA signals

INPUT

TT FILTER

ARMED

threshold

TRIGGER

hold-off

TIME STAMP

ENERGY

flat top

TRAPEZ. FILTER

PEAKING

baseline

rise time

peaking time


Trigger and Timing Filter

• Pulse triggering is the basis for all DPP and Zero Suppression algorithms

• Fast Shaping filter: digital version of the RC-CRN filter (N=1, 2)

• Immune to baseline fluctuation and low frequency noise (ground loop)

• Pulse identification also with the presence of pile-up

• High frequency noise rejection (RC smoothing filter)

• Can operate as a digital CFD

• Zero crossing for precise timing information

• Off-line interpolation to overcome the sampling period granularity

• Zero crossing of CFD can also be used for Rise Time Discrimination (identification of double pulses piling up within their rise time)


Energy Filter

• The trapezoidal shaper (Moving Window Deconvolution) is the digital version of the gaussian shaper of the analog spectroscopy amplifiers

• The rise/fall time of the trapezoid corresponds to the shaping time: higher rise times result in better resolution but also higher probability of pile-up (dead time)

• Also the trapezoidal shaping requires pole-zero cancellation (controlled by a digital parameter that represents the exponential decay time)

• The baseline is calculated by averaging a programmable number of samples before the start of the trapezoid

• Flat top duration, peaking time (position of the peak in the flat top) and peaking averaging are also programmable for an optimum ballistic deficit correction


Pile-up in the Trapezoidal Filter

• Case 1: T > TTR+TTF (2nd trapezoid starts on the falling edge of the 1st one). Both energies are good (no pile-up events)

• Case 2: ~TPR < T < TTR+TTF (2nd trapezoid starts on the rising edge or flat top

of the 1st one). Pulse height calculation is not possible, no energy information is available (pile-up events); still two time stamps.

• Case 3: T < ~TPR (input pulses piling up on their rising edge). The TT filter doesn’t distinguish the double pulse condition. Only one event is recorded (energy sum). The Rise Time Discriminator might mitigate this unwanted effect.

trapezoid

T1 T2trigger

TT filter

input

peaking

E1

E2

T1 T2

T1

E1

T2

E2

readout

T1

0T2

0

readout

T1

T1

readout

E1

E1TTF

TPR

TTR


Dead Time in the DPP-PHA

• Unlike the analog chain, in the DPP-PHA there is no conversion time

• The A/D conversion and the pulse processing is always alive; dead time in the energy filter is only given by the trapezoid overlap (Trise + Tflat)

• Although pile-up causes the loss of energy values, the timestamps is given for almost all pulses: therefore, the true rate can be calculated

• DeadTime = RealTime * (Energy Count / Time-Stamp Count)

• Double pulse resolution Rise Time (two pulses separated by at least the pulse rise time can be distinguished)

• The Rise Time Discriminator allows double pulses piling up on the rising edge to be detected and counted twice (the relevant energies are discarded)

• Residual multiple pulses that cannot be distinguished (despite the RTD) can be counted on a statistical basis

• The x724+DPP-PHA operates in List Mode and the histogram is calculated off-line: the ‘dead-time’ correction is done by the readout software that uses the time stamps of the missed energies in order to dynamically redistribute them onto the energy spectrum


DPP-TF vs Analog Chain set-ups

N1470

High

Voltage

N968 Shaping

Amplifier

N957 Peak

Sensing ADC

DT5724 14bit @ 100MSps

Digitizer + DPP-TF

Energy

Energy

Time

Ge / Si C.S.

PRE


Test Results with HPGe detectors

• Preliminary tests performed at LNL (Legnaro - Italy) on Nov-2008 and Feb-2009

• Duke University on Jul-2010

• University of Palermo (Dep. Of Phisycs) on Jan 2011. Detector: Ortec HP-Ge mod. GEM40P4 cooled with an X-cooler (Peltier). Preamp: A257P (time constant = 100s).

• Saclay (France), lab of radiochemistry on March 2011. Different types of detectors and sources.

FWHM @ 1.33 MeV:

1.98 KeV


Test Results with HPGe (I)


Test Results with HPGe (II)


Test Results with HPGe (III)


Test Results with HPGe (IV)

SUM PEAK

Cs137 @ 110 Kcps

RTD enabled RTD disabled

1

1 0

1 0 0

1 0 0 0

1 0 0 0 0

1 0 0 0 0 0

1 e + 0 0 6

0 1 0 0 0 2 0 0 0 3 0 0 0 4 0 0 0 5 0 0 0 6 0 0 0 7 0 0 0

' H i s t o 1 9 _ R T D . t x t '

' H i s t o 1 7 _ 1 1 0 K H z . t x t '


Test Results with CdTe at high rate (I)

• Tests executed at University of Palermo on February 2011

• Detector: CdTe from Amptek with embedded FET integrator

• Rise Time = 140 ns, Decay Time = 100 s

• Source = 109Cd, X-ray peaks at 22 and 25 KeV

• Tested at 70, 200 and 800 KHz with different DPP parameters

70 KHz


Test Results with CdTe at high rate (II)

200 KHz

200 KHz

with Rise Time Discriminator

SUM PEAKS

NO SUM PEAKS

800 KHz

800 KHz

with Baseline Hold-off


Coming soon…

• CAEN is designing a full featured 2 channel, 16K Digital Pulse Height Analyzer (DPHA) in the form factor of the Desktop Digitizers

• Two BNC inputs with four SW selectable dynamic ranges

• Two SHV high voltage supplies for the detector bias (± 6kV, 1mA)

• Two DB9 with low voltage supplies for the pre-amplifiers (±12V, ±24V), temp. sensor and HV inhibit; the latter also on BNC (back panel)

• Readout from USB (30MB/s) and Optical Link (80MB/s)

• Drivers, Libraries and Readout Software for Windows, Linux and LabView


DPP-CI


DPP-CI topics

• Digital implementation of the QDC + discriminator and gate generator

• Implemented in the Mod. x720 - 12 bit, 250MS/s

• Self-gating integration; no delay line to fit the pulse within the gate

• Baseline restoration (pedestal cancellation)

• Extremely high dynamic range

• Dead-timeless acquisition (no conversion time)

• Energy and timing information can be combined

• Typically used for PMT or SiPM/MPPC readout


DPP-CI Block Diagram

INPUT

a = Low Pass mean

b = RiseTimeThr = TRG Threshold

W = Gate width

Nsbl = Baseline mean

TIMING

FILTER

GATE

DELAYED

INPUT

D = Delay (Pre-Gate) COMP

DELAY

TRG & TIMING

FILTER

TRIGGER

BASELINE

MEAN

a b

Nsbl

Thr

SUB

INPUT

TIME STAMP

CHARGE

W

CLK COUNTER

ACCUMULATOR

(INTEGRATOR)

D

MONOSTABLEGATE

QLSB = TS * VLSB / 50

= 40 fC (Mod 720)


DPP-CI vs Analog Chain set-up

N1470

High

Voltage

DT5720 12bit @ 250MSps

Digitizer + DPP-CI

Charge

Charge

Time

NaI(Tl)

PMT

Dual Timer

N93B

Delay

N108A

QDC

V792N

CFD

N842

TDC

V1190 Time

Splitter

A315


DPP-CI: Test Results with NaI+PMT

DPP-CI Analog QDC

Energy (MeV) Res (%) Res (%)

0.481 (137Cs Compton edge) 9.41 1.18 12.80 0.70

0.662 (137Cs Photopeak) 7.01 0.04 8.17 0.04

1.33 (60Co Photopeak) 5.67 0.03 6.66 0.18

1.17 (60Co Photopeak) 5.46 0.02 5.89 0.13

2.51 (60Co Sum peak) 3.82 0.11 4.10 0.24 Resolution = FWHM * 100 / Mean

NaI detector and PMT directly connected to the QDC or digitizer


DPP-CI: Test Results with SiPM kit SP5600

•0.5 ph

•1.5 ph

•2.5 ph

•Th

resh

old

scan


DPP-CI: Test Results with LaBr

• Project: SLIM.CHECK (detection of illicit radioactive material)

• Test performed at JRC Ispra by INFN PD (acknowledges: G. Visti)

• 4 detectors: LaBr, NaI(Tl), NE213, 3He, all read by a V1720 with DPP-CI

• Source 238U (348 Kg)

LaBr

NaI


DPP-PSD


DPP-PSD topics

• Digital implementation of the E/E analysis (double gate charge integration)

• Implemented in the Mod. x720 - 12 bit, 250MS/s and Mod x751 - 10 bit, 1GS/s or 2GS/s

• PSD = (QLONG - QSHORT)/ QLONG

• Typically used with organic liquid scintillators (e.g. BC501)

• Dead-timeless acquisition (no conversion time)

• Alternative analysis (not implemented yet) based on the Rise Time Discrimination technique: T in the Zero Crossing of two CFDs at 25% and 75%; applied to integrated output (either from C.S. preamp or digital integrator)


DPP_PSD Block Diagram (I)

SHORT GATE

LONG GATE

DELAY

BASELINE

BLns

TRGthr

SUBINPUT

TIME STAMP

Q-FAST

CLKTIME

COUNTER

GATE1

ACCUMULATOR

(INTEGRATOR)

COMPTRIGGER

BLthr GateWidth1

WAVEFORM

PULSE SHAPE

DISCRIMINATORGATE2

EV

EN

T B

UIL

DE

R

PSDthr

Q-SLOW

PreTrigger

GateWidth2

OUT

DATA


DPP_PSD Block Diagram (II)

T

Algorithms tested off-line

Not yet implemented in FW

DELAY

BASELINE

BLns

TRGthr

SUBINPUT

TIME STAMPCLK

TIME

COUNTERCOMP

T1

BLthr

WAVEFORM

PULSE SHAPE

DISCRIMINATOR

PreTrigger

CFD

DELAY

25% ATTEN

75% ATTEN

SUB

SUB

ZC

ZC

EV

EN

T B

UIL

DE

R

T2

OUT

DATA

PSDthr


-n Discrimination: test results (I) Detector: BC501A 5x2 inches,

PMT: Hamamatsu R1250


-n Discrimination: test results (II)


-n Discrimination: test results (III)


-n Discrimination: test results (IV)


-n Discrimination: test results (V)

- 5 0

0

5 0

1 0 0

1 5 0

2 0 0

2 5 0

3 0 0

3 5 0

4 0 0

4 5 0

5 0 0

- 5 0 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0

' h i s t o g r a m 2 d . t x t '

- 5 0

0

5 0

1 0 0

1 5 0

2 0 0

2 5 0

3 0 0

3 5 0

4 0 0

4 5 0

5 0 0

- 5 0 0 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0

' h i s t o g r a m 2 d . t x t '

12bit 250MS/s

10bit 1GS/s (off-line)


-n Discrimination: test results (VI)

E/E (dual gate)

t CFD (25%, 75%)

(off-line)


Practical example of off-line coincidence

0

5000

10000

15000

20000

25000

0 50 100 150 200 250 300 350 400

ALL

0

500

1000

1500

2000

0 50 100 150 200 250 300 350 400

COINC

• Detectors: 2 BC501A

• Source: Na22

• 740.000 events acquired in list mode (energy+time stamp) from both detectors

• Off-line analysis: search for time-stamp coincidence within 50 ns

• Energy spectrum of all events (up) and after coincidence (down)

• Energy vs Time of Flight 2-D plot (below)


TIMING


Conventional TDCs vs Digitizers

• Conventional TDC boards:

V1190: 128 channel, 100 ps Multi-Hit TDC

V1290: 32 channel, 25 ps Multi-Hit TDC

V775: 32 channel, 35 ps Start-Stop TDC

• TDC in a digitizer can't compete in terms of density and cost, but…

• There are cases where the implementation of a TDC in a digitizer is profitable:

Time measurement (at medium-low resolution) combined with energy or other parameters

Extremely high timing resolution (better than 10 ps) in the whole chain

Bursts of very close pulses (e.g. Free Electron Lasers)

Avoid the use of Constant Fraction Discriminators


Algorithms for the Time Measurements

• DPP time stamp LSB equals the sampling period (Resolution = Ts/12);

• Interpolation between samples improves timing resolution

• It is not worth doing on-line interpolation (floating point consumes FPGA resources and has no significant data size reduction)

• DPP can make on-line digital CFD or LED and save just 2 (or more) points into the readout data; interpolation is then calculated off-line

• The resolution is greatly depending of the rise-time and amplitude of the pulses (V/ T)

S1

S2

S3

S4S4 = ZC time stamp

Resolution = Ts / 12

High Resolution ZC after

math. Interpolation

Time

INPUT

Timing

Filter


ZC timing errors Timing resolution affected by three types of noise:

– Electronic noise in the analog signal (here ignored)

– Quantization error Eq

– Interpolation error Ei

There are 2 different cases:

Rise Time > 5*Ts linear interpolation is good: Ei << Eq The resolution is proportional to V/T and to the number of bits of the ADC.

Rise Time < 5*Ts approximation to a straight line is too rough: Ei is the dominant error (Eq is negligible). Such a geometric error varies with the position of the signal respect to the sampling clock giving non gaussian spectra and other non-physical effects. The resolution becomes inversely proportional to the rise time.

Optimum Rise Time = 5*Ts

for any type of digitizer! SN-1

SN

TSAMPL

LSBADC

zero

Eq

Ei

ANALOG

SIGNAL

LINEAR

INTERPOLATION

TRUE TIME

MEASURED TIME

TIME STAMP


Sampling Clock phase effect (RT<5Ts) (I)

ERRA

CHA CHB

ERRB

DELAYA-B = N*TS

CHA CHB

ERRA ERRB

DELAYA-B = (N+0.5)*TS

DELAYAB = N * Ts:

same clock phase for A and B

same interpolation error

ERRA ERRB

Error cancellation in calculating TIMEAB

TIMEAB = (ZCA + ERRA) – (ZCB + ERRB) = ZCA– ZCB + (ERRA - ERRB )

DELAYAB = (N+0.5) * Ts:

rotated clock phase for A and B

different interpolation error

ERRA ERRB

No error cancellation. ERRA and ERRB

are symmetric: twin peak distribution

When rise time < 5*Ts, the interpolation error has a big variation with the phase between the rising edge and the sampling clock.


Sampling Clock phase effect (RT=0) (II)

SCLK

CH-A

DATA-AS1 S2

S3 S4 S5

TA

S1 S2 S3

S4 S5

TB

CH-B

DATA-B

TAB

TS TX

SCLK

CH-A

DATA-AS1 S2

S3 S4 S5

TA

S1 S2 S3

S4’ S5

TB’

CH-B

DATA-B

TAB’

TS TX

S4’’

TB’’

TAB’’

TAB

counts

TAB

counts

TX = n * Ts

n

TX = (n+0.5) * Ts

n n+1

Sigma = 0

Sigma = 0.5


Sampling Clock phase effect (RT<5Ts) (III)

0

1 0 0

2 0 0

3 0 0

4 0 0

5 0 0

6 0 0

7 0 0

8 0 0

9 0 0

0 2 0 0 4 0 0 6 0 0 8 0 0 1 0 0 0 1 2 0 0 1 4 0 0 1 6 0 0

' h i s t o _ M o d 7 2 4 _ d t 1 0 n . t x t '

' h i s t o _ M o d 7 2 4 _ d t 1 5 n . t x t '

DELAY = N * Ts

DELAY = (N + 0.5) * Ts


Sampling Clock phase effect (RT<5Ts) (IV)

Vpp = 100mV

Mod720: 12bit 250MSps

Emulation

0.01

0.1

1

10

3 4 5 6 7 8 9

Std

_D

ev[n

s]

Delay[ns]

RiseTime 5ns

RiseTime 10ns

RiseTime 15ns

RiseTime 20ns

RiseTime 30ns

5 ns 10 ns 15 ns 20 ns 30 ns

Rise Time


Preliminary results: Mod724 (14 bit, 100 MS/s)

RiseTime (ns)

Std

De

v (

ns)

5*T

DELAY = (N + 0.5) * Ts

DELAY = N * Ts


Preliminary results: Mod720 (12 bit, 250 MS/s)

RiseTime (ns)

Std

De

v (

ns)

5*T


Preliminary results: Mod751 (10 bit, 1 GS/s)

NOTE: the region with Rise Time < 5*Ts (5 ns) is missing in this plot

RiseTime (ns)

Std

De

v (

ns)

5*T


Mod724 vs Mod720 vs Mod751

RiseTime (ns)

Std

De

v (

ns)

Amplitude = 100 mV


Mod751 @ 2 GS/s S

tdD

ev (

ns)

Amplitude (mV)

5 ps !

The cubic interpolation can reduce the gap between best and

worst case as well as increase the resolution for small signals!

DIGITAL SIGNAL (NIM or ECL)


Software for Digitizers

WaveDump

VME

Digitizers

VM

E

CONET2 (Optical Link)

Desktop

Digitizers

A2818 A3818

V2718

V1718

NIM

Digitizers

PCIe

Digitizers

DPPRunner Other Application

CAENDigitizer Library

CAENComm Library

A2818 driver A3818 driver V1718 driver USB driver P72XX driver

PC

I

PC

Ie

PC

Ie

USB 2.0 USB 2.0 USB 2.0

SBC

3rd part

driver


Applications

Acquisition

Engine

Control

PanelPlotter

OTHER CONFIG FILES

PLOT DATA

FILES

PLOTTER

CONFIG FILE

OUTPUT FILES

CAENDigitizer Lib

PIPESOCKET

SOFTWARE

HARDWARE

DPPconfig.dpp

CAENComm Lib

Drivers

Digitizer

Spectroscopy

Analysis

digital pulse processing for physics applications

Documents