DISEÑO LÓGICO (DLO)

Ejemplos de VHDL

2

Biestable D - latchlibrary IEEE;use IEEE.std_logic_1164.all;

entity DLatch is port (

GATE: in STD_LOGIC; DIN: in STD_LOGIC; DOUT: out STD_LOGIC );

end DLatch;

architecture DLatch_arch of DLatch isbeginprocess (GATE, DIN)begin if GATE='1' then -- habilitación del biestable activa a nivel alto DOUT <= DIN; end if;end process;end DLatch_arch;

3

Biestable D-latch con resetlibrary IEEE;use IEEE.std_logic_1164.all;entity DLatchR is port (

GATE: in STD_LOGIC; RESET: in STD_LOGIC; DIN: in STD_LOGIC; DOUT: out STD_LOGIC );

end DLatchR;architecture DLatchR_arch of DLatchR isbeginprocess (GATE, DIN, RESET)begin if RESET='1' then -- RESET activo a nivel alto DOUT <= '0'; elsif GATE='1' then -- habilitación del biestable activa a nivel alto DOUT <= DIN; end if;end process;end DLatchR_arch;

4

Biestable D- flip-flop, (sin y con reset)

library IEEE;use IEEE.std_logic_1164.all;

entity DFlipFlop is port ( CLK: in STD_LOGIC;

DIN: in STD_LOGIC; DOUT: out STD_LOGIC );

end DFlipFlop;

architecture DFlipFlop_arch of DFlipFlop isbeginprocess (CLK)begin if CLK'event and CLK='1' then -- CLK rising

edge DOUT <= DIN; end if;end process;end DFlipFlop_arch;

library IEEE;

use IEEE.std_logic_1164.all;

entity DFlipFlopR is

port (

CLK: in STD_LOGIC;

RESET: in STD_LOGIC;

DIN: in STD_LOGIC;

DOUT: out STD_LOGIC

);

end DFlipFlopR;

architecture DFlipFlopR_arch of DFlipFlopR is

begin

process (CLK, RESET)

begin

if RESET='1' then -– RESET asíncrono activo alto

DOUT <= '0';

elsif (CLK'event and CLK='1') then -- CLK rising edge

DOUT <= DIN;

end if;

end process;

end DFlipFlopR_arch;

D con reset

5

Biestable D- flip-flop (Con CE, y reset síncronos

library IEEE;use IEEE.std_logic_1164.all;entity DFlipFlopCE is port ( CLK: in STD_LOGIC;

ENABLE: in STD_LOGIC; DIN: in STD_LOGIC; DOUT: out STD_LOGIC );

end DFlipFlopCE;architecture DFlipFlopCE_arch of

DFlipFlopCE isbeginprocess (CLK) begin if (CLK'event and CLK='1') then

if (ENABLE='1') then DOUT <= DIN;

end if; end if; end process;end DFlipFlopCE_arch;

library IEEE;

use IEEE.std_logic_1164.all;

entity DFlipFlopSR is

port (

CLK: in STD_LOGIC; RESET: in STD_LOGIC;

DIN: in STD_LOGIC; DOUT: out STD_LOGIC

);

end DFlipFlopSR;

architecture DFlipFlopSR_arch of DFlipFlopSR is

begin

process (CLK)

begin

if CLK'event and CLK='1' then --CLK rising edge

if RESET='1' then --synchronous RESET active High

DOUT <= '0';

else

DOUT <= DIN;

end if;

end if;

end process;

end DFlipFlopSR_arch;

D c

on

CE

D c

on

res

et

sín

cro

no

6

Decodificador 3 a 8library IEEE;use IEEE.std_logic_1164.all;

entity deco3a8 is port ( RESET: in STD_LOGIC; CLK: in STD_LOGIC;

D_IN: in STD_LOGIC_VECTOR(2 downto 0); D_OUT: out STD_LOGIC_VECTOR(7 downto 0) );

end deco3a8 ;

architecture deco3a8_arch of deco3a8 isbeginprocess(CLK, RESET, D_IN)beginif ( RESET = '1') then

D_OUT <= "00000000";elsif ( CLK'event and CLK ='1') then

case D_IN iswhen "000" => D_OUT <= "00000001";when "001" => D_OUT <= "00000010";when "010" => D_OUT <= "00000100";when "011" => D_OUT <= "00001000";when "100" => D_OUT <= "00010000";when "101" => D_OUT <= "00100000";when "110" => D_OUT <= "01000000";when "111" => D_OUT <= "10000000";when others => NULL;

end case;end if;end process;end deco3a8_arch;

7

Codificador 8 a 3library IEEE;use IEEE.std_logic_1164.all;

entity enco8a3 is port ( RESET: in STD_LOGIC; CLK: in STD_LOGIC; D_IN: in STD_LOGIC_VECTOR(7 downto 0);

D_OUT: out STD_LOGIC_VECTOR(2 downto 0) );

end enco8a3 ;

architecture enco8a3_arch of enco8a3 isbeginprocess(CLK,RESET,D_IN)beginif ( RESET = '1') then

D_OUT <= "000";elsif ( CLK'event and CLK ='1') then

case D_IN iswhen "00000001" => D_OUT <= "000";when "00000010" => D_OUT <= "001";when "00000100" => D_OUT <= "010";when "00001000" => D_OUT <= "011";when "00010000" => D_OUT <= "100";when "00100000" => D_OUT <= "101";when "01000000" => D_OUT <= "110";when "10000000" => D_OUT <= "111";when others => NULL;

end case;end if;end process;end enco8a3_arch;

8

Multiplexor 4 a 1library IEEE;use IEEE.std_logic_1164.all;

entity Mux4a1 is port (

SEL: in STD_LOGIC_VECTOR(1 downto 0); A, B, C, D:in STD_LOGIC; MUX_OUT: out STD_LOGIC );

end Mux4a1;

architecture Mux4a1_arch of Mux4a1 isbeginprocess (SEL, A, B, C, D)begin case SEL is when "00" => MUX_OUT <= A; when "01" => MUX_OUT <= B; when "10" => MUX_OUT <= C; when "11" => MUX_OUT <= D; when others => MUX_OUT <= 'X'; end case;end process;end Mux4a1_arch;

9

Contador de 4 bitslibrary IEEE;use IEEE.std_logic_1164.all;

entity Contador is port (

CLK: in STD_LOGIC; RESET: in STD_LOGIC; CE, LOAD, DIR: in STD_LOGIC; DIN: in INTEGER range 0 to 15; COUNT: inout INTEGER range 0 to 15 );

end Contador;

architecture Contador_arch of Contador isbeginprocess (CLK, RESET)begin if RESET='1' then COUNT <= 0; elsif CLK='1' and CLK'event then if LOAD='1' then COUNT <= DIN; else if CE='1' then if DIR='1' then COUNT <= COUNT + 1; else COUNT <= COUNT - 1; end if; end if; end if; end if;end process;end Contador_arch;