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Introduction to VHDL Modules #6 and #7 Digilent Inc. Course

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Page 1: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Introduction to VHDL

Modules #6 and #7

Digilent Inc. Course

Page 2: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Data Selectors / Multiplexers

Page 3: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Bus Multiplexer

Page 4: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

MUX VHDL Example:

Selected Signal Assignment

Page 5: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Bus MUX VHDL Example:

Selected Signal Assignment

Page 6: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

More Complex MUX VHDL:

Conditional Assignment

Page 7: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Decoder

Page 8: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Decoder VHDL Example:

Selected Signal Assignment

Page 9: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

DeMultiplexer (DeMUX)

Page 10: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

DeMUX VHDL Code

� Assignment: modify the code of a MUX to implement a DeMUX

Page 11: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

7-Segment Decoder

Page 12: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

7-Segment Decoder VHDL Code

Page 13: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Priority Encoder

Page 14: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Shifters

Page 15: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Shifters

Page 16: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Shifters VHDL Example

Page 17: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Bit-Slice Design Method

� Consider a circuit that works on a pair of bits

� Goal is to create a circuit that can simply be replicated N times

� once for each bit

� Some circuits defy this approach

� Information passing between adjacent bits

Page 18: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Comparators

Page 19: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Comparator Bit-Slice Design

Page 20: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Comparator Bit-Slice Design

Page 21: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Adders

Page 22: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Arithmetic and Logic Unit (ALU)

Page 23: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

8-Bit, 4-Function ALU VHDL

Page 24: Introduction to VHDL - ymk.k-space.orgymk.k-space.org/ME_VHDL2.pdf · entity mux select is port (13, 12, Il, 10: in std_logic sel in std_logic vector (1 downto 0); Y . out std_logic

Assignment

� Lab Project P6

� Do only on Xilinx Webpack

� Simulate to show results

� No Digilent board demo is necessary

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