ece u530 digital hardware...

ECEU530

ECE U530Digital Hardware Synthesis

• Lecture 4:• Std_logic and resolved types• Delta Delays • Example: 2-to-1 mux

–many different architectures• Signal Assignments:

–simple, conditional, selected

ECE U530 F06lect04.ppt

Prof. Miriam [email protected]

Sept 18, 2006

ECE U530 F’062lect04.ppt

Class Schedule• Quiz in class on September 25

• Based on Tutorial, and Book Chapter 1• Open book and notes

• Hommework 1 due September 27• No class on Monday, October 2

• Make an appointment to see me October 3 through 6 to discuss your class project

ECEU530


Course Accounts• You must have a COE account for this course

• Programming assignments will be done on WinCOE sytems• Tools: Xilinx ISE version 6.2i, Modelsim 5.7e

• If you are registered for this class,A sub-directory called Courses/ECEU530 will automatically appear in your home directory

• IMPORTANT: Do NOT create this directory !• Do not use this as your active working directory !

–only files submitted for homework should be in this directory• use your home directory for all design work !• tutorial should be done in your home directory


Homework 1 due September 27• Describe a 4 way AND-OR-INVERT gate:

• Behaviorally• Structurally

• Submit your VHDL files only in your courses directory• To see your courses directory,

• click on the "My Computer" icon then double click on the mapped drive (a drive with a pipe on the bottom) similar to the Z: drive.

• Do not be try to open the "Courses" directory inside the Z: drive. This will not work.

• You should be using the L: drive which is labeled ECEU530-01.

ECEU530


And-Or-Invert Logic


STD_LOGIC_1164 - Logic Values

IEEE Standard

type STD_ULOGIC is ( ‘U’,-- Uninitialized

‘X’,-- Forcing Unknown

‘0’,-- Forcing 0

‘1’, -- Forcing 1

‘Z’,-- High Impedance

‘W’,-- Weak Unknown

‘L’,-- Weak 0

‘H’,-- Weak 1

‘-’,-- Don’t care

);

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Resolution

CONSTANT resolution_table : stdlogic_table := (-- ----------------------------------------------------------- | U X 0 1 Z W L H - | | -- ---------------------------------------------------------

( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |( 'U', 'X', '0', '1', 'W', 'W', 'W','W', 'X' ), -- | W |( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |( 'U', 'X', 'X', 'X', 'X', 'X', 'X', ’ X', 'X' ) -- | - |

);


STD_LOGIC Definition---------------------------------------------------- *** industry standard logic type ***--------------------------------------------------

SUBTYPE std_logic IS resolved std_ulogic;

-------------------------------------------------- unconstrained array of std_logic for use -- in declaring signal arrays------------------------------------------------TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;

ECEU530


Signal Assignment Statements• A signal assignment is a concurrent statement:

Y <= ((not sel) and A) or (sel and B));

• statement is evaluated whenever sel, A, or B change

• A process statement is a concurrent statement

process( A, B, sel) is

begin

Y <= ((not sel) and A) or (sel and B));end process;


Delta Delay• If no future time is specified, VHDL automatically

assumes a small time delay.• The delay is called delta delay: δδδδ

• The smallest unit of time

• Causes changes to occur only in the future• Consistent with the definition of signals

• Mechanism• Assignment schedules a transaction• The transaction is applied after the process suspends• Process does not see the effect until it resumes next time

• REMEMBER: A signal assignment statement is a process

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Why Delta Delay?• Remember simulator behavior• Twp phases :

• Signal update phase• Process execution phase

• Signal update phase updates the values of the signals at the current simulation time

• Process execution phase evaluates the results of those signals being applied

• Process update phase causes (new) signals to change• This is called triggering events

• Signals are changed at the NEXT time simulator runs• May be one delta later


Why Delta Delay?• Assignments are done in the process execution

phase. Eg. X <= 10;• Transaction is not applied immediately

• It can be done only in the signal update phase

• When all processes are suspended, simulation time is updated

• Only then is the transaction applied• Simulation time may be t + δδδδ, t + 2 δδδδ ...

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Be careful• Delta delay makes programming different• Always remember : “Signals can be updated only in

future time”.• If you think sequential code means sequential

execution, you are wrong• A common pitfall :

s <= ‘1’;……if (s = ‘1’) then signal is not updated yet


1

IN: 1 →→→→ 0 A

B

C

Time Delta Event0 ns 0 IN: 1 →→→→ 0

eval INVERTER1 A: 0 →→→→ 1

eval NAND, AND2 B: 1 →→→→ 0

C: 0 →→→→ 1eval AND

3 C: 1 →→→→ 01 ns

Delta Delay•

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Modeling Hardware with VHDL


ECEU530

Libraries and Packages• A library is a place where the VHDL compiler stores

information about a particular design project• For any design, the compiler creates and uses the

work library• A design may have multiple files, each containing different

units• When a file is compiled, the results are placed in the work

library.

• Not all information needed in a design must be in the work library. A designer may rely on common definitions or functions across a family of different projects

• A project can refer to libraries containing shared definitions:library ieee;

Using packages• Specifying a library gives access to any previously

analyzed entities and architectures, but does not give access to types and the like

• A package is a file with definitions of objects (signals, types, constants, functions, procedures, component declarations) to be used by other programs

• A design can use a package:use ieee.std_logic_1164.all;

• Within the ieee library, the signal definitions are in:std_logic_1164

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ECEU530


Example: 2-to-1 Multiplexer• Many different ways to describe

• data flow–boolean logic

• structural• behavioral

• Point is to show you different VHDL styles


Example 2-to-1 Multiplexer

2 x 1 MUX

A

BY

sel

sel Y0 A1 B

ECEU530


2-to-1 Multiplexer Behavior

when sel = 0 choose A to send to output Y sel =1 choose B

Y <= Sel •••• A + Sel •••• B

sel Y0 A1 B

I can describe 2-to-1 multiplexer:with logic gateswith a Boolean equationwith if -- then -- else statement


library IEEE;use IEEE.std_logic_1164.all;

entity mux21 isport (

A: in STD_LOGIC;B: in STD_LOGIC;sel: in STD_LOGIC;Y: out STD_LOGIC

);end mux21;

2-to-1 MUX Entity

A

B

Y

sel

2 x 1MUX

ECEU530


architecture blogic1 of mux21 isbegin

y <= ((not sel) and A) or (sel and B));end architecture blogic1;

•Precedence is from left to right:•use parentheses for precedence!

•Boolean logic operators: not and or nand nor xor xnor•defined for type std_logic

•Note: Boolean logic operators are NOT logic gates.•This is NOT a structural description

Architecture: Boolean Logic


architecture blogic2 of mux21 issignal c, d: std_logic;beginc <= (A and (not sel));d <= (B and sel);Y <= c or d;

end architecture blogic2;

•This is still a Boolean logic description •This is NOT a structural description

•This has different timing behavior from blogic1•Why ?


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architecture blogic3 of mux21 isvariable c, d: std_logic;beginprocess(A,B,sel)

beginc := (A and (not sel));d := (B and sel);Y <= c or d;

end process;end architecture blogic3;

•This is still a Boolean logic description

•Does this have the same timing as architecture blogic1 ?•architecture blogic 2?•Why?



Structural Components• To use components in the Xilinx tools, uncomment

these lines in your VHDL file:library UNISIM;

use UNISIM.VComponents.all;

• Structural Components are found in the UNISIM library. • Look under libraries in Modelsim

• To use a component from a component library:• component names must match exactly• port names must match exactly

• In the unisim library:• Output port is called O and is listed first• Input ports are called I0, I1, ...

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• Note: This is a VHDL-87 style description!

architecture structural of mux21 iscomponent INV port(O: out std_logic;

I: in std_logic );end component;component AND2 port(O:out std_logic;

I0,I1:in std_logic); end component;component OR2 port(O:out std_logic;

I0,I1:in std_logic);end component;signal sel_n, c, d: std_logic;begin

...

Architecture: Structural


architecture structural of mux21 is...beging0: INV port map(I => sel, O => sel_n);g1: AND2 port map(I0=>sel_n, I1 => A,

O => c); g2: AND2 port map(d, sel, B);g3: OR2 port map(I0 =>c, I1 => d,

O => Y);end architecture structural;

•Structural descriptions wire together components•Components are found in design library unisims•Wires are associated with ports : port map• Association may be positional

or explicit: i1 => sel

Architecture: Structural (2)

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architecture behavioral of mux21 isbegin

mux2_1: process(a, b, sel)begin

if sel = '0' theny <= a;

elsey <= b;

end if;end process mux2_1;

end architecture behavioral;

Architecture: If-then-else


architecture csa of mux21 isbegin

y <= A WHEN sel = '0' ELSE B;end architecture csa;

Architecture: Conditional Signal Assignment (CSA)

ECEU530


Configurations• A configuration is a specification of the mapping

between an architecture and a particular instance of an entity

• A configuration exists for each entity• The default configuration maps the most recently

compiled architecture to the entity• Configurations are often used to specify alternative

simulation models for hardware designs


An n-bit 2-to-1 Multiplexer

n-bit2 x 1 MUX

a(n-1:0)

b(n-1:0)y(n-1:0)

sel

sel y0 a1 b

ECEU530



entity muxnbit21 isgeneric (width:positive);port (

a: in STD_LOGIC_VECTOR(width-1 downto 0);b: in STD_LOGIC_VECTOR(width-1 downto 0);sel: in STD_LOGIC;y: out STD_LOGIC_VECTOR(width-1 downto 0)

);end muxnbit21;

n-bit 2 x 1 MUX: entity

a(n-1:0)

b(n-1:0)

y(n-1:0)

sel

n-line2 x 1MUX


entity muxnbit21 isgeneric (width:positive);port (


);end muxnbit21;architecture blogic1 of muxnbit21 isbegin

y <= ((not sel) and A) or (sel and B));end architecture blogic1;

•This will not work! Why not?

Architecture for n-bit 2-to-1 mux?

ECEU530


Constants, Variables, Signals• constants have type and value

• the value never changes

• variables have type, initial value (optional)• updated without delay

• signals have type• always delay before updating

• variable assignment: sequential statement• evaluates when you come across it in the code

• signal assignment: concurrent statement• evaluates when signal on RHS changes

• I can mix variables and signals• I cannot mix types !


Concurrent vs. Sequential• Concurrent VHDL statements are active all the time

• whenever inputs change, outputs can be scheduled to change

• Sequential VHDL statements are evaluated when they are reached in the program

• Concurrent and sequential statements can be used to describe combinational hardware

• Concurrent and sequential statements can be used to describe sequential hardware

• Type of VHDL statement is about the code, not the circuit !

ECEU530


VHDL concurrent statements• A signal assignment is a concurrent statement:

Y <= ((not sel) and A) or (sel and B));

• statement is evaluated whenever sel, A, or B change

• A process statement is a concurrent statement

process( A, B, sel) is

begin

w := (A and (not sel));

x := (B and sel);

end process;


Process statementprocess ( )

<declarations> sensitivitybegin list

<sequential statements>

end process;

• If signal on sensitivity list changes, evaluate process

• A signal assignment statement is a one-line process • all signals on the RHS of the signal assignment statement

are automatically in the sensitivity list

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Sequential Statements• Must be inside a process• Why?

• so simulator knows when to evaluate them

• Sequential statements:• variable assignment• if ... then ... else


architecture behavioral of mux21 isbegin

mux2_1: process(a, b, sel)begin

if sel = '0' theny <= a;

elsey <= b;

end if;end process mux2_1;

end architecture behavioral;

•All signals on RHS of if ... then .. else should be in process sensitivity list

If-then-else must be in a process

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Vectors in VHDL• std_logic_vector(7 downto 0);• std_logic_vector(0 to 7);

• y <= “11110000”;

• signal y std_logic_vector(7 downto 0);• descending range• y(7) = ?• y(0) = ?

• signal y std_logic_vector(0 to 7);• ascending range• y(7) = ?• y(0) = ?


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VHDL Types

ECEU530


VHDL Data Types• data objects: signal, variable, constant

• all objects have types

• types are defined in the VHDL library STANDARD• STANDARD is automatically loaded in most CAD packages• bit, bit_vector are part of library STANDARD

• VHDL types are defined in VHDLtype integer is range ________________

-- range is implementation dependent

-- -2147483647 to 2147483647 is 32 bit integers

type real is range _________________-- range is implementation dependent

-- reals not supported in Xilinx tools


Integer subtypes• User can define types based on integer ranges:

type counter is range 0 to 100;

type register is range 0 to 100;

signal A: counter;

signal B: register;

A <= A + B; -- this will create an error

-- Why ?

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Bits and Booleans• The type boolean has two elements: true, false

• defined as an ennumerated type:type boolean is (true, false);

type color is (red, green, blue);

-- another ennumerated type

• The type bit has two elements: ‘0’, ‘1’• type bit is (‘0’,’1’);

• What type is the statement:(sel = ‘0’)

• This code will create an error -- why ?y, sel : bit;

y <= ( sel = ‘0’);


Characters• A character literal is a character in single quotes:• ‘0’, ‘1’

Type four_values is (‘0’, ‘1’,’U’,’X’);

signal SIG: four_values;

Sig <= ‘X’;

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Array types• Array: group of elements all having the same type

type byte is array (7 downto 0) of std_logic;

type word is array(31 downto 0) of std_logic;

type memory is array(0 to 4095) of word;

• std_logic_vector is array of std_logic elements:TYPE std_logic_vector IS

ARRAY ( NATURAL RANGE <>) OF std_logic;

• This is how you declare an “unconstrained” range


Strings• A string is an array of characters

• characters are in single quotes• strings are in double quotes;

variable name: string(1 to 10) := “model name”;

• Note:“true” is NOT the same as true

‘1’ is not the same as 1

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Std_logic_vector• std_logic_vector is array of std_logic elements:TYPE std_logic_vector IS

ARRAY ( NATURAL RANGE <>) OF std_logic;

signal counter_16: std_logic_vector (15 downto 0);

counter_16 <= B”1011_0010_1011_0101”;

• Bit string literals:B”1011” -- binaryO”7345” -- octalX”ECE530” -- hexadecimal

counter_16 <= X”B2B5”;


8 input 2-1 muxlibrary IEEE;

use IEEE.std_logic_1164.all;

entity mux8bit21 is

port (

a: in STD_LOGIC_VECTOR(7 downto 0);

b: in STD_LOGIC_VECTOR(7 downto 0);

sel: in STD_LOGIC;

y: out STD_LOGIC_VECTOR(7 downto 0) );

end mux8bit21;

architecture behav1 of mux8bit21 is

begin

y <= a when sel = ‘0’ else b;

end architecture behav1;

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Signal Assignment Statementstarget <= expression;

target <= expression when condition else expression;

with expression select

target <= expression when choices,

expression when choices;

architecture behav1 of mux8bit21 is

begin

y <= a when sel = ‘0’ else b;

end architecture behav1;


Selected Signal Assignmentarchitecture behav2 of mux21_8 is

begin

with sel select

y <= a when ‘0’,

b when ‘1’,

“XXXXXXXX” when others;

end behav2;

• Why is others clause needed?

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Signal Assignmentarchitecture new_behav of mux21_8 is

signal temp: std_logic_vector (7 downto 0);

begin

temp <= (sel,sel,sel, others => sel);

y <= ((not temp) and a) or (temp and b);

end new_behav;

• Every bit of temp is set equal to sel:temp <= (sel, sel, sel, sel, sel, sel, sel, sel);

temp <= (others => sel);

temp <= ( 1 => sel, 7 => sel, ...);


ECEU530



Signal Assignment Statements• Simple signal assignment:target <= expression;

• Conditional signal assignment:target <= expression when condition else expression;

• More than one expression can be true• Evaluation order matters

• Selected signal assignment:with expression select

target <= expression when choices,

expression when choices;

• Exactly one expression should be true• Evaluation order does not matter• All possible choices must be covered

ECEU530



entity muxnbit21 isgeneric (width:positive := 8);port (


);end muxnbit21;

n-bit 2 x 1 MUX: entity

a(n-1:0)

b(n-1:0)

y(n-1:0)

sel

n-line2 x 1MUX


VHDL Generics• Generics may be used for readability, maintenance

and configuration• Generic clause syntax :

generic (generic_name : type [:= default_value]);

• Generic value is assigned when component is used in a larger design

• Generic value is assigned with a generic map statement:

generic map width => 8;

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