lec13-generics - bu electronics design...

ECEU530

ECE U530Digital Hardware Synthesis

• Lecture 13:• Homework 5• Xilinx VHDL tools and XST• Generate Statements -- Ashenden, Chapter 14

• HW 4: Due now• Midterm review in class Monday, October 30• Midterm in class on Wednesday, November 1

ECE U530 F06lect13.ppt

Prof. Miriam [email protected] 25, 2006

ECE U530 F’062lect13.ppt

Schedule• Review in class on Monday, October 30

• I will hand out a sample Midterm• Midterm in class on Wednesday, November 1

• Open book and notes• Computers okay, but no running of CAD tools

• Classes on November 6 and 8 will be in 429 Dana• Homework 5 due Wednesday, November 8

• Write the Datapath for the calculator from ECEU323 in VHDL• Use the posted entity

• Project progress report due Friday, November 10:• and email to me telling me where your project stands• some working VHDL code

• Homework 6: Lab 5 due Wednesday November 15


What’s on the midterm• This material is in Handout 5: Midterm Information• The VHDL simulation model• VHDL types including bit, bit_vector, std_logic and

std_logic_vector• Modeling combinational circuits in VHDL using behavioral,

dataflow, and structural modeling• How to include a component from the Xilinx component library• Modeling sequential circuits in VHDL, including circuits with

clocks, synchronous resets, and asynchronous resets• flip-flops, registers, shift registers, counters

• Modeling Mealy and Moore Machines in VHDL• Simulatable vs. synthesizable VHDL. Constructs that are

synthesizable by the design tools used in this class• Writing a testbench in VHDL


Midterm Reading

• XST User Guide:• Chapter 2: HDL Coding Techniques

–We have not covered RAMds/ROMs and Black Boxes• Chapter 6: VHDL Language Support

• Ashenden:• Chapters 1, 2 and 3• Chapter 4 Sections 4.1, 4.2, 4.3• Chapter 5• Chapter 7 Sections 7.4 and 7.5• Chapter 8 Sections 8.1, 8.2, 8.3• Chapter 11 Sections 11.1, 11.2• Chapter 13 Section 13.1

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Datapath for the Calculator(HW 5)


HW 5 Datapath Entitylibrary ieee;

use ieee.std_logic_1164.all;

entity datapath is

port (

din : in std_logic_vector (3 downto 0);

dout : out std_logic_vector (3 downto 0); cout : out std_logic;

sm : in std_logic; -- mux selector

sa : in std_logic_vector (2 downto 0); -- alu mode selectors

ss : in std_logic_vector (1 downto 0); -- stack mode selectors

clk : in std_logic -- clock );

end datapath;


Stack for Datapathentity stack is

port(

clk, reset : in std_logic; -- clock

s : in std_logic_vector (1 downto 0); din : in std_logic_vector (3 downto 0);

tos : out std_logic_vector (3 downto 0) );

end stack;

architecture behavioral of stack is

begin

-- <<enter your statements here>>

end behavioral;


Implement the Stack:

Stack Function Stack select hold 0, 1 push 2 pop 3

• In lab, used shift registers to implement the stack• In VHDL, use behavioral code to implement the stack

• How ?• Hint: Create internal state for the “stack”

• Looks like a simple state machine• Output is simply TOS

•Note: Stack has an asynchronous reset

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StackARCHITECTURE behavioral of stack IS

SUBTYPE four_bit is std_logic_vector (3 downto 0);

TYPE four_array IS ARRAY (3 downto 0) OF four_bit;

SIGNAL stk, next_stack : four_array;

begin

-- process for updating stack state


Xilinx Design Process

�Step1: Design• Two design entry methods: HDL(Verilog or

VHDL) or schematic drawings

�Step 2: Synthesize to create Netlist• Translates V, VHD, SCH files into an industry

standard format EDIF file

�Step 3: Implement design (netlist)• Translate, Map, Place & Route

�Step 4: Configure FPGA• Download BIT file into FPGA

HDL code Schematic

Netlist

Implement

Synthesize

BIT File


XST Flow

To ImplementationTools

SynthesisReport File

SynthesisTechnology Specific Optimization

Constraints

VHDL Verilog

.LOG.NGC


Main Synthesis Steps

HDL

HDL ParsingIdentification of language syntax errors

HDL SynthesisMacro recognition, FSM extraction,

resource sharing

Low Level OptimizationMacro implementation, timing optimization,

LUT mapping, register replication

.NGC .LOG

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FSM Recognition

�XST is able to recognize state machines independent of the modeling style used• For example, you may have several processes (one, two, or three)

in your description, depending on how you describe your state machine

�Notes• XST can handle/recognize synchronous state machines• Currently, XST requires FSM with initialization signals, which can

be asynchronous or synchronous

�Optimization is based on:• State assignment • Flip-flop (FF) type selection


Messages During Synthesis

Analyzing Entity <timecore> (Architecture <Beh>).Entity <timecore> analyzed. Unit <timecore> generated.

Synthesizing Unit <timecore>.Related source file is timecore.vhd.Found 7-bit subtractor for signal <$n0010> created at line 150.Found 7-bit subtractor for signal <$n0011> created at line 152.Found 7-bit register for signal <min>.Found 4-bit register for signal <points_tmp>.Found 7-bit register for signal <sec>.Summary:

inferred 1 Finite State Machine(s).inferred 18 D-type flip-flop(s).inferred 10 Adder/Subtracter(s).

Unit <timecore> synthesized.

HDL Synthesis (Example)

In many cases, XST assigns an internal name to a macro during macro inference•Starting with version 4.2i, XST gives the line number of the HDL code so it is possible to determine where

in the HDL code this macro was inferred.Note: In some cases, XST still fails to give such information. One reason is that a macro

inference may correspond to several lines of code.


Final Statistics

Top Level Output File Name : <path>\<filename>.ngcCrit : speedUsers Target Library File Name : virtex...Macro Statistics

# Adders/Subtractors : 35-bit adder : 26-bit adder : 1

Design Statistics# IOs : 93

Cell Usage :# BELS : 121# GND : 1# LUT2 : 32# FlipFlops/Latches : 111# FDC : 111...

General Statistic Table (Example)


XST Synthesis in Project Navigator

�Module/entity selected in Sources window treated as “top”�XST-specific processes

• Synthesize– View Synthesis Report– Analyze Hierarchy– Check Syntax

�XST-specific properties• Synthesis Options• HDL Options• Xilinx Specific Options

AM2910 as top-level

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ISE GUI�Synthesis options

• Global synthesis and optimization goal and effort

�HDL options• Family-specific inference and optimization

options

�Xilinx Specific options• Specific low-level implementation and

optimization algorithms


XST - Synthesis Options

�Optimization Goal• Speed/Area

�Optimization Effort• Normal/High

�Constraints File• Any Text File

�Inference Report Detail• Normal/Low/Verbose

�Case Implementation Style • Full/Parallel/FullParallel


XST - HDL Options

�Macro Extraction Options• FSM Encoding• FSM Flip-flop Type• RAM• Mux• Decoder• Priority Encoder• Shift Register• Logical Shifter• XOR Collapsing• Resource Sharing• Complex Clock Enable• Multisource Resolution


XST - Xilinx Specific Options

�Sets specific low-level implementation and optimization algorithms

�Add I/O Buffers�Equivalent Register Removal�Maximum Fanout� Incremental Synthesis�Register Duplication/Balancing�Move First/Last Flip-Flop Stage�Slice Packing�Pack I/O Registers into IOBs

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Constraints �Writing constraints is a method of communicating

your design and performance objectives to the synthesis tools and implementation tools

�There are 3 ways to define design constraints:�Directly in the GUI for global constraints

– Easiest way to achieve required results– Most constraints are accessible here– Applies to Foundation ISE GUI or XST stand-alone GUI

�Via HDL attributes added to the HDL source code– Constraints can be applied to specific signals or instances– Best method for fine-tuning a design

�Via a separate constraint file– Allows precise tuning, but HDL source left unchanged– Uses simplified VHDL syntax, even if your design is verilog


HDL Attributes

�VHDL• The constraint type must first be defined

attribute <Name> : <Type>;Ex: attribute RLOC : string;

• The constraint may then be applied to a net, instance or entityattribute <Name> of <Object> :

<Type> is <Value>;

Ex: attribute RLOC of u123 : label is "R11C1.S0";


Constraint File Example

attribute AttributeName of ObjectName:

ObjectType is “AttributeValue”;• ObjectType can be any entity, label, or signal• AttributeValue should always be strings. They are not typed

• Each statement only applies to one object• List of object identifiers cannot be specified in the same statement• Examples:

• Attribute RLOC of u123:label is “R11C1.S0”;• Attribute bufg of my_sig:signal is {“clk”|”sr”|”oe”}


Sample FPGA Constraints/Attributes

�allclocknets�period�max_delay�mux_style�ram_style�maxfanout�register_duplication�keep_hierarchy

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Synthesis of VHDL Code

• Three things are needed• VHDL Model• Constraints on the circuit

–Area–Delay

• Library Models–What kind of components we have?–How are they characterized for area, delay etc?


Two Major Functions

• Translation – Converts the textual representation to a net-list containing target technology cells.• Also called mapping.

• Optimization – Transforms the functionality to meet requirements.

• Optimization is an iterative process• Enter constraints• Run the tools with different options• Tune the constraints

• Ideally, the synthesized circuit should simulate the same as the input VHDL code.


VHDL as a Synthesis Language

• Features of VHDL• Describe hardware at Behavioral, RTL and Gate level• Create Test Stimulus• Error checking on the model and its usage• File I/O


Subset for Synthesis

• Synthesis tools should be concerned only about the subset that enables hardware description.

NoYesFile I/O

NoYesError Checking

NoYesTest Stimulus

YesYesHardware Description

SynthesisSimulation

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VHDL as a Synthesis Language

• Vendors supply libraries to target ASICs or FPGAs• VHDL style and synthesizable subset are vendor

specific• Tools come with specific guidelines for that tool

• The documentation does not completely define the operation of tool; in contrast to the VHDL simulator where the LRM tells you exactly what to expect.

• The tool is complex. There are many options.• Use scripts to develop repeatable experiments:

• Avoid interactive input


VHDL Synthesis Flow


XST and FSMs

• XST recognizes FSMs described in VHDL with one, two or three processes

• State registers must be initialized• reset signal can be asynchronous or synchronous• XST does not support FSM without a reset signal

• The type of the state register can be: • integer, bit_vector, std_logic_vector, ...

• Recommended: • define an enumerated type containing all possible state

values and declare your state register with that type


XST and State Encoding

• XST supports the following state encoding techniques:• Auto: XST chooses the “best” encoding style for this FSM• One-Hot: This is the default• Gray Code • Compact: binary encoding. Minimize FFs• Johnson• Sequential• User Defined: Use enum_encoding attribute

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Specifying State Assignments

• In VHDL, use the attribute “enum_encoding”• This is telling the XST synthesis tool what the

encoding of the states is.

architecture behavior of example is

type statetype is (ST0, ST1, ST2, ST3);

attribute enum_encoding of statetype : type is "001 010 100 111";

signal state : statetype;

signal next_state : statetype;

begin

...


Parameterized VHDL statements

• VHDL provides facilities for writing general statements that can be used over and over again

• Packages and Libraries for storing shared declarations, functions, etc.

• Generate statements for building regular structures• Generics for leaving constants and parameters

unspecified until component or function is used• Attributes are useful for generics

• Can also have unconstrained ranges• similar to generics, used in different places


Regular VHDL Structures

• Iterative Circuits Are Composed of Many Identical Circuits: • Ripple-carry adder• RAM• Counters• Comparators

• VHDL has a “generate” statement for building iterative circuits


Generate Statement

• Automatically Generates Multiple Component Instantiations

• Two Kinds of Statements• Iteration

–FOR . . . GENERATE• Conditional

–IF . . . GENERATE

• Use Generate Statement to Reduce Coding Effort• Can Include Any Concurrent Statement Including

Another Generate Statement• Does Not Execute Directly, But Expands into Code

Which Does Execute

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Iteration

• Instantiates Identical Components• FOR Syntax

<name> : FOR <identifier> IN <range>

GENERATE

begin

concurrent-statements

END GENERATE <name> ;

• identifier cannot be changed inside the generate statement• <name> is required


Conditional

• Takes Care of Boundary Conditions• IF Syntax

• Cannot use “else” or “elsif” clauses

<name> : IF (boolean expression)

GENERATE

begin

{concurrent statements}

END GENERATE <name> ;


Binary Ripple Carry Adder• Example of a regular structure. • LSB and MSB are slightly different from the middle bits


Generate Example: R-C Adder

ENTITY RCAdder_16 IS

PORT

( A, B : IN std_logic_vector (15 downto 0);

Cin : IN std_logic ;

Sum : OUT std_logic_vector(15 downto 0);

Cout : OUT std_logic_vector ) ;

END RCAdder_16 ;

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Generate Example: R-C Adder ARCHITECTURE Generate_S OF RCAdder_16 ISCOMPONENT Full_Adder

--defined elsewhere

PORT ( A, B, Cin : IN std_logic ; S, Cout : OUT std_logic );

END COMPONENT Full_Adder ;SIGNAL Int_C : std_logic_vector (15 DOWNTO 0);

BEGIN --RC AdderAll_Bits:

FOR I IN 15 DOWNTO 0 GENERATE BEGIN



LSB : IF (I = 0) GENERATE BEGIN

S0: Full_Adder

PORT MAP ( A(I), B(I), Cin, Sum(I), Int_C(I) );

END GENERATE S0 ;

Middle_bits:

IF ( I < 15 AND I > 0 ) GENERATE

BEGIN

SI: Full_Adder

PORT MAP ( A(I), B(I), Int_C(I-1),

Sum(I), Int_C(I) );

END GENERATE SI;


Generate e.g., R-C AdderMSB:

IF ( I = 15 ) GENERATE

BEGIN

S15: Full_Adder

PORT MAP ( A(I), B(I), Int_C(I-1),

Sum(I), Cout );

END GENERATE MSB;

END GENERATE All_Bits;

END Generate_S ;


A more compact definitionARCHITECTURE regular OF RCAdder_16 IS

SIGNAL int_c: STD_LOGIC_VECTOR(16 TO 0);

BEGIN

int_c(0) <= cin;

g_main: FOR k IN 0 TO 15 GENERATE

co: Full_adder PORT MAP (a(k), b(k), cm(k), z(k), cm(k+1));

END GENERATE;

cout <= int_c(16);

END regular;

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Unconstrained Ports

• Entity declarations can have ports defined usingarrays without explicitly including the size of the array

• Leads to a general specification of an iterative circuit• Uses Predefined Array Attribute ‘LENGTH

ENTITY RCAdder_N IS

PORT ( A, B : IN std_logic_vector ;

Cin : IN std_logic ;

Sum : OUT std_logic_vector ;

Cout : OUT std_logic ) ;

END RCAdder_N ;


Array Attributes

A’left(N) left bound of index range of dimension N of A

A’right(N) right bound of index range of dimension N of A

A’low(N) lower bound of index range of dimension N of A

A’high(N) upper bound of index range of dimension N of A

A’range(N) index range of dimension N of A

A’reverse_range(N) index range of dimension N of A

A’length(N) length of index range of dimension N of A

A’ascending(N) length of index range of dimension N of A

(See Ashenden, page 93)



ARCHITECTURE Generate_S OF RCAdder_N IS

COMPONENT Full_Adder --defined elsewhere

PORT ( A, B, Cin : IN std_logic ;

S, Cout : OUT std_logic ) ;

END COMPONENT Full_Adder ;

SIGNAL Int_C : std_logic_VECTOR ((A’LENGTH - 1) DOWNTO 0);

BEGIN

All_Bits:

FOR I IN (A’LENGTH -1) DOWNTO 0 GENERATE


Generate Example: R-C AdderLSB: IF (I = 0) GENERATE

BEGIN

S0: Full_Adder

PORT MAP ( A(I), B(I), Cin,

Sum(I), Int_C(I) );

END GENERATE LSB ;

Middle_bits:

IF ( I < ( A’LENGTH - 1 ) AND I > 0 ) GENERATE

BEGIN

SI: Full_Adder

PORT MAP ( A(I), B(I), C(I-1),

Sum(I), Int_C(I) );

END GENERATE Middle_bits ;

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Generate Example: R-C AdderMSB:

IF ( I = A’LENGTH - 1 ) GENERATE

BEGIN

SN: Full_Adder

PORT MAP ( A(I), B(I), INT_C(I-1),

Sum(I), Cout );

END GENERATE MSB;

END GENERATE All_Bits;

END Generate_S ;


Generate Statement -- More compact

AB: for i in A’range generateonce: if i = 0 generate

L: adder port map (A(0), B(0), Cin, S(0), C(0));end generate;rest: if i /= 0 generateL: full_adder port map(A(i),B(i),C(i-1),S(i),C(i));

end generate;end generate;C_out <= C(i);

C3S3

A3 B3

C2S2

A2 B2

C1S1

A1 B1

C0S0

A0 B0

C4S4

A4 B4

Cin


Generics

• In place of constants

• As parameters to functions, entities, etc.

• Use a generic map to specify values when the function or component is used


Generics – As Constants

• Specify constants associated with an entity as generic: Example: delay

entity and_gate isgeneric (delay : time := 5 ns);port (a, b : in std_logic;

o : out std_logic);end and_gate;

architecture arch of and_gate isbegino <= a and b after delay;end arch;

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Generics – As Parameters

• Allows parametrization

• Generic MapA1 : adder generic map (width => 8);

port map (av, bv, o);

entity adder isgeneric (width : positive := 4);port (a, b : in std_logic_vector(0 to width –1);

o : out std_logic_vector(0 to width) );end adder;


Add Procedure: Unconstrained Rangesprocedure ADD (A, B: in std_logic_vector;

CIN: in std_logic;

SUM: out std_logic_vector;

COUT: out std_logic ) is

variable SUMV, AV, BV:

std_logic_vector(A’length-1 downto 0);

variable carry: std_logic;

begin

AV := A; BV := B; Carry := CIN;

for I in 0 to SUMV’High loop

SUMV(I) := AV(I) xor BV(I) xor Carry;

Carry := (AV(I) and BV(I)) or (AV(I) and Carry) or (BV(I) and Carry);

end loop;

COUT:= Carry; Sum:= SumV;

End ADD;


Generate vs unconstrained ranges

• How does adder built with a generate statement differ from ADD procedure with unconstrained ranges?


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