dls digital controller tony dobbing head of power supplies group
TRANSCRIPT
DLS Digital Controller
Tony Dobbing
Head of Power Supplies Group
Content of talk
J A Dobbing
• Features and overview
• Problem of resolution
• FPGA program structure
• Performance
• Development program
• Conclusions
J A Dobbing
DLS Digital Controller Features• Implemented on Xilink Spartan FPGA (low cost).
• Backward compatible with original PSI digital controller.
• Direct Ethernet connection to computer control network via Colibri PXA270 processor board running EPICS, 312 MHz clock, 64 MB RAM, 32 MB Flash.
• Remote parameter loading.
• Direct Ethernet port for Fast Orbit Feedback, with low latency (150 s less than original PSI controller).
• FPGA program loaded from PXA270 – remote software changes.
• USB port for local control via Labview application.
• 64 MB Flash memory (non-volatile), 64 MB DDR SRAM.
• 50MHz Clock Oscillator.
J A Dobbing
ADC/DAC Components
• 4 Channel 16 bit ADC AD974, for DC link voltage and output voltage monitoring.
• 4 off 18 bit ADC AD7691, for current measurement, with oversampling 22 bit precision is achieved.
• 4 Channel DAC LTC2604, to monitor internal signals from front panel.
J A Dobbing
DLS Digital Controller Block Diagram
24 V
XilinxSpartan 3S 1600E
FPGA
FLASH Memory
Power Converter
PWM signal
PWM synchronisation
ServicePC
(serial port)
Backplane
Computer Network
DCDC
OtherController
Cards
Analog Sig.
Programming
Timing System Front Panel Optical Input
ControlInterlocks, Digital I/O
Dual
USB
UART
RAM
Colibri
Module
PXA270
Ethernet Link
Reset
4 x DAC16 bit
4x ADC16 bit
4X ADC18 bit
Analog Sig.
Ethernet LinkFast Orbit Feedback System
J A Dobbing
DLS Controller - Module
Ethernet Ports
USB Port
Optical Trig
DAC O/P
18 bit ADC Cover
PXA270
FPGA
J A Dobbing
LabView Interface – Summary and Scope
J A Dobbing
LabView Interface – Parameters and Waveforms
J A Dobbing
The Problem of Resolution with a Digital Controller
Resolution = Clock Period/PWM Period
For a power supply operating with a PWM of 100 kHz and a 50 MHz processor clock.
Resolution = 20ns/10 s
= 0.2% (which is not enough by far)
J A Dobbing
Xilink Quadrant Phase Shift
Solutions:-
• Increase clock frequency.
• Xilink output quadrant phase shift, effectively increases resolution to 4 times clock frequency.
• E.g. 200 MHz clock with phase shifting gives 125 ppm resolution for 100 kHz PWM.
Better but still not enough!
J A Dobbing
DLS Controller PWM Resolution
5 ns PWM resolution with 20 ns clock
J A Dobbing
Clock Pulse Averaging
K+
+Round to nearest integer
+-
Sum
Sum errors and add running total to next cycle
Integer number of clock pulses/quadrants to
PWM generator
ModulationIndex
Convert to clock pulses
Average PWM output resolution is now limited only by computation word length.
J A Dobbing
Spartan 3E FPGA Structure
• 3688 Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables that implement logic plus storage elements. CLBs perform a wide variety of logical functions as well as store data.
• 376 Input/Output Channels with Blocks (IOBs) controlling the flow of data between the I/O pins and the internal logic of the device. Each IOB supports bidirectional data flow plus 3-state operation.
• 648 Kbits Block RAM provides data storage in the form of 18-Kbit dual-port blocks.
• 36 Dedicated Multiplier Blocks.• Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying,
multiplying, dividing, and phase-shifting clock signals.
J A Dobbing
FPGA Program Structure
ADCinterface
Register
Scaling and filtering
Register
Feedback
Register
Modulation index to
clock pulses
Register
PWM Generation
Protection
Register
Load
64 clock pulses or 1.28 s
J A Dobbing
Controller Performance - ADC Noise
Filter Level (Hz) Noise Level RMS ppm
10 0.34
100 0.54
1000 1.4
10,000 4.4
The noise level of the output current, when Power Supply is running at 1 A
J A Dobbing
Waveform
Filtered Output Current Unfiltered Output Current
Controller Performance - Resolution100A/5Hz Waveform and Resulting Unfiltered Output Current and
Measured Output Current Filtered at 100 Hz.
J A Dobbing
Controller Performance - Stability
0 2 4 6 8 10 12 14 16 18 20-6
-4
-2
0
2
4
6
8Power Supply Stability
Cur
rent
var
iatio
n (p
pm)
Time (h)
Stability over 20h with 100 mH Load
J A Dobbing
Controller Performance - Linearity
-6 -4 -2 0 2 4 6-300
-200
-100
0
100
200
300Power Supply Linearity Error
Current Ref (A)
Pow
er S
uppl
y Li
near
ity E
rror
(pp
m)
J A Dobbing
Development Programme for Booster Fast Orbit Feedback System
• One controller presently operating on Booster corrector.
• Upgrade 11 Booster corrector controllers in June 2012.
• Upgrade remaining 33 Booster corrector controllers in August 2012.
• Develop feedback algorithm to exploit reduced latency.
• Upgrade Storage Ring FOFB system.
J A Dobbing
Conclusions
• All diamond’s power supplies use the original very successful PSI digital controller.
• The Cirrus ADC used in this controller is no longer available.
• Diamond now has its own replacement, that is pin compatible and has significantly reduced latency, which makes it better for fast orbit feedback applications.
• The PXA270 processor eliminated the need for additional hardware between the power supply and computer control network.