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Migration From AT89C51SND1C toAT83C51SDN1C

This application note details the differences between AT89C51SND1C andAT83C51SDN1C products, and gives some tips and tricks to the user when migratingfrom Flash to ROM product from a hardware and firmware point of view.

MP3

Microcontrollers

Application Note

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AT8xC51SND1C Application Note 4244AMP305/03

Memory Architecture The AT83C51SND1C product provides the internal program/code memory in ROMmemory while the AT89C51SND1C product provides it in Flash memory.

AT83C51SDN1C MemoryArchitecture

Figure 1. ROM Memory Architecture

As shown in Figure 1 the AT83C51SDN1C ROM memory is composed of only one userspace detailed as follows.

User Space This space is composed of a 64K Bytes ROM memory programmed during the manu-facturing process. It contains the users application code.

AT89C51SND1C MemoryArchitecture

Figure 2. Flash Memory Architecture

As shown in Figure 2 the AT89C51SND1C Flash memory is composed of four spacesdetailed as follows.

User Space This space is composed of a 64K Bytes Flash memory organized in 512 pages of 128Bytes. It contains the users application code.

This space can be read or written by both software and hardware modes.

Boot Space This space is composed of a 4K Bytes Flash memory. It contains the bootloader for In-System Programming and the routines for In Application Programming.

This space can only be read or written by hardware mode using a parallel programmingtool.

Hardware Security Space This space is composed of one Byte: the Hardware Security Byte (HSB) divided in 2separate nibbles. The MSN contains the X2 mode configuration bit and the Bootloader

FFFFh

64K Bytes

ROM Memory

0000h

User

FFFFh

64K Bytes

Flash Memory

0000h

Hardware Security

User

4K Bytes

Flash Memory

FFFFh

F000hBoot

Extra Row

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AT8xC51SND1C Application Note

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Jump Bit and can be written by software while the LSN contains the lock system level toprotect the memory content against piracy and can only be written by hardware.

Extra Row Space This space is composed of 2 Bytes:

The Software Boot Vector (SBV).This Byte is used by the software bootloader to build the boot address.

The Software Security Byte (SSB).This Byte is used to lock the execution of some bootloader commands.

User Constraints Due to its ROM technology, the AT83C51SND1C product does not allow In-System andIn-Application Programming and therefore, does not implement any boot space, hard-ware security space and extra row space.

No Boot Space or Extra RowSpace

Attempting to enable the boot memory through software or hardware boot condition willresult in no effect. Then, jumping to the boot entry address (F000h) will jump in internaluser ROM.

Software boot conditionENBOOT bit in AUXR1 register (see Table 1) is not implemented inAT83C51SDN1C product.

Note: User must take care not to write to ENBOOT bit.

ISP pin (see Figure 3) is not implemented in AT83C51SDN1C product.

Note: User must take care to leave this pin unconnected.

Hardware Security Space Since the HSB register (see Table 3) is not implemented, the AT83C51SND1C productdoes not provide any programmable hardware security system. Internal ROM content isalways secured because there is no way to read it externally.

Moreover the AT83C51SND1C product does not implement X2B bit in HSB disallowingto start automatically in X2 mode.

Note: User must take care to always set the X2 bit in CKCON register by firmware in the appli-

cation start-up routine if needed.

Version Register The AT83C51SND1C product NVERS register (see Table 2) is set to 0XXX XXXXb(ROM product) while it is set to 1XXX XXXXb in the AT89C51SND1C product.

Note: User must take care of NVERS register usage in its code to avoid any infinite loop thatmay have been implemented to secure firmware from old product versions usage.

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Pinout Figure 3. AT8xC51SND1C 80-pin QFP Package

Note: 1. ISP for AT89C51SND1C, NC for AT83C51SDN1C. Do not connect this pin when

using AT83C51SDN1C.

AT89C51SND1C-RO (Flash)AT83C51SDN1C-RO (ROM)

P0.3/AD3

P0.4/AD4

P0.5/AD5

VSS

VDD

P0.6/AD6

P0.7/AD7

P2.0/A8

P2.1/A9

P3.1

/TXD

P3.2

/INT0

P3.3

/INT1

P3

.4/T0

P3.0

/RXD

1

2

3

4

5

6

7

8

13

11

10

P2.2/A10

P2.3/A11

P2.4/A12

P2.6/A14

P2.5/A13

P2.7/A15

MCLK

MDATMCMD

P0.2/AD2

P0.1/AD1

P0.0/AD0

PVSS

VSS

X2

X1

TST

VSS

9

12

14

15

16

P4.3/SS

P4.2/SCK

P4.1/MOSI

P4.0/MISO

VSS

VDD

RST

SCLK

DSEL

DCLK

DOUT

AIN1

AIN0

AR

EFN

AR

EFP

A

VSS

A

VDD

P3.7/RD

P3.6/WR

P3

.5/T1

VDD

P1.0/KIN0

P1.1/KIN1

P1.2/KIN2

P1.3/KIN3

P1.4

P1.5

P1.7/SDA

FILTPVDD

VDD

P1.6/SCL

17

18

19

20

2122232425262728

33

313029

3234353637383940

41

42

43

44

45

46

47

48

53

51

50

49

52

54

55

56

57

58

59

60

616263646566676873 71 70 697274757677787980

ALE

ISP/NC(1)

UVDD

UVSS

P5.0

P5.1

P4.7

P4.6

D-D+

P5.3

P5.2

VSS

VDD

P4.5

P4.4

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AT8xC51SND1C Application Note

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Registers Table 1. AUXR1 RegisterAUXR1 (S:A2h)Auxiliary Register 1

Reset Value = XXXX 00X0b

Note: 1. This bit is not implemented in AT83C51SDN1C product. Do not set this bit.

Table 2. NVERS Register (Read Only)NVERS (S:FBh)Version Register

Reset Value = 0XXX XXXXb (AT83C51SDN1C) or 1XXX XXXXb (AT89C51SND1C)

7 6 5 4 3 2 1 0

- - ENBOOT - GF3 0 - DPS

Bit NumberBit

Mnemonic Description

7 - 6 -Reserved

The value read from these bits are indeterminate. Do not set these bits.

5 ENBOOT(1)

Enable Boot Flash

Set this bit to map the boot Flash in the code space between at addresses

F000h to FFFFh.

Clear this bit to disable boot Flash.

4 -Reserved

The value read from this bit is indeterminate. Do not set this bit.

3 GF3General Flag

This bit is a general-purpose user flag.

2 0

Always Zero

This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3

flag.

1 - Reserved for Data Pointer Extension.

0 DPS

Data Pointer Select Bit

Set to select second data pointer: DPTR1.

Clear to select first data pointer: DPTR0.

7 6 5 4 3 2 1 0

V7 V6 V5 V4 V3 V2 V1 V0

Bit

Number

Bit


7 - 0 V0:7 Value of these bits depends on hardware version.

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Table 3. HSB ByteHardware Security Byte

Reset Value = XXUU UXXX, UUUU UUUU after an hardware full chip erase.

Notes: 1. On AT89C51SND1C X2B initializes the X2 bit in CKCON during the reset phase.

2. Bits 0 to 3 (MSN) can only be programmed by hardware mode.

7 6 5 4 3 2 1 0

X2B BLJB - - - LB2 LB1 LB0

Bit

Number

Bit


7 X2B(1)X2 Bit

Program this bit to start in X2 mode.

Unprogram (erase) this bit to start in standard mode.

6 BLJB

Bootloader Jump Bit

Program this bit to execute the bootloader at address F000h on next reset.

Unprogram (erase) this bit to execute user s application at address 0000h on

next reset.

5 - 4 -

Reserved

The value read from these bits is always unprogrammed. Do not program these

bits.

3

Reserved

The value read from this bit is always unprogrammed. Do not program this bit.

2 - 0 LB2:0Hardware Lock Bits

Refer to for bits description.

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Atmel Corporat ion 20 03 .Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company s standard warrantywhich is detailed in Atmel s Terms and Conditions located on the Companys web site. The Company assumes no responsibility for any errorswhich may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and doesnot make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are grantedby the Company in connection with the sale of Atmel products, expressly or by implication. Atmels products are not authorized for use as criticalcomponents in life support devices or systems.

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