doping profile dependence of the vertical impact ionization mosfet’s (i-mos) performance
DESCRIPTION
Doping Profile Dependence of the Vertical Impact Ionization MOSFET’s (I-MOS) Performance. Nano and Giga Challenges in Electronics and Photonics NGC 2007 Phoenix, Arizona, USA 16 March 2007. Overview. Motivation Vertical Impact Ionisation MOSFET (IMOS): Device Concept - PowerPoint PPT PresentationTRANSCRIPT
Ulrich Abelein, Mathias Born, Markus Schindler, Andreas Assmuth, Peter Iskra, Torsten Sulima, Ignaz Eisele
Doping Profile Dependence of the Vertical Doping Profile Dependence of the Vertical Impact Ionization MOSFET’s (I-MOS) Impact Ionization MOSFET’s (I-MOS)
PerformancePerformance
Nano and Giga Challenges in Electronics and Photonics
NGC 2007
Phoenix, Arizona, USA
16 March 2007
Ulrich Abelein 2NGC 2007
OverviewOverview
• Motivation
• Vertical Impact Ionisation MOSFET (IMOS):– Device Concept– Influence of Doping Profiles
• Electrical Characterization
• Summary and Outlook
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MotivationMotivation
Conventional MOSFET:
Subthreshold slope S = dVG/d(logID) is diffusion limited.
min S = kT/q · ln10 = 60 mV/dec @ 300 K
Minimum static leakage current ILEAK:
ILEAK = ID(VT) · 10-VT/S
Shrinking the feature size according to Moore‘s Law makes a reduction of VT necessary.
ILEAK
Solution Reducing S below the kT/q limit!
Achievable by gate controlled impact ionisation
Impact Ionisation MOSFET (IMOS)
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Device Concept – Device StructureDevice Concept – Device Structure
n+ Si source
n+ Si drain
i- Si
i- Si
p+ delta layer
Gate oxide (4.5 nm)
Gate oxide (4.5 nm)Drain contact
n+ Poly
n+ Poly
Gate contact
Source contact
Spacer Spacer
Schematic drawing of the vertical IMOS (above) and SIMS profile of the mesa layer stack (left hand side)
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Device Concept – Simulation ResultsDevice Concept – Simulation Results
n+ Si source
n+ Si drain
i- Si
i- Si
p+ delta layer
Gate oxide
Drain contact
n+ Poly
Gatecontact
Source contact
Spacer Spacer
-
-2 -1 0 1
Energy in eV
1010 1020 1030
Ionisation rate in pairs / (cm3s)
0
80
Dis
tan
ce i
n n
m
Drain
Source
VGS=VDS=0 VVGS=0 V; VDS=2 VVGS = VDS=2 V
p+ delta barrier lowered by gate field
High field between p+ delta layer and drain
causes impact ionisation
Simulations of the electric field and the ionisation rate in the channel region
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Device Concept – Operating ModesDevice Concept – Operating Modes
VDS < 1.25 V Conventional MOSFET mode
2.2 V > VDS > 1.25 V Impact Ionization Mode Holes generated by
impact ionization charge the body.
Dynamic lowering of VT!
VDS > 2.2 V Bipolar Mode Parasitic bipolar transistor contributes to ID
W = 2µm
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Device Concept – Operating ModesDevice Concept – Operating Modes
VDS < 1.25 V Conventional
MOSFET mode
VDS > 1.25 V Beginning of
significant impact ionziation
Holes generated by impact
ionization charge the body
Dynamic lowering of VT
S is reduced below kT/q
W = 2 µm
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Influence of Doping ProfilesInfluence of Doping Profiles
Unintentional changes in doping profiles due to diffusion!
p+ delta layer doping diffuses into intrinsic zones!
Diffusion Sharper delta layer, larger barrier, higher eelctric fields!
Impact Ionization rates (at const. VDS)
Lower S due to increased body charge for low VDS
Diffusion Lower barrier
Switch on voltage of parasitic bipolar transistor
Extremley low S due to current amplification
Hysteresis in input characteristics
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Experimental Results – Doping ProfilesExperimental Results – Doping Profiles
Using 750 °C and 800 °C gate oxide process:
Decreasing of boron diffusion for 750 °C
Maximum doping level increased by a factor of 3
Larger barrier!
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Electrical Characerization – Output CharacteristicsElectrical Characerization – Output Characteristics
Low thermal budget sample
Impact ionization mode begins at lower voltage
Later transistion to bipolar mode
VDS = 2.25 V
• LT sample in Impact Ioniziation mode
• HT sample in bipolar mode
W = 2 µm
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Electrical Characerization – Input CharacteristicsElectrical Characerization – Input Characteristics
VDS = 2.25 V
LT sample in Impact Ioniziation mode
S = 4 mV/dec
No hysteresis!W = 2 µm
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Electrical Characerization – Input CharacteristicsElectrical Characerization – Input Characteristics
VDS = 2.25 V
HT sample in bipolar mode
S = 1.06 mV/dec!
Hysteresis visible
Gate controlled switch-off possible!
W = 2µm
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Summary and OutlookSummary and Outlook
Summary:
• Influence of boron diffusion on device performance was shown• Subthreshold slope of 1.06 mV/dec was shown• Devcie can be optimized to needs of application
– Very low subthreshold slope with measurable hysteresis– Low subthreshold slope without any hystersis
Outlook:
• Realization of the p-channel device• Shrinking device dimensions and reducing supply voltages