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EE 105 Fall 1998Lecture 13
MOSFET Geometry in SPICE
■ Statement for MOSFET ... D,G,S,B are node numbers for drain, gate, source, and bulk terminals
Mname D G S B MODname L= _ W=_ AD= _ AS=_ PD=_ PS=_
MODname specifies the model name for the MOSFET
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AS = W × Ldiff (source)
Ldiff (source) Ldiff (drain)
AD = W × Ldiff (drain)
NRS = N (source)PS = 2 × Ldiff (source) = W
NRD = N (drain)PD = 2 × Ldiff (drain) = W
W
L
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EE 105 Fall 1998Lecture 13
MOSFET Model Statement
.MODEL MODname NMOS/PMOS VTO=_ KP=_ GAMMA= _ PHI=_LAMBDA= _ RD=_ RS=_ RSH=_ CBD=_ CBS=_CJ=_ MJ=_ CJSW=_MJSW=_ PB=_ IS= _ CGDO=_ CGSO=_ CGBO=_ TOX=_ LD=_
DC Drain Current Equations:
Parameter name (SPICE / this text)
SPICE symbol Eqs. (4.93), (4.94)
Analytical symbol Eqs. (4.59), (4.60)
Units
channel length Leff L m
polysilicon gate length L Lgate m
lateral diffusion/gate-source overlap
LD LD m
transconductance parameter KP µnCox A/V2
threshold voltage /zero-bias threshold
VTO VTnO V
channel-length modulation parameter
LAMBDA λn V-1
bulk threshold / backgate effect parameter
GAMMA γn V1/2
surface potential / depletion drop in inversion
PHI - φp V
IDS 0 V( GS V– TH)≤=
IDSKP2
-------- W Leff⁄( )VDS 2 VGS VTH–( ) VDS–[ ] 1 LAMBDA VDS⋅+( )= 0 VDS VGS VTH–≤ ≤( )
IDSKP2
-------- W Leff⁄( ) VGS VTH–( )2
1 LAMBDA VDS⋅+( )= 0 VGS VTH– VDS≤≤( )
VTH VTO GAMMA 2 PHI⋅ VBS– 2 PHI⋅–( )+=
EE 105 Fall 1998Lecture 13
Capacitances
SPICE includes the “sidewall” capacitance due to the perimeter of the source and drain junctions --
Gate-source and gate-drain overlap capacitance are specified by CGDO and CGSO (units: F/m).
Level 1 MOSFET model:
.MODEL MODN NMOS LEVEL=1 VTO=1 KP=50U LAMBDA=.033 GAMMA=.6+ PHI=0.8 TOX=1.5E-10 CGDO=5E-10 CGSO= 5e-10 CJ=1E-4 CJSW=5E-10+ MJ=0.5 PB=0.95
The Level 1 model is adequate for channel lengths longer than about 1.5 µm
For sub-µm MOSFETs, BSIM = “Berkeley Short-Channel IGFET Model” developed by Profs. P. Ko (now at HKUST) and C. Hu and their students is the industry-standard SPICE model for MOSFETs.
n+ drain
CBD VBD( ) CJ AD⋅
1 VBD PB⁄–( )MJ------------------------------------------- CJSW PD⋅
1 VBD PB⁄–( )MJSW---------------------------------------------------+=
(area) (perimeter)
EE 105 Fall 1998Lecture 13
SPICE Statement for a MOSFET
A
B
F
VDD
VSS
VDD
VSS
0 2 4 6 8 10 12 14 16 18 20 µm
02
46
810
1214
1618
20µ m
EE 105 Fall 1998Lecture 13
SPICE Netlist for Extracted Circuit
■ Number nodes sequentially; let VSS = 0 , VDD = 5 V, and VB = 5 V.
.
VF
(3/1)
(3/1)
(4.5/1)(4.5/1)
Cw
CA-SS
CA-DD
CB-SS
CB-DD
+-5 V
0
1
-+VA
2
3
4
M1
M2
M3
M4
EE 105 Fall 1998Lecture 13
SPICE Input File
■ Source File (parastic and load capacitors omitted since the output we want the DC transfer curve and not a transient response)
* simple NAND gateVDD 1 0 5VA 2 0 DCM1 3 2 0 0 modn W=3u L=1u AD=3p AS=12p PD=2u PS=10uM2 4 1 3 0 modn W=3u L=1u AD=12p AS=3p PD=10u PS=2uM3 4 2 1 1 modp W=4.5u L=1u AD=8p AS=18p PD=2u PS=12.5uM4 4 1 1 1 modp W=4.5u L=1u AD=8p AS=18p PD=2u PS=12.5u* standard H&S level 1 models for L = 1 um.model modn nmos level=1 vto=1 kp=50u lambda=.1 gamma=.6 phi=.8 tox=15e-9+ cgdo=.5e-9 cgso=.5e-9 cj=.1e-3 cjsw=.5e-9 mj=.5 pb=.95.model modp pmos level=1 vto=-1 kp=25u lambda=.1 gamma=.6 phi=.8 tox=15e-9+ cgdo=.5e-9 cgso=.5e-9 cj=.3e-3 cjsw=.35e-9 mj=.5 pb=.89* dc transfer curve for VA = 0 to 5 V with 0.1 V steps.DC VA 0 5 0.1.END
■ Spice3 command line syntax
Spice 1 -> load sourcefile
Spice 2 -> run
Spice 3 -> plot v(4)
EE 105 Fall 1998Lecture 13
Graphical Output
EE 105 Fall 1998Lecture 13
Digital Electronics
■ Assign “1” and “0” to a range of voltage (or current), with a separation that minimizes a transition region
We will use positive logic (usually the case)
Simplest binary function: inversion
Circuit must take the “1” voltage range at the input and deliver the “0” voltage range at the output.
Logic0
Positive Logic Negative Logic
Voltage
Logic1
Logic0
Logic1
Transition Region Transition Region
A BA B
1
1 0
0
EE 105 Fall 1998Lecture 13
Boolean Algebra
■ Standard logic functions
A
B
C
A B AB C
C = ABNAND (not AND) gate
A
B
C
A B A+B C
C = A+BNOR (not OR) gate
EE 105 Fall 1998Lecture 13
Boolean Algebra
■ Adding two-digit binary numbers:
Truth table
Synthesis using standard NAND and NOR gates: C = AB, (XOR)
A + B = F
(and carry = C)
A
B
F
C
A B F C
F A B⊗=