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1Lecture 4: Transistor Summary/Inverter Analysis
Subthreshold MOSFET currents
IEEE Spectrum, 7/99, p. 26
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2Lecture 4: Transistor Summary/Inverter Analysis
ID versus VDS
-4
VDS (V)0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5x 10
I D (
A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10
-4
VDS (V)
I D (
A)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
ResistiveSaturation
VDS = VGS - VT
Long Channel Short Channel
© Digital Integrated Circuits2nd
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3Lecture 4: Transistor Summary/Inverter Analysis
Current-Voltage Relations in the Deep-Submicron Era
LinearRelationship
-4
VDS (V)0 0.5 1 1.5 3 3.3
0
0.5
1
1.5
2
2.5x 10
I D (
A)
VGS= 3.3 V
VGS= 2.5 V
VGS= 1.65 V
VGS= 1.0 V
nFET
2.5
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4Lecture 4: Transistor Summary/Inverter Analysis
Current-Voltage Relations in the Deep-Submicron Era
LinearRelationship
VGS= -3.3 V
VGS= -2.5 V
VGS= -1.65 V
VGS= -1.0 V
-4
0
-0.5
-1
-1.5
-2
-2.5 x 10
I D (
A)
0
VDS (V)
-0.5-1.0-1.5-3.0-3.3 -2.5
pFET
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-4
VDS
(V)
0 0.5 1 1.5 3 3.30
0.5
1
1.5
2
2.5x 10
I D (
A)
VGS= 3.3 V
VGS= 2.5 V
VGS= 1.65 V
VGS= 1.0 V
2.5
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VGS= -3.3 V
VGS= -2.5 V
VGS= -1.65 V
VGS= -1.0 V
V
DS
(V)
-0.5-1.0-1.5-3.0-3.3
-4
0
-0.5
-1
-1.5
-2
-2.5x 10
ID (A)
0
-2.5
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7Lecture 4: Transistor Summary/Inverter Analysis
W/L and transistor sizing
Length L
SourceGate
Channel
Wid
th W
Contact
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VGS= -3.3 V
VGS= -2.5 V
VGS= -1.65 V
VGS= -1.0 V
-4
0
-0.5
-1
-1.5
-2
-2.5 x 10
I D (A
)
0
V
DS
(V)
-0.5-1.0-1.5-3.0-3.3 -2.5
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9Lecture 4: Transistor Summary/Inverter Analysis
Inverter layout
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10Lecture 4: Transistor Summary/Inverter Analysis
Some Definitions
Voh output voltage highVol output voltage low
Vih minimum allowed voltage input for a logic-low output
Vil maximum allowed voltage input for a logic-high output
Noise margin: NML = Vil – Vol NMH = Voh – Vih
Vm switching threshold (where Vout=Vin)
Fan-in: The number of inputs to a gateFan-out: The number of loads (min geometry) the gate drives
Propagation delay: The signal delay through a gate (50% points of input and output)
Rise and fall times: Time for a signal to transition from 10% to 90% of its logic swing
Power–delay product (gate power)×(gate prop delay)
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11Lecture 4: Transistor Summary/Inverter Analysis
n / p ratio (kn/kp)
Vinv is set by n / p You can size the transistors to place Vinv where you want it
Affects noise margin and speed
Optimal noise margin: Make p FET wider than n FETn
p
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12Lecture 4: Transistor Summary/Inverter Analysis
Switching Threshold as a function of Transistor Ratio
100
101
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
MV
(V
)
Wp
/Wn © Digital Integrated Circuits2nd
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13Lecture 4: Transistor Summary/Inverter Analysis
Inverter power dissipation
Static power Dissipation when the inverter isn’t switching Primarily subthreshold currents
And very small noise currents
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14Lecture 4: Transistor Summary/Inverter Analysis
Inverter power dissipation (con’t)
Dynamic power: Direct-path current pFET and nFET are both on during switching
Direct current path from Vdd to gnd Integrate curve to find energy loss Edirect
Dissipation = Edirect × switching frequency
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15Lecture 4: Transistor Summary/Inverter Analysis
Inverter power dissipation (con’t)
Dynamic power: Driving load capacitance Charge capacitor to Vdd; then discharge to gnd Dissipation = CVdd
2 × switching frequency