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Microelectronic Circuit DesignMcGraw-Hill
Chapter 15
Multistage Amplifiers
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
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Chapter Goals
Understand analysis and design of ac-coupled multistage amplifiers
including voltage gain, input and output resistances and small signal
limitations.
Understand analysis and design of dc-coupled multistage amplifiers.
Discuss characteristics of Darlington configuration and cascodeamplifier.
Explore dc and ac properties of differential amplifiers.
Understand basic three-stage op amp.
Explore design of class-A, class-B, class-AB output stages.
Discuss characteristics and design of electronic current sources.
Continue understanding the use of SPICE in circuit analysis.
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AC-coupled Amplifiers: Circuit
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AC-coupled Amplifiers: Description
MOSFETM1operating in C-S configuration provides high input
resistance and moderate voltage gain.
BJT Q2 in C-E configuration, the second stage, provides high gain.
BJT Q3, an emitter-follower gives low output resistance and buffers the
high gain stage from the relatively low load resistance. Bias resistors are replaced by
Input and output of overall amplifier is ac-coupled through capacitors
C1 and C6.
Bypass capacitors C2 and C4 are used to get maximum voltage gain
from the two inverting amplifiers.
Interstage coupling capacitors C3 and C5 transfer ac signals between
amplifiers but provide isolation at dc, and prevent Q-points of the
transistors from being affected.
212RR
BR
433RR
BR
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AC-coupled Amplifiers: Equivalent
Circuits
AC
Equivalent
Small-signal
Equivalent
DC
Equivalent
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AC-coupled Amplifiers: Input
Resistance and Voltage Gain
598k2.176201
I
R
k31.4k8.51k7.42
I
R
232250k3.33
L
R
M1 GRinR
-4.78478S01.011
1v2
v
1
LR
mg
vA
k54.33
)13
(32
322
LR
or
IR
inR
IR
LR
-222k54.3mS8.62
222v
3v
2
L
Rm
gv
A
950.0
3)1
3(
3
3)1
3(
3vov
3
LR
or
LR
ov
A
998123
inR
IR
inR
vA
vA
vAvA
47823905982
598211
r
inR
IR
LR
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AC-coupled Amplifiers: Output
Resistance
3990542004310
222xixv
3
or
IRRCEoutI
Rth
R
To find output resistance, testvoltage is applied at amplifier
output.
5.6081
3990
S0796.0
988.03300
13
3
3
33300
3
3300
xi
xv
3
xv
3300xv
eirixi
o
thR
mg
o
out
R
out
R
outR
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AC-coupled Amplifiers: Current and
Power Gain
Input current delivered to amplifier from source is
and current delivered to load by amplifier is
iv71090.9i
v
ii
inR
IR
sv99.3250
s998v
250iv
250ov
oi vA
61003.4
iv71090.9
i3.99v
iioi
iA
91002.461003.4998
iioi
ivov
iAvA
sPoP
PA
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AC-coupled Amplifiers: Input Signal
Range For first stage,
For second stage,
For third stage,
On the whole,
V202.0990.0
)21(2.0)(2.0 iv
TNV
GSV
1v
mV06.1
0.990
mV05.1mV05.1
4.78
0.005mV5
mV5
iv
v1A
1v
1v
v1A
2v
be2v
V7.92005.0
)990.0(21
331
mV5
3
331
)sv990.0(21
331
3v
be3v
vAvA
LR
mg
i
v
be
v
LR
mgv
Av
A
LR
mg
V7.92V)7.92mV,06.1mV,202min( iv
mV5.92V)7.92(998V)7.92( vAov
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AC-coupled Amplifiers: Methods to
Improve Voltage Gain
Gain of C-S amplifier is inversely proportional to square root of drain
current, so voltage gain could be increased by reducingID1 while
maintaining a constant voltage drop acrossRD1. Signal range could be
improved by increasing current in output stage and voltage drop across
RE3. Q1 could be replaced with a FET. This could cause gain loss in third
stage since gain of C-D amplifier is typically < that of a C-C stage.
However, this loss could be made up by improving gain of first and
second stages.
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Common-Emitter Cascade
To achieve maximum gain, severalC-E stages can be cascaded.
For the final stage,
For all other stages,
1231-n
vov...
1v2
v
iv1
v
vA
vA
vAvA
CCV
LRmngvnA 10
)1
(
i
rLi
Rmi
gvi
A
If gain is limited by interstage resistances,each stage has a gain of about -10VCCand
overall gain is:
If gain is limited by input resistance oftransistors, it is given by:
Normally as signal and powerlevels usually increase in each successive
stage of most amplifiers. Since o< 10VCC,
this case often represents the actual limit.
n
CCVvnA
10
CCVonoo
CnIC
InvnA 10...32
11
1CICnI
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Direct-coupled Amplifiers: Circuit
Coupling capacitors in series with signal path-
C1, C3, C5, and C6 are eliminated as they prevent
the amplifier from providing gain at dc or verylow frequencies.
Additional bias resistors in individual stages
are also removed, making design less expensive.
Bypass capacitors- C2 and C4affect gain at low frequencies
but dont inherently prevent the
amplifier from operating at dc.
Symmetrical power supplies
are used to set Q-point voltages
at input and output to about
zero.
Alternatingpnp orp-channel
and npn orn-channel transistorsare used from stage to stage to
take maximum advantage of
available power supply voltage.
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Direct-coupled Amplifiers: DC Analysis
Voltage at drain ofM1 provides base
bias forQ2 and voltage at collector of
Q2 provides base bias forQ3. Alltransistors operate in active region
irrespective of direct connection
between stages.
2216005.7(0
2
01.02
2
DI
TNV
GSVn
KDI
So,ID = 6.66. mA (which would produce 10.7
V drop acrossRS1 and cut off FET) orID =5.29
mA (correct value).
IB2
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Direct-coupled Amplifiers: DC Analysis
(contd.)
0.4V0.7V-V10.1 BE3V
C2VoV
mA99.32503300
V5.7
o
VoV
LI
3I
E3I
F3 = 80, soIC3 =3.94 mA andIB3 = 49.3 mA
V10.70.40V-5.75.7 E3V
CE3V thus Q3 is in active region.
There is an offset voltage of 0.4 V at output and a nonzero dc current exists in
250 W load resistor. In an ideal design, offset voltage would be zero and no dc
current would appear in load.
Based on Q-point values, small-signal parameters can be calculated.
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Direct-coupled Amplifiers: AC Analysis
Values of interstage capacitors are
higher than those in ac-coupled
amplifier due to absence of bias
resistors.
Overall characteristics are similar to
those in ac-coupled amplifier as Q-
points and small-signal parameters of
transistors are similar
Dc coupling requires fewer
components than ac-coupling
but Q-points of various stages
become interdependent.
If Q-point of one stage shifts,Q-points of all other stages
might also shift.
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Direct-coupled Amplifiers: Darlington
Circuit
Darlington circuit behaves similar to
the single transistor but has a current
gain given by the product of current
gains of individual transistors.
DC Analysis: ForF1
, F2
>>1,
VBEof composite transistor = 2 diode
voltage drops. So VCE>(VBE1 + VBE2) .
BI
F2F1C2I
C1I
CI
AC Analysis: For the composite transistor,
212
1
11'
ro
yr
012
y
2/221
'm
gymg
o2ryor )3/2(
1
22'
21
0211
21'oo
v
y
y
o
3/2
02
1v2
v'
fi
fmm
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Direct-coupled Amplifiers: Cascode
Circuit
Cascode circuit is cascade connection
of C-E and C-B amplifiers, used in
high gain amplifiers and high output
resistance current sources.
DC Analysis: For a high current gain,
For forward-active operation of Q2,C1
IC1
IFC2
IC
I
AC Analysis: For the composite transistor,
1
1
11'
ryr
012
y
121'
mgymg
o2r
o2yor
1
22'
1
0211
21'o
v
y
y
o
220
21
v2
v'
foi
fmm
BEV
BBV
BE1V
BE2V
BBV
CE1V 2
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Differential Amplifiers
Differential amplifiers,also considered
the C-C/C-B cascade, eliminate the
bypass capacitors as well as the
external coupling capacitors at theinput and output of direct-coupled
amplifiers.
Each circuit has two inputs.
Differential-mode output
voltage is the voltage
difference between collectors,
drains of the two
transistors.Ground referenced
outputs can also be taken fromcollector/drain.
Ideal differential amplifier
uses perfectly matched
transistors.
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Bipolar Differential Amplifiers: DC
Analysis
Both inputs are set to zero,
emitters are connected together.
If transistors are matched,
BEV
BE2V
BE1V
CV
C2V
C1V
CI
C2I
C1I
EI
E2I
E1I
BI
B2I
B1I
EE2R
BEV
EEV
EI
E
I
FC
I
F
CI
B
I
CR
CI
CCV
C2V
C1V CE2
VCE1
V
V0C2
VC1
VOD
V
Terminal currents are also equal.
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Small-Signal Transfer Characteristic
T
V2idv
CI
T
V2BE2v
BE1v
CI
C2I
C1I tanh2tanh2
The current switch is a digital application of the differential amplifier.
Large-signal transfer characteristic of differential amplifier is given by:
Even-order distortion terms are eliminated.This increases signal-handling
capability of differential pair. For small-signal operation, liner term mustbe dominant. Hence, we set the third-order term to be one-tenth the linear
term.
...
7
315
175
15
23
3
12
TV2idv
TV2idv
TV2idv
TV2idv
CI
mV273.02 idv
TV
idv
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Bipolar Differential Amplifiers: DC
Analysis (Example)
Problem:Find Q-points of transistors in the differential amplifier.
Given data:VCC=VEE=15 V,REE=RC=75k,F=100
Analysis:
A3.95)3102(75
V7.015
m
EE2R
BEV
EEV
EI
A4.94101
100m
EI
EI
FCI
A944.0
100
A4.94m
m
F
CI
BI
V62.8V)7.0(--V92.7
V92.715
EV
CV
CEV
CR
CI
CV Due to symmetry, both
transistors are biased at Q-
point (94.4 mA, 8.62V)
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Bipolar Differential Amplifiers: AC
Analysis
21 id
v
icvv 22 id
v
icvv
Circuit analysis is done by
superposition of differential-mode
and common-mode signal portions.
21 cvcvodv 221 c
v
c
v
ocv
icvidv
ccAcd
A
dcAdd
A
ocvodv
Add= differential-mode gain
Acd= common-mode to differential-mode
conversion gain
Acc = common-mode gain
Adc = differential mode to common-modeconversion gain
For ideal symmetrical amplifier,Acd=Adc = 0.
Purely differential-mode input gives purely
differential-mode output and vice versa.
icvid
v
ccAdd
A
ocvod
v 0
0
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Bipolar Differential Amplifiers: Differential-
mode Gain and Input Resistance
0ev0)22(ev
ev)4v
3v)((
mggEEG
EEGgmg
2id
v
4v
ev2idv
3v ev
2idv
4v
Output signal voltages are:
2idv
c1v
CRmg 2
idvc2
vC
Rmg
idv
odv
CRmg
2id
v
3v
Emitter node in differential amplifier representsvirtual ground for differential-mode input signals.
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Bipolar Differential Amplifiers: Differential-
mode Gain and Input Resistance (contd.)
CRmgdd
A
0ic
vidvod
v
Differential-mode gain for balanced output, is:
If either vc1 or vc2 is used alone as output, output is said to be single-ended.
c2v
c1v
odv
220
icvid
vc1
v
1dd
AC
Rmg
ddA
22
0ic
vidvc2
v
2dd
AC
Rmg
ddA
Differential-mode input resistance is small-signal resistance presented to
differential-mode input voltage between the two transistor bases.
If vid =0, . For single-ended outputs,
ridR 2
b1i/
idv
CRorC
Rod
R 2)(2 CR
odR
r
)2/id
v(
b1i
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Bipolar Differential Amplifiers: Common-
mode Gain and Input Resistance
Both arms of differential amplifier are symmetrical.
So terminal currents and collector voltages are equal.
Characteristics of differential pair with common-
mode input are similar to those of a C-E (or C-S)
amplifier with large emitter (or source) resistor.
Output voltages are:EE
Ror )1(2icv
bi
icv
)1(2bi
c2v
c1v
EE
R
o
rC
RoC
Ro
icv
icv
)1(2
)1(2bi)1(2ev
EERorEE
Ro
EERo
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Bipolar Differential Amplifiers: Common-
mode Gain and Input Resistance (contd.)
EEVC
V
EERC
R
EERor
CRo
ccA22)1(2
0id
vicvocv
Common-mode gain is given by:
For symmetrical power supplies, common-mode gain =0.5. Thus, common-
mode output voltage andAcc is 0 ifREEis infinite. This result is obtained since
output resistances of transistors are neglected. A more accurate expression is:
Therefore, common-mode conversion gain is found to be 0.0c2vc1vodv
EERoro
CRccA
2
11
EERo
rEERor
icR )1(
22
)1(2
bi2ic
v
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Common-Mode Rejection ratio (CMRR)
Represents ability of amplifier to amplify desired differential-mode inputsignal and reject undesired common-mode input signal.
For differential output, common-mode gain of balanced amplifier is zero,
CMRR is infinite. For single-ended output,
For infiniteREE, CMRR is limited by omf . If term containingREEis
dominant
Thus for differential pair biased by resistorREE , CMRR is limited by
available negative power supply.
Due to mismatches, , gives fractional
mismatch between small-signal device parameters in the two arms of
differential pair. HencegmREEproduct is maximized.
EERmgfocc
Add
A
cmAdm
A
2112
12/CMRR
m
EEV
EER
CI
EERmg 2040CMRR
gg
EERmgCMRR
21)21(2 gg gggg
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Analysis of Differential Amplifiers
Using Half-Circuits
Half-circuits are constructed by first drawing
the differential amplifier in a fully
symmetrical form- power supplies are split
into two equal halves in parallel, emitter
resistor is separated into two equal resistors in
parallel.
None of the currents or voltages in the circuit
are changed.
For differential mode signals, points on the
line of symmetry are virtual grounds
connected to ground for ac analysis
For common-mode signals, points on line of
symmetry are replaced by open circuits.
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Bipolar Differential-mode Half-circuits
Applying rules for drawing half-
circuits, the two power supply
lines and emitter become ac
grounds. The half-circuit
represents a C-E amplifier stage.
2id
v
c1v
CRmg
2
idv
c2v
CR
mg
idv
c2v
c1vov C
Rmg
Direct analysis of the half-circuits yield:
ridR 2
b1i/
idv
)(2 orCR
odR
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Bipolar Common-mode Half-circuits
All points on line of symmetry become open circuits.
DC circuit with VIC set to zero is used to find amplifiers Q-point.
Last circuit is used for for common-mode signal analysis and
represents the C-E amplifier with emitter resistor 2REE.
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Bipolar Common-mode Input Voltage
Range
For symmetrical power supplies, VEE
>> VBE
, andRC
=REE
,
EER2C
R
F
CCV
BEV
EEV
EER2C
R
F
CCV
ICV
EER
EEV
BEV
ICV
FCI
ICVCRCICCVCBV
1
1
2
0
3CC
V
ICV
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Biasing with Electronic Current Sources
Differential amplifiers are biased using electroniccurrent sources to stabilize the operating point and
increase effective value ofREEto improve CMRR
Electronic current source has a Q-point current ofISS
and an output resistance ofRSS as shown.
DC model of the electronic current source is a dccurrent source,ISSwhile ac model is a resistanceRSS.
SPICE model includes both ac
and dc models.
SSR
0V
SSI
DCI
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MOSFET Differential Amplifiers: DC
Analysis
Op amps with MOSFET inputs have a
high input resistance and much higher
slew rate that those with bipolar input
stages.Using half-circuit analysis method, we
see thatIS=ISS/2.
nKSS
I
TNV
nKD
2I
TNV
GSV
TNV
GSVn
KDI
2
2
DR
DI
DDV
D2V
D1V 0oV and
GSV
DR
DI
DDV
SV
DV
DSV
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Small-Signal Transfer Characteristic
MOS differential amplifier gives improved linear input signal range and
distortion characteristics over that of a single transistor.
Second-order distortion product is eliminated and distortion is greatly
reduced. However some distortion prevails as MOSFETs are nor perfect
square law devices and some distortion arises through voltage dependence
of output impedances of the transistors.
22
2 TNV
GS2v
TNV
GS1vn
K
D2I
D1I
2idv
GSV
GS2v
For symmetrical differential amplifier with purely differential-mode input
2idv
GSV
GS1v
idvmgid
vTNV
GSVnKD2
ID1I
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MOSFET Differential Amplifiers: DC
Analysis (Example)
Problem:Find Q-points of transistors in the differential amplifier. Given data:VDD=VSS=12 V,ISS=200 mA,RSS= 500 k,RD = 62 k,l
= 0.0133 V-1,Kn = 5 mA/ V2, VTN=1V
Analysis:A100m
2
SSI
DI
V8.6
TNV
DR
DI-
DDV
ICV
TNV
DR
DI-
DDV-
ICV
GDV
V20.125mA/V
A2001
mGS
V
V7V2.1)A)(62k100(-V12 mDSV
To maintain pinch-off operation ofM1 for nonzero VIC ,
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MOSFET Differential Amplifiers:
Differential-mode Input Signals
2id
v
d1v
DRmg
2id
v
d2v DRmg
idv
odv
DRmg
Source node in differential amplifier represents virtual groundDifferential-mode gain for balanced output is
Gain for single-ended output is
DRmgdd
A
0ic
vidvod
v
220
icvid
vd1
v
1dd
AD
Rmg
ddA
220
icvid
v
d2v
2
ddA
DRmg
ddA
id
RD
Rod
R 2
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MOSFET Differential Amplifiers:
Common-mode Input Signals
Electronic current source is modeled by twice its small-signal output resistance representing output resistance of the
current source.
Common-mode half-circuit is similar to inverting amplifier
with 2RSSas source resistor.
icv
21d2v
d1v
SSRmgDRmg
ic
vic
v21
2sv
SSRmgSSRmg
0d2
vd1
vod
v Thus, common-mode conversion gain= 0
SSRD
R
SSRmgD
Rm
g
ccA221
0id
vicvoc
v
Due to infinite current gain of
FET, ro can be neglected.
ic
R
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Common-Mode Rejection ratio (CMRR)
For purely common-mode input signal, output of balanced MOS amplifieris zero, CMRR is infinite. For single-ended output,
RSS(which is much >REEand thus provides more Q-point stability) should
be maximized.
To compare MOS amplifier directly to BJT amplifier, assume that MOS
amplifier is biased by
From given data in example, MOS amplifiers CMRR=54 or 35 dB (almost
10 dB worse than BJT amplifier).To increase CMRR in BJT and FET
amplifiers, current sources with higherRSSorREEare used.
SSRmg
SSR
DR
DRmg
ccAdd
A
cmAdm
A
)2/(
2/)(2/CMRR
SS
IGSV
SSV
SSR
TNV
GSV
GSV
SSV
TNV
GSV
SSR
SSI
TNV
GSV
SSR
DI
)(2CMRR
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Two-port model for Differential
Amplifiers
Two-port model simplifies circuit analysis of differential amplifiers.
Expressions for FET are obtained by substitutingRSSforREE.
EER
focR
or
odR
EERcmv
cmv
EERmgmg
cmi
dmvmgdm
i
m2
2
221
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Differential Amplifier Design (Example)
Problem:Find Q-points of transistors in the differential amplifier.
Given data:Adm=40 dB,Rid>250 k,single-ended CMRR> 80 dB, VIC
at least 5V, MOSFETs with: l= 0.0133 V-1,Kn
= 50 mA/ V2, VTN=1V,
BJTs with : F=100, VA =75V,IS=0.5 fA
Assumptions: Active-region operation, symmetrical power supplies, o =F, vidmaximum of 30 mV.
Analysis:
Adm=40 dB =100. To achieve this gain with resistively loaded amplifier, we
use BJT. ForAdm =gmRC=40ICRC , required gain can be obtained with
voltage drop of 2.5 V acrossRC.
For bipolar differential amplifier,Rid=2r, so, r=125 k.A20
rTVo
CI
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Differential Amplifier Design (Example
contd.)
ChooseIC= 15 mA to provide safety margin. SoRC=2.5 V/15 mA =167 k.
ChooseRC= 180 k as the nearest value with 5% toleranceand alos to
compensate for neglecting ro in the analysis.
VICof 5V requires collector voltage to be at least 5 V at all times. We also
know that vidcan be a maximum of 30 mV for linearity. So accomponent of differential output will not be greater than 100(0.03 V)=3V,
half of which appears at each collector. Thus dc signal acrossRCwont
exceed 4 V( 2.5 V dc + 1.5 V ac) and positive power supply must fulfill
Choose VCC=10 V to dive desired margin of 1 V, For symmetrical supplies,VEE= -10 V. Single-ended CMRR of 80 dB needs
Choose current source withIEE=30 mA andREE> 20 M
V94)V5(V4 ICV
CCV
M7.16)A15)(V/40(
410CMRR
mgEE
R
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Two-stage Prototype of an Op Amp
For higher gain,pnp C-E amplifier isconnected at output of the input stage
differential amplifier.
Virtual ground at emitter node allows input
stage to achieve full inverting amplifier
gain without needing emitter bypasscapacitor.
Pnp transistor permits direct coupling
between stages, allows emitter ofpnp to be
connected to ac ground and provides
required voltage level shift to bring outputback to zero.
Bypass and coupling capacitors are thus
eliminated.
Differential amplifier providesdesired differential input,CMRR
and ground referenced output as
the input stage of op amp.
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Two-stage Op Amp: DC Analysis
This circuit requires a resistance inseries with emitter ofQ3 to stabilize Q-
point (as collector current ofQ3 is
exponentially dependent on base-
emitter voltage), at the expense of
voltage gain loss.
From dc equivalent circuit,IE1=IE2 =I1 /2. Ifbase current ofQ3 is neglected and C-B
current gains are one,
As both inputs are zero, output also=0
IS3 is saturation current. For zero offset voltage
BEVC
R1
I
CCV
CE2V
CE1V
2
REEV
C3I / CC
VEC3V
S3IC3
I
TV
EB3V 1ln
S3
IC3I
F3
C3I
21
I
F
TV
CR 1ln
2
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Two-stage Op Amp: AC Analysis
(Differential Mode)
Half-circuit can be constructed from acequivalent circuit in spite of asymmetricity, as
voltage variations at collector ofQ2dont
substantially alter transistor current in
forward-active operation region.
From small-signal circuit model,
Rm
gvt
A
rCRm
g
LRm
g
vtA
3c2
vov
2
)3(22
122
idvc2
v
1
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Two-stage Op Amp: AC Analysis
(Differential Mode contd.)
This can be rewritten as
Base current ofQ3 is neglected so,IC2RC=VBE3=0.7 V,IC3R=VEE,
3
322)
3)(
3(
22
21c2
vov
idvc2v
idv
ov
r
CR
RoCRmgRm
grC
Rmgvt
Avt
Adm
A
322
340
340
3240
2
1
33
332
2
1
oCR
CI
CIC
I
RC
IoC
RC
I
oCRmg
Rm
gRoC
Rm
g
dmA
2
3
3
281
560
CIC
I
o
EEV
dmA
Upper limit onIC2 andI1 is set by maximum dc bias
current at input, lower limit onIC3 is set by minimum
current to drive total load impedance at output.
12
22
idi/
idv
rr
idR R
orR
outR
3
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Two-stage Op Amp: AC Analysis
(Common Mode)
From ac equivalent circuit, we
observe that circuitry beyond
collector ofQ2 is same as that in
differential mode half-circuit.
The difference in collector
currents causes difference in
output voltage.
1221
icv
2
12
221
icv
2
1)1
2(2
2
icv
2c2i
Rm
g
mg
R
o
mgm
g
Ro
r
o
From ac equivalent circuit for common-mode inputs,
For differential-mode inputs, collectorcurrent was
Thus,id
v2
2c2i m
g
12212
21CMRR
1221
2
3
3
1221
2
Rm
gR
mg
cmAdm
ARmg
dmA
rCR
Ro
Rmg
CR
mg
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Improving Op Amp Voltage Gain
Overall amplifier gain decreases rapidly as thequiescent current of second stage decreases.
Voltage gain can improve if resistor in second
stage is replaced by current source withR2 >>
ro3, ifR2 is neglected,
This expression can be reduced to
)33)(3(
2221 ormgrCRm
g
vtAvtAdmA
2
3
3
281
3560
CI
CI
o
AV
dmA
332 or
orR
outR
Output resistance is degraded, amplifier more represents
transconductance amplifier than a true low output
resistance voltage amplifier.
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Reducing Output Resistance
A C-C stage is added to the
prototype to maintain voltage
gain but reduce output
resistance.
From ac equivalent circuit,
1
)14(4
)14
(
3
)3
(32
)3
(2
21
LRor
LR
o
v
A
RCCinor
mg
vA
rC
Rmg
vA
LR
orR
CCin
)14
(4
22r
idR
3
41
4
31
4
1
14
3
4
1
14
4
4
1
CIC
I
o
f
mg
o
or
mgo
thR
mgout
R
m
3213
vov
2v
3v
idv
2v
vtA
vtA
vtA
dmA
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Three-Stage Bipolar Op Amp Analysis
Problem: Find differential-mode gain, CMRR, input and output resistances.
Given data:VCC=VEE=15 V, o1 = o2 = o3 = o4 =100, VA3 =75V,I1 = 100
mA,I2 = 500 mA,I3 = 5 mA,R1 = 750 k ,RL = 2 k,R2 andR3 are infinite.
Analysis:
k55.4
S2102.240
A55011
mS98.1)(4040
m3g
o3
3
r
C3I
m3g
F4
3I2
I
F4
E4I2
IB4I
2I
C3I
E2I
F2C2I
m2g
m
Voltage at node 3 is one base-emitter voltage
drop above zero. VEC3=15-0.7=14.3 V.
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Three-Stage Bipolar Op Amp Analysis
(contd.)
k9.15
5054
mA95.4
k162
F3
C3I
C2I
EB3V
CR
C4I
TV
o4r
E4I
F4C4I
C3I
EC3VA3V3o
r
1998.0
)14(4
)14
(
3
1980))14
(4
(332
50.3)3
(2
21
LRor
LR
o
v
A
LR
or
or
mg
vA
rC
Rmgv
A
6920321
vtA
vtA
vtA
dmA
k1012
2 r
idR k61.1
14
3
4
1
o
or
mgout
R
63.5dB149012CMRR RmgOverall gain is lower because of lower gain of first stage (since r3
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CMOS Op Amp Prototype: Circuit
Differential amplifier (M1 and
M2) followed by C-S stageM3
and source followerM4.
Current sources are used to
bias differential input and
source follower stages and as
load forM3.
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CMOS Op Amp Prototype: AC Analysis
LR
mg
LR
mg
DRmg
f
vtA
vtA
vtA
dmA
41
42
23
321
m
Since source follower has unity gain,
33
32
3
3
2
2
3
1
22
33
)1(21
TP
V
pK
DI
DI
pK
DI
nK
TNV
GSV
GSV
fvtA
vtA
dmA
l
m
Design freedom is higher than in bipolar case
due to Q-point dependence ofmf. Operating
currents should be reduced andM3 should
have small lto achieve higher gain.Inputbias current doesnt restrictID1 asIG =0.
id
R
4
1
mgout
R
12CMRR R
mg
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BiCMOS Amplifiers
Integrated circuit processes that offer
combination of bipolar and MOS transistors or
bipolar transistors and JFETs are called
BiCMOS and BiFET technologies respectively. Input PMOS transistors give high input
resistance, can be biased at relatively high input
currents, which can improve slew rate.
Second gain stage uses BJT
with superior amplification
factor than FET.
REincreases voltage across
RD2 and hence the voltage
gain of first stage withoutreducing amplification factor
ofQ1.
Follower stage uses another
FET to maximize second-
stage gain while maintainingreasonable output resistance.
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Op Amp Output Stages
Output stage is designed to provide low output resistance and
relatively high current drive capability.
Followers: Class-A amplifiers- transistors conduct during full 3600 of
signal waveform, conduction angle =3600.
Push-pull: Class-B- each of the two transistors conducts during 1800ofsignal wavefrom, conduction angle =1800.
Class-AB: Characteristics of Class-A and Class-B are combined, most
commonly used as output stage in op amps.
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Source-Follower: Class-A Output Stage
For a source-follower,difference between input and outputvoltages is fixed and voltage transfer characteristic is as
shown. If load resistor is connected to output, total source
current:
vMIN = -ISSRL and iS=0,M1cuts off when vI= -ISSRL + VTN.
0
LRov
SSI
Si
tDDVov sin
If output signal is given by:
Efficiency of amplifier is given by:
%252
2
2
DDV
SSI
LR
DDV
avPacP
Low efficiency is due to currentISSthat constantly
flows between the two supplies.
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Class-B Push-Pull Output Stage
Improve efficiency by operating transistors atzero Q-point current eliminating quiescent
power dissipation. NMOS transistor is a
source-follower for positive input signals and
NMOS transistor is a source-follower for
negative input signals.
Since neither transistor conducts when,
output waveform suffers from a dead-zone or
crossover distortion.
%5.782
2
2
2
L
RDDV
LRDDV
avPacP
TNV
GSv
TPV
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Class-AB Amplifiers
Benefits of Class-B amplifier can be
maintained without dead zone by
biasing transistors into conduction
but at a low quiescent current level(
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Class-AB Output Stages for Op Amps
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Short-Circuit Protection
High current, high power dissipation or direct destructionof base-emitter junction can destroy the BJT if output of a
follower circuit is accidentally shorted to ground. Q2 is
added to protect the emitter follower.
Normally, voltage acrossR is
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Transformer Coupling: Follower
Transformer coupling is used in
amplifiers to achieve high voltage gain
and efficiency while delivering power
to low impedance loads.
Coupling capacitor blocks dc paththrough primary of transformer.
2v
1v n
1i
2i n
LZnZ 2
1
Transformer provides impedance
transformation by n2 . From ac
equivalent circuit,transistor must
drive
Transformer restricts operation to
frequencies >dc.
LRn
EQR 2
n1v
ov
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Transformer Coupling: Inverting
Amplifier and Class-B Output Stage
At dc, transformer is a short circuit,
quiescent operating current is suppliedthrough transformer primary. At signal
frequency load n2RL is presented to
transistor.
Inductance permits signal voltage to swing
symmetrically above and below VDD.
As both quiescent
operating currents
= 0, emitters can bedirectly connected
to transformer
primary.
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Electronic Current Sources: Introduction
Current through ideal current
source is independent of voltageacross its terminals and the output
resistance is infinite.
In electronic current sources,
current depends on voltage across
the terminals and they have afinite output resistance.
Currentsource
Currentsink
Single-transistor current sources operate in only one quadrant ofi-v space but
realize very high output resistances.
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Current Sources: Figure of Merit
is used as a figure of merit for comparing different current sources.
For a given Q-point current, VCSrepresents the equivalent voltage that
will be needed across a resistor to achieve same output resistance as
given current source.
For resistor:
For BJT:
For MOSFET:
outRoICSV
lll 111
DSV
DI
DSV
DIorD
Iout
RoICSV
AV
CEV
AV
CI
CEV
AV
CIorC
Iout
RoICSV
EEVR
REEV
outRoICS
V
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Higher Output Resistance Sources
Output resistance of the current sourcecan be increased by placing a resistor
in series with the emitter or source of
the transistor.
For BJT:
AVoCE
VAVoCS
VAVoCE
VAVoCS
V
ERrRR
ERooroutR
)()(
21
1
For MOSFET:
3
)1(
SSV
fCSV
SR
fSRmgorout
R
m
m
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Multiple Output Current Sources
k39.3
21
21
V18.3
21
1
RR
RR
BBR
SSV
RR
R
BBV
k47.01
k7.41
k221
11
15)7.0(
321F
BV
BI
BI
BI
7.0 BVBEVBVEVAssume equal current gains for all BJTs.
A48422
A103k22
1511
V7.127.012
V12)3390)(321
(18.315
BI
FCI
EVFB
IFC
I
EV
BI
BI
BI
BV
mA84.433
BI
FCI
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Multiple Output Current Sources (contd.)
Output resistances of the three current sources are given by:
k1773
M48.52
M8.311
211
10017.72
211
1
outRoutR
outR
ER
rRRC
I
ER
rRRooroutR
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Bipolar Transistor Current Source
Design Example
Problem: Design a current source with the largest possible outputvoltage range that meets the given output resistance specification.
Given data:VEE= 15 V,Io = 200 mA,IEE< 250 mA,Rout> 2 M, BJTs
available with (o, VA) = (80, 100 V) and (150, 75 V), VB must be as low
as possible.
Assumptions: Active region and small-signal operating conditions. VBE= 0.7 V, VT= 0.025 V, choose Vo = 0 V as representative output value.
Analysis:
V2000)M10)(A200(
21
1
outRoIA
Vo
AVoout
RoICSV
oro
E
RrRR
ERo
oroutR
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Bipolar Transistor Current Source
Design Example (contd.)
Both BJTs can satisfy these conditions. But, we choose BJT (150, 75V)with higheroVA product.
Total current < 250 mA. As output current is 200
mA, maximum of 50 mA can be used by base bias
network. Current used by base bias network must
be 5 to 10 times base current of BJT (1.33 mA forBJT with a current gain of 150). So bias network
current =20 mA.
LargeRBB reduces output resistance and output
compliance range (increase VBB).Trading
increased operating current for wider compliancerange, choose bias network current of 40 mA.
k375A40
V1521 m
RR
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Bipolar Transistor Current Source
Design Example (contd.)
Following set of equations can be used in a spreadsheet analysis todetermine design variables. Primary design variable is VBB which can
be used to determine other variables.
F
oI
BI
15
k37515
)21
(1
BBVBBVRRR 1k3751)21(2 RRRRR
21RR
BBR
oIBB
RBI
BEV
BBV
FER
)(BB
RBI
BEV
BBV
EEV
CEV
oITVo
r
oICE
VAV
or
ERrRR
ERo
oroutR
21
1
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Bipolar Transistor Current Source
Design Example (contd.)
From spreadsheet, smallest VBB for which output resistance > 10M with
some safety margin is 4.5 V, resulting output resistance is 10.7M.
Analysis of circuit with 1% resistor values givesIo = 200 mA and supply
current = 244 mA.
Final current source design is as shown.
MOSFET current source design can also be analyzed in similar manner.