Download - CIRCUIT DESIGN PROCESS
![Page 1: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/1.jpg)
CIRCUIT DESIGN PROCESS
MOS Layers, Stick Diagram, Design rules and layout
9/4/2015 CMOS VLSI DESIGN 1
![Page 2: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/2.jpg)
Circuit Design Process
• MOS layers
• Stick diagrams
• Design rules and layout
• Lambda-based design and other rules
• Examples, layout diagrams symbolic diagrams
9/4/2015 CMOS VLSI DESIGN 2
![Page 3: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/3.jpg)
04-09-2015 3
Measure Twice and Fabricate Once
![Page 4: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/4.jpg)
04-09-2015 4
Logic to Layouts
• Frontend:
Simulation
Verification
• Backend:
Turning codes or schematics into Masks-Gates to Layouts.
![Page 5: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/5.jpg)
MOS Layers
• MOS circuits are formed on four basic layers:
1. N-diffusion
2. P-diffusion
3. Polysilicon
4. Metal
• They are isolated by a thick or thin SiO2 insulating layer
• When polysilicon crosses diffusion transistors are formed
• Some process use second metal layer and second polysilicon
• Different layers are joined together at contact
9/4/2015 CMOS VLSI DESIGN 5
![Page 6: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/6.jpg)
STICK DIAGRAM & Layout
• Stick diagram: Conveys layer information through the color code.
• Layout: Symbolic representation of stick diagram which reflect the topology of the actual output.
N+ N+
9/4/2015 CMOS VLSI DESIGN 6
![Page 7: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/7.jpg)
Color Coding
9/4/2015 CMOS VLSI DESIGN 7
![Page 8: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/8.jpg)
Color Coding
9/4/2015 CMOS VLSI DESIGN 8
![Page 9: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/9.jpg)
STICK DIAGRAM – Notations
9/4/2015 CMOS VLSI DESIGN 9
Metal 1
poly
ndiff
pdiff
Can also draw
in shades of
gray/line style.
Similarly for contacts, via, tub etc..
![Page 10: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/10.jpg)
STICK DIAGRAM– Rules
Rule 1.
When two or more ‘sticks’ of the same type cross or touch each other that represents electrical contact.
9/4/2015 CMOS VLSI DESIGN 10
![Page 11: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/11.jpg)
STICK DIAGRAM– Rules
Rule 2.
When two or more ‘sticks’ of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connection explicitly).
9/4/2015 CMOS VLSI DESIGN 11
![Page 12: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/12.jpg)
STICK DIAGRAM– Rules
Rule 3
When a poly crosses diffusion it represents a transistor.
9/4/2015 CMOS VLSI DESIGN 12
Note: If a contact is shown then it is not a transistor.
![Page 13: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/13.jpg)
STICK DIAGRAM– Rules
Rule 4 In CMOS a demarcation line is drawn to avoid touching of p-diff
with n-diff.
• CMOS Technology (Demarcation Line p-Well Boundary)
– Transistor above demarcation line PMOS
– Transistor below demarcation line NMOS
9/4/2015 CMOS VLSI DESIGN 13
![Page 14: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/14.jpg)
Rules to be followed
9/4/2015 CMOS VLSI DESIGN 14
![Page 15: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/15.jpg)
STICK DIAGRAM(nMOS Process)
9/4/2015 CMOS VLSI DESIGN 15
![Page 16: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/16.jpg)
STICK DIAGRAM(CMOS P-Well Process)
9/4/2015 CMOS VLSI DESIGN 16
![Page 17: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/17.jpg)
STICK DIAGRAM
9/4/2015 CMOS VLSI DESIGN
Gnd
VDD
x x
X
X
X
X
VDD
x x
Gnd
17
![Page 18: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/18.jpg)
STICK DIAGRAM
9/4/2015 CMOS VLSI DESIGN 18
![Page 19: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/19.jpg)
STICK DIAGRAM –Representation
9/4/2015 CMOS VLSI DESIGN 19
1. Two Transistors in series
![Page 20: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/20.jpg)
STICK DIAGRAM –Representation
2. Two Transistors in parallel
9/4/2015 CMOS VLSI DESIGN 20
![Page 21: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/21.jpg)
N-MOS Design Style Single metal, single polysilicon nMOS technology
Layout of nMOS involves:
N-diffusion and other thin oxide regions (Green)
Polysilicon 1 (red)
Metal-1 (Blue)
Implant (Yellow)
Contacts (black or brown)
1. First step is to draw metal vdd & Gnd rails.
2.Thin oxide (n-diffusion) paths are drawn between rails and appropriate Contacts are made.
9/4/2015 CMOS VLSI DESIGN 21
![Page 22: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/22.jpg)
STICK DIAGRAM
9/4/2015 CMOS VLSI DESIGN 22
![Page 23: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/23.jpg)
Stick diagram
9/4/2015 CMOS VLSI DESIGN 23
A B N1 N2 P Vout
0 0 OFF OFF ON 1
0 1 OFF ON ON 0
1 0 ON OFF ON 0
1 1 ON ON ON 0
A B N1 N2 P Vout
0 0 OFF OFF ON 1
0 1 OFF ON ON 1
1 0 ON OFF ON 1
1 1 ON ON ON 0
2 INPUT NOR GATE
2 INPUT NAND GATE
![Page 24: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/24.jpg)
Stick Diagram
Write the nMOS stick diagram for the following
1. f=(xy+x)’
2. 3 input AND gate
3. 3 input OR gate
4. f=AB+C
9/4/2015 CMOS VLSI DESIGN 24
![Page 25: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/25.jpg)
CMOS design style • CMOS design style are based on the contribution
made by MEAD and CONWAY
• It do not use any depletion mode Transistor
• NMOS TransistorDriver
• PMOS TransistorLoad • CMOS Technology (Demarcation Line p-Well Boundary)
– Transistor above demarcation line PMOS
– Transistor below demarcation line NMOS
• Diffusion paths must not cross the demarcation line
• P-diffusion and n-diffusion must not join directly
• N and p diffusion are normally joined by metal where connection is needed
9/4/2015 CMOS VLSI DESIGN 25
![Page 26: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/26.jpg)
2-Input NAND Gate
9/4/2015 CMOS VLSI DESIGN 26
A B N1 N2 P1 P2 Vout
0 0 OFF OFF ON ON 1
0 1 OFF ON ON OFF 1
1 0 ON OFF OFF ON 1
1 1 ON ON OFF OFF 0
![Page 27: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/27.jpg)
2 input NOR Gate
9/4/2015 CMOS VLSI DESIGN 27
A B N1 N2 P1 P2 Vout
0 0 OFF OFF ON ON 1
0 1 OFF ON ON OFF 0
1 0 ON OFF OFF ON 0
1 1 ON ON OFF OFF 0
![Page 28: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/28.jpg)
2 input NOR Gate-STICK DIAGRAM
9/4/2015 CMOS VLSI DESIGN 28
![Page 29: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/29.jpg)
STICK DIAGRAM
• Write the stick diagram for the schematic given:
9/4/2015 CMOS VLSI DESIGN 29
![Page 30: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/30.jpg)
STICK DIAGRAM
9/4/2015 CMOS VLSI DESIGN 30
Power
Ground
B
C
Out A
![Page 31: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/31.jpg)
2 Input XOR Gate
9/4/2015 CMOS VLSI DESIGN 31
![Page 32: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/32.jpg)
2 Input XNOR Gate
9/4/2015 CMOS VLSI DESIGN 32
![Page 33: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/33.jpg)
2:1 MULTIPLXER
9/4/2015 CMOS VLSI DESIGN 33
• Write the schematic and stick diagram for 2:1 MUX F=Po.S’ + P1.S
where, A & B Inputs S = Select input
![Page 34: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/34.jpg)
Euler Path
• Euler graph is used to write the stick diagram for the complex gates
9/4/2015 CMOS VLSI DESIGN 34
![Page 35: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/35.jpg)
Euler Path
9/4/2015 CMOS VLSI DESIGN 35
![Page 36: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/36.jpg)
Euler Path
9/4/2015 CMOS VLSI DESIGN 36
![Page 37: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/37.jpg)
Euler Path
9/4/2015 CMOS VLSI DESIGN 37
![Page 38: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/38.jpg)
Euler Path
9/4/2015 CMOS VLSI DESIGN 38
![Page 39: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/39.jpg)
Euler path
9/4/2015 CMOS VLSI DESIGN 39
![Page 40: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/40.jpg)
Euler path
9/4/2015 CMOS VLSI DESIGN 40
![Page 41: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/41.jpg)
Euler path
9/4/2015 CMOS VLSI DESIGN 41
![Page 42: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/42.jpg)
Euler path
9/4/2015 CMOS VLSI DESIGN 42
![Page 43: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/43.jpg)
Euler Path
9/4/2015 CMOS VLSI DESIGN 43
![Page 44: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/44.jpg)
Example-2
9/4/2015 CMOS VLSI DESIGN 44
![Page 45: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/45.jpg)
Euler Path
9/4/2015 CMOS VLSI DESIGN 45
![Page 46: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/46.jpg)
Stick diagram
9/4/2015 CMOS VLSI DESIGN 46
![Page 47: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/47.jpg)
Layout Technique using Euler Graph Method
• Euler Graph Technique can be used to determine if any complex CMOS gate can be physically laid out in an optimum fashion
– Start with either NMOS or PMOS tree (NMOS for this example) and connect lines for transistor segments, labeling devices, with vertex points as circuit nodes.
– Next place a new vertex within each confined area on the pull-down graph and connect neighboring vertices with new lines, making sure to cross each edge of the pull-down tree only once.
– The new graph represents the pull-up tree and is the dual of the pull-down tree.
• The stick diagram at the left (done with arbitrary gate ordering) gives a very non-optimum layout for the CMOS gate above.
![Page 48: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/48.jpg)
Layout with Optimum Gate Ordering • By using the Euler path approach to re-order the
polysilicon lines of the previous chart, we can obtain an optimum layout.
• Find a Euler path in both the pull-down tree graph and the pull-up tree graph with identical ordering of the inputs.
– Euler path: traverses each branch of the graph exactly once!
• By reordering the input gates as E-D-A-B-C, we can obtain an optimum layout of the given CMOS gate with single actives for both NMOS and PMOS devices (below).
![Page 49: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/49.jpg)
CMOS 1-Bit Full Adder Circuit • 1-Bit Full Adder logic function:
Sum = A XOR B XOR C
= ABC + AB’C’ + A’BC’ + A’B’C
Carry_out = AB + AC + BC
– Exercise: Show that the sum function can be written as shown at left
Sum = ABC + (A + B + C) · carry_out’
• This alternate representation of the sum function allows the 1-bit full adder to be implemented in complex CMOS with 28 transistors, as shown at left below.
– Carry_out’ internal node is used as an input to the adder complex CMOS gate
– Exercise: Show that the two P-trees in the complex CMOS gates of the carry_out and sum are optimizations of the proper dual derivations from the two N-tree networks.
![Page 50: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/50.jpg)
CMOS Full Adder Layout (Complex Logic)
• Mask layout of 1-bit full adder circuit is shown below
– A layout designed with Euler method shows that the carry_out inverter requires separate active shapes, but all other N (and P) transistors were laid out in a single active region
– Layout below is non-optimized for performance
• All transistors are seen to be minimum W/L
• Design of n-bit full adder:
– A carry ripple adder design uses the carry_out of stage k as the carry_in for stage k+1
– Typically the layout is modified from that shown below in order to use larger transistors for the carry_out CMOS gate in order to improve the performance of the ripple bit adder
• See Fig. 7.30 in Kang and Leblebici
![Page 51: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/51.jpg)
1 bit shift register • Schematic of 1 bit shift register
• S & S’ of first TG is fed with clk-1
• S & S’ of second TG is fed with clk-2
• Clk-1 is in not phase with clk-2
9/4/2015 CMOS VLSI DESIGN 51
![Page 52: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/52.jpg)
1 bit shift register
9/4/2015 CMOS VLSI DESIGN 52
![Page 53: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/53.jpg)
1 bit shift register
9/4/2015 CMOS VLSI DESIGN 53
![Page 54: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/54.jpg)
1 bit shift register
9/4/2015 CMOS VLSI DESIGN 54
![Page 55: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/55.jpg)
1 bit shift register
9/4/2015 CMOS VLSI DESIGN 55
![Page 56: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/56.jpg)
1 bit shift register
9/4/2015 CMOS VLSI DESIGN 56
![Page 57: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/57.jpg)
1 bit shift register
9/4/2015 CMOS VLSI DESIGN 57
![Page 58: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/58.jpg)
Why we need design rules
9/4/2015 CMOS VLSI DESIGN 58
![Page 59: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/59.jpg)
Lamda Based Design Rules • Design Rules:
• Allow translation of circuit diagram (Stick diagram or symbolic diagram) into the actual geometry in silicon.
• Effective interface between circuit/system designer & process engineer.
• To obtain a circuit with optimum yield (functional circuits versus non functional circuits) without comprising reliability & area.
• To provide best comprise between performance & yield. • It mainly focuses on geometrical reproduction of features
& interaction between layers. • Approaches: Micron design rule & Lamda based design
rules.
9/4/2015 CMOS VLSI DESIGN 59
![Page 60: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/60.jpg)
Lamda Based Design Rules
• Lamda Based Design Rules (Proposed –Mead & Conway) – based on single parameter λ
– Linear feature.
– Permits first order scaling.
– Revolution of the complete wafer implementation process.
– All parts in all layers are dimensioned in λ units.
– 1.0 um Technology min features size 2λ Therefore, λ= 0.5 um.
9/4/2015 CMOS VLSI DESIGN 60
![Page 61: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/61.jpg)
STICK DIAGRAM(nMOS Process)
9/4/2015 CMOS VLSI DESIGN 61
![Page 62: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/62.jpg)
STICK DIAGRAM(CMOS P-Well Process)
9/4/2015 CMOS VLSI DESIGN 62
![Page 63: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/63.jpg)
Design Rules for wires(nMOS &pMOS)
9/4/2015 CMOS VLSI DESIGN 63
![Page 64: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/64.jpg)
Design Rules for wires
9/4/2015 CMOS VLSI DESIGN 64
![Page 65: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/65.jpg)
9/4/2015 CMOS VLSI DESIGN 65
![Page 66: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/66.jpg)
A N-well rules
• A1 =10
• A2= 6 wells at same potential
• A2=8 wells at different potentials
9/4/2015 CMOS VLSI DESIGN 66
![Page 67: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/67.jpg)
B Active Area Rules
• Active Area Rules(n-diffusion, p-diffusion)
• B1= 3
• B2=3
• B3=5
• B4=3
• B5=5
• B6=3
9/4/2015 CMOS VLSI DESIGN 67
![Page 68: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/68.jpg)
Transistor Design Rules nMOS, pMOS & CMOS
9/4/2015 CMOS VLSI DESIGN 68
![Page 69: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/69.jpg)
Transistor Design Rules nMOS, pMOS & CMOS
9/4/2015 CMOS VLSI DESIGN 69
![Page 70: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/70.jpg)
Contact cuts
• When making contacts between polysilicon and diffusion in nmos circuits there are 3 possible approaches
• Poly to metal then metal to diffusion
• Buried contact poly to diffusion
• Butting Contact(poly to diff using metal)
9/4/2015 CMOS VLSI DESIGN 70
![Page 71: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/71.jpg)
Contact cuts
9/4/2015 CMOS VLSI DESIGN 71
![Page 72: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/72.jpg)
Contacts polysilicon to diffusion
9/4/2015 CMOS VLSI DESIGN 72
![Page 73: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/73.jpg)
Cross section through some contact structures
9/4/2015 CMOS VLSI DESIGN 73
![Page 74: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/74.jpg)
2 input NAND gate
9/4/2015 CMOS VLSI DESIGN 74
![Page 75: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/75.jpg)
2 input NOR gate
9/4/2015 CMOS VLSI DESIGN 75
![Page 76: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/76.jpg)
Other design rules
• Double Metal MOS process Rules
• CMOS fabrication is much more complex than nMOS fabrication
• 2 um Double metal, Double poly. CMOS/BiCMOS Rules
• 1.2um Double Metal single poly.CMOs rules
9/4/2015 CMOS VLSI DESIGN 76
![Page 77: CIRCUIT DESIGN PROCESS](https://reader034.vdocument.in/reader034/viewer/2022050809/563db919550346aa9a9a05a1/html5/thumbnails/77.jpg)
XOR Implementations using CMOS Transmission Gates
• The top circuit implements an XOR function with two CMOS transmission gates and two inverters
– 8 transistors total (4 fewer than a complex CMOS implementation)
• The XOR can also be implemented with only 6 transistors with one transmission gate, one standard inverter, and one special inverter gate powered from B to B’ (instead of Vdd and Vss) and inserted between A and the output F.