circuit design process
DESCRIPTION
CIRCUIT DESIGN PROCESS MOS Layers, Stick Diagram, Design rules and layoutTRANSCRIPT
CIRCUIT DESIGN PROCESS
MOS Layers, Stick Diagram, Design rules and layout
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Circuit Design Process
• MOS layers
• Stick diagrams
• Design rules and layout
• Lambda-based design and other rules
• Examples, layout diagrams symbolic diagrams
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Measure Twice and Fabricate Once
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Logic to Layouts
• Frontend:
Simulation
Verification
• Backend:
Turning codes or schematics into Masks-Gates to Layouts.
MOS Layers
• MOS circuits are formed on four basic layers:
1. N-diffusion
2. P-diffusion
3. Polysilicon
4. Metal
• They are isolated by a thick or thin SiO2 insulating layer
• When polysilicon crosses diffusion transistors are formed
• Some process use second metal layer and second polysilicon
• Different layers are joined together at contact
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STICK DIAGRAM & Layout
• Stick diagram: Conveys layer information through the color code.
• Layout: Symbolic representation of stick diagram which reflect the topology of the actual output.
N+ N+
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Color Coding
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Color Coding
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STICK DIAGRAM – Notations
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Metal 1
poly
ndiff
pdiff
Can also draw
in shades of
gray/line style.
Similarly for contacts, via, tub etc..
STICK DIAGRAM– Rules
Rule 1.
When two or more ‘sticks’ of the same type cross or touch each other that represents electrical contact.
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STICK DIAGRAM– Rules
Rule 2.
When two or more ‘sticks’ of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connection explicitly).
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STICK DIAGRAM– Rules
Rule 3
When a poly crosses diffusion it represents a transistor.
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Note: If a contact is shown then it is not a transistor.
STICK DIAGRAM– Rules
Rule 4 In CMOS a demarcation line is drawn to avoid touching of p-diff
with n-diff.
• CMOS Technology (Demarcation Line p-Well Boundary)
– Transistor above demarcation line PMOS
– Transistor below demarcation line NMOS
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Rules to be followed
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STICK DIAGRAM(nMOS Process)
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STICK DIAGRAM(CMOS P-Well Process)
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STICK DIAGRAM
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Gnd
VDD
x x
X
X
X
X
VDD
x x
Gnd
17
STICK DIAGRAM
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STICK DIAGRAM –Representation
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1. Two Transistors in series
STICK DIAGRAM –Representation
2. Two Transistors in parallel
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N-MOS Design Style Single metal, single polysilicon nMOS technology
Layout of nMOS involves:
N-diffusion and other thin oxide regions (Green)
Polysilicon 1 (red)
Metal-1 (Blue)
Implant (Yellow)
Contacts (black or brown)
1. First step is to draw metal vdd & Gnd rails.
2.Thin oxide (n-diffusion) paths are drawn between rails and appropriate Contacts are made.
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STICK DIAGRAM
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Stick diagram
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A B N1 N2 P Vout
0 0 OFF OFF ON 1
0 1 OFF ON ON 0
1 0 ON OFF ON 0
1 1 ON ON ON 0
A B N1 N2 P Vout
0 0 OFF OFF ON 1
0 1 OFF ON ON 1
1 0 ON OFF ON 1
1 1 ON ON ON 0
2 INPUT NOR GATE
2 INPUT NAND GATE
Stick Diagram
Write the nMOS stick diagram for the following
1. f=(xy+x)’
2. 3 input AND gate
3. 3 input OR gate
4. f=AB+C
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CMOS design style • CMOS design style are based on the contribution
made by MEAD and CONWAY
• It do not use any depletion mode Transistor
• NMOS TransistorDriver
• PMOS TransistorLoad • CMOS Technology (Demarcation Line p-Well Boundary)
– Transistor above demarcation line PMOS
– Transistor below demarcation line NMOS
• Diffusion paths must not cross the demarcation line
• P-diffusion and n-diffusion must not join directly
• N and p diffusion are normally joined by metal where connection is needed
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2-Input NAND Gate
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A B N1 N2 P1 P2 Vout
0 0 OFF OFF ON ON 1
0 1 OFF ON ON OFF 1
1 0 ON OFF OFF ON 1
1 1 ON ON OFF OFF 0
2 input NOR Gate
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A B N1 N2 P1 P2 Vout
0 0 OFF OFF ON ON 1
0 1 OFF ON ON OFF 0
1 0 ON OFF OFF ON 0
1 1 ON ON OFF OFF 0
2 input NOR Gate-STICK DIAGRAM
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STICK DIAGRAM
• Write the stick diagram for the schematic given:
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STICK DIAGRAM
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Power
Ground
B
C
Out A
2 Input XOR Gate
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2 Input XNOR Gate
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2:1 MULTIPLXER
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• Write the schematic and stick diagram for 2:1 MUX F=Po.S’ + P1.S
where, A & B Inputs S = Select input
Euler Path
• Euler graph is used to write the stick diagram for the complex gates
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Euler Path
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Euler Path
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Euler Path
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Euler Path
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Euler path
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Euler path
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Euler path
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Euler path
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Euler Path
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Example-2
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Euler Path
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Stick diagram
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Layout Technique using Euler Graph Method
• Euler Graph Technique can be used to determine if any complex CMOS gate can be physically laid out in an optimum fashion
– Start with either NMOS or PMOS tree (NMOS for this example) and connect lines for transistor segments, labeling devices, with vertex points as circuit nodes.
– Next place a new vertex within each confined area on the pull-down graph and connect neighboring vertices with new lines, making sure to cross each edge of the pull-down tree only once.
– The new graph represents the pull-up tree and is the dual of the pull-down tree.
• The stick diagram at the left (done with arbitrary gate ordering) gives a very non-optimum layout for the CMOS gate above.
Layout with Optimum Gate Ordering • By using the Euler path approach to re-order the
polysilicon lines of the previous chart, we can obtain an optimum layout.
• Find a Euler path in both the pull-down tree graph and the pull-up tree graph with identical ordering of the inputs.
– Euler path: traverses each branch of the graph exactly once!
• By reordering the input gates as E-D-A-B-C, we can obtain an optimum layout of the given CMOS gate with single actives for both NMOS and PMOS devices (below).
CMOS 1-Bit Full Adder Circuit • 1-Bit Full Adder logic function:
Sum = A XOR B XOR C
= ABC + AB’C’ + A’BC’ + A’B’C
Carry_out = AB + AC + BC
– Exercise: Show that the sum function can be written as shown at left
Sum = ABC + (A + B + C) · carry_out’
• This alternate representation of the sum function allows the 1-bit full adder to be implemented in complex CMOS with 28 transistors, as shown at left below.
– Carry_out’ internal node is used as an input to the adder complex CMOS gate
– Exercise: Show that the two P-trees in the complex CMOS gates of the carry_out and sum are optimizations of the proper dual derivations from the two N-tree networks.
CMOS Full Adder Layout (Complex Logic)
• Mask layout of 1-bit full adder circuit is shown below
– A layout designed with Euler method shows that the carry_out inverter requires separate active shapes, but all other N (and P) transistors were laid out in a single active region
– Layout below is non-optimized for performance
• All transistors are seen to be minimum W/L
• Design of n-bit full adder:
– A carry ripple adder design uses the carry_out of stage k as the carry_in for stage k+1
– Typically the layout is modified from that shown below in order to use larger transistors for the carry_out CMOS gate in order to improve the performance of the ripple bit adder
• See Fig. 7.30 in Kang and Leblebici
1 bit shift register • Schematic of 1 bit shift register
• S & S’ of first TG is fed with clk-1
• S & S’ of second TG is fed with clk-2
• Clk-1 is in not phase with clk-2
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1 bit shift register
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1 bit shift register
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1 bit shift register
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1 bit shift register
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1 bit shift register
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1 bit shift register
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Why we need design rules
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Lamda Based Design Rules • Design Rules:
• Allow translation of circuit diagram (Stick diagram or symbolic diagram) into the actual geometry in silicon.
• Effective interface between circuit/system designer & process engineer.
• To obtain a circuit with optimum yield (functional circuits versus non functional circuits) without comprising reliability & area.
• To provide best comprise between performance & yield. • It mainly focuses on geometrical reproduction of features
& interaction between layers. • Approaches: Micron design rule & Lamda based design
rules.
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Lamda Based Design Rules
• Lamda Based Design Rules (Proposed –Mead & Conway) – based on single parameter λ
– Linear feature.
– Permits first order scaling.
– Revolution of the complete wafer implementation process.
– All parts in all layers are dimensioned in λ units.
– 1.0 um Technology min features size 2λ Therefore, λ= 0.5 um.
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STICK DIAGRAM(nMOS Process)
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STICK DIAGRAM(CMOS P-Well Process)
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Design Rules for wires(nMOS &pMOS)
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Design Rules for wires
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A N-well rules
• A1 =10
• A2= 6 wells at same potential
• A2=8 wells at different potentials
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B Active Area Rules
• Active Area Rules(n-diffusion, p-diffusion)
• B1= 3
• B2=3
• B3=5
• B4=3
• B5=5
• B6=3
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Transistor Design Rules nMOS, pMOS & CMOS
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Transistor Design Rules nMOS, pMOS & CMOS
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Contact cuts
• When making contacts between polysilicon and diffusion in nmos circuits there are 3 possible approaches
• Poly to metal then metal to diffusion
• Buried contact poly to diffusion
• Butting Contact(poly to diff using metal)
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Contact cuts
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Contacts polysilicon to diffusion
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Cross section through some contact structures
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2 input NAND gate
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2 input NOR gate
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Other design rules
• Double Metal MOS process Rules
• CMOS fabrication is much more complex than nMOS fabrication
• 2 um Double metal, Double poly. CMOS/BiCMOS Rules
• 1.2um Double Metal single poly.CMOs rules
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XOR Implementations using CMOS Transmission Gates
• The top circuit implements an XOR function with two CMOS transmission gates and two inverters
– 8 transistors total (4 fewer than a complex CMOS implementation)
• The XOR can also be implemented with only 6 transistors with one transmission gate, one standard inverter, and one special inverter gate powered from B to B’ (instead of Vdd and Vss) and inserted between A and the output F.