EEL7312 – INE5442
Digital Integrated Circuits
1
Digital Integrated Circuits
Chapter 6 – The CMOS Inverter
EEL7312 – INE5442
Digital Integrated Circuits
2
Contents
� Introduction - MOST simulation models
� The CMOS inverter : The static behavior:
o DC transfer characteristics,
o Short-circuit current
� The CMOS inverter : The dynamic behavior
� Energy, power, and energy delay
EEL7312 – INE5442
Digital Integrated Circuits
3
Introduction - 1
Zero-order model (ideal switch)
of n- and p-channel MOSFETs
Inverter
Source: Weste & Harris
What for a signal between “0” and “1”?
EEL7312 – INE5442
Digital Integrated Circuits
4
Introduction - 2
VGS ≥ VT
Ron
S D
Non ideal switch
|VGS|
An MOS Transistor
First-order model of a MOSFET
Source: Rabaey
What’s the value of Ron? Abrupt transition from on to off?
EEL7312 – INE5442
Digital Integrated Circuits
5
Introduction - 3
The MOS Transistor
Polysilicon Aluminum
Source: Rabaey
EEL7312 – INE5442
Digital Integrated Circuits
6
Introduction - 4
MOS Transistors – n- and p-channel
S
D
G
G
S
D
NMOS Enhancement
PMOS Enhancement
D
S
G B
G B
In general connected to GND
In general connected to VDD
EEL7312 – INE5442
Digital Integrated Circuits
7
Introduction - 5
I-V Relations
Long-channel n-MOST
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10-4
VDS
(V)
I D(A
)
VGS= 2.5 V
VGS= 2.0 V
VGS= 1.5 V
VGS= 1.0 V
Resistive Saturation
VDS = VGS - VT
VGS< 0.5 V
S
D
G
ID
Source: Rabaey
EEL7312 – INE5442
Digital Integrated Circuits
8
Introduction - 6
I-V Relations
Long-channel p-MOST
0 0.5 1 1.5 2 2.50
1
2
3
4
5
6x 10-4
-VDS
(V)
I D(A
)
VGS=- 2.5 V
VGS= -2.0 V
VGS= -1.5 V
VGS= -1.0 V
Resistive Saturation
VDS = VGS - VT
VGS>- 0.5 V
ID
S
D
G
Source: Rabaey
EEL7312 – INE5442
Digital Integrated Circuits
9
Introduction – 7 Experimental setup
ID
S
G B
+
-
[0,3.3] step 0,5 V +
-
[0,3.3] step 0,050 V
D
2
3
1
1
+
VDD = 3.3 V
-
+
-
VGS
+
-
VDS
EEL7312 – INE5442
Digital Integrated Circuits
10
Introduction – 8
� Circuit description (SPICE) – PMOS1.cir
� http://www.inf.ufsc.br/~guntzel/ine5442/parametros
Também está disponível – NMOS1.cir
SpiceOpus (c) 1 -> source PMOS1.cirSpiceOpus (c) 2 -> setplotnew New plot
Current const Constant values (constants)SpiceOpus (c) 3 -> dc v3 0 3.3 50m v2 0 3 0.5
SpiceOpus (c) 4 -> plot 1000*i(v3) xlabel VD[V] ylabelID[mA]
EEL7312 – INE5442
Digital Integrated Circuits
11
Introduction – 9
VGS=-3.3 V
VGS=-2.3 V
VGS=-2.8 V
VGS=-1.8 V
VGS=-1.3 V
EEL7312 – INE5442
Digital Integrated Circuits
12
Introduction - 10
The Transistor as a Switch
VGS ≥ VT
Ron
S D
( )0
1
2eq midR R R≡ +
( )2
2
PDSAT DD T
K WI V V
L≡ −
ID
VDS
VGS = VDD
VDD/2 VDD
R0
RmidIDSAT
Source: Rabaey
EEL7312 – INE5442
Digital Integrated Circuits
13
Introduction - 11 CMOS static logic –
the beginning
EEL7312 – INE5442
Digital Integrated Circuits
14
Introduction - 12 CMOS static logic –
the beginning
EEL7312 – INE5442
Digital Integrated Circuits
15
Introduction - 13
CMOS device structure from Frank Wanlass's patent
drawing.U. S. Patent Office.
EEL7312 – INE5442
Digital Integrated Circuits
16
OutIn
VDD
PMOS
NMOSPolysilicon
InOut
VDD
GND
PMOS2λλλλ
Metal 1
NMOS
Contacts
N Well
Source: Rabaey
Introduction - 14 Schematic and layout -1
EEL7312 – INE5442
Digital Integrated Circuits
17
Introduction - 15 Schematic and layout -2
EEL7312 – INE5442
Digital Integrated Circuits
18
Static characteristics - 1
Vin Vout
CL
VDD
Vin 0 VDD
NMOS OFF ON
PMOS ON OFF
Vout VDD 0
Source: Rabaey
VDD VDD
Vin= VDD Vin= 0
VoutVout
Rn
Rp
0
DD TnGSn
TpGSp
V V V
V V
= >
= >
0 TnGSn
DD TpGSp
V V
V V V
= <
= − <
EEL7312 – INE5442
Digital Integrated Circuits
19
Static characteristics - 1
Vin Vout
CL
VDD
Vin 0 VDD
NMOS OFF ON
PMOS ON OFF
Vout VDD 0
Source: Rabaey
VDD VDD
Vin= VDD Vin= 0
VoutVout
Rn
Rp
0
DD TnGSn
TpGSp
V V V
V V
= >
= >
0 TnGSn
DD TpGSp
V V
V V V
= <
= − <
EEL7312 – INE5442
Digital Integrated Circuits
20
Static characteristics - 1
Vin Vout
CL
VDD
Vin 0 VDD
NMOS OFF ON
PMOS ON OFF
Vout VDD 0
Source: Rabaey
VDD VDD
Vin= VDD Vin= 0
VoutVout
Rn
Rp
0
DD TnGSn
TpGSp
V V V
V V
= >
= >
0 TnGSn
DD TpGSp
V V
V V V
= <
= − <
EEL7312 – INE5442
Digital Integrated Circuits
21
Vin Vout
CL
VDD
Source: Rabaey
Voltage swing is equal to the supply voltage;
Logic levels are not dependent upon the relative
device sizes;
In steady state there always exists a path with finite
resistance between the output and either VDD or
ground;
The input resistance →∞;
No direct path exists between supply and ground
rails under steady-state operating conditions (this is
first order approx. and is far from reality in more
advanced technologies) → static power ≈ 0
Static characteristics - 2
EEL7312 – INE5442
Digital Integrated Circuits
22
Source: Rabaey
Static characteristics - 3
Vin = VDD+VGSp
IDn = - IDp
Vout = VDD+VDSp
PMOS Load Line
Vout
IDn
Vin Vout
CL
VDD-
VGSp
+-
VDSp
+
IDp
IDn
VDSp
IDp
VGSp=-2.5
VGSp=-1VDSp
IDn
Vin=0
Vin=1.5
Vin = VDD+VGSpIDn = - IDp
Vout = VDD+VDSp
VDD=2.5 V
Vout
IDn
Vin=0
Vin=1.5
2.5
EEL7312 – INE5442
Digital Integrated Circuits
23
Source: Rabaey
Static characteristics - 4
Vin Vout
VDD-
VGSp
+-
VDSp
+
IDp
IDn
IDn
Vout
Vin= 2.5
2
1.5
Vin= 0
0.5
1
NMOS
Vin= 0
Vin= 0.5
Vin= 1Vin= 1.5
Vin= 2
Vin= 2.5
11.5
PMOS
VTC
Vout
0.5
11.5
22.5
NMOS resPMOS off
NMOS satPMOS sat
NMOS offPMOS res
NMOS satPMOS res
NMOS resPMOS sat
in0.5 1 1.5 2 2.5 V
EEL7312 – INE5442
Digital Integrated Circuits
24Source: Rabaey
Static characteristics - 5
Vin Vout
VDD-
VGSp
+-
VDSp
+
IDp
IDn
IDn
Vout
Vin= 2.5
2
1.5
Vin= 0
0.5
1
NMOS
Vin= 0
Vin= 0.5
Vin= 1Vin= 1.5
Vin= 2
Vin= 2.5
11.5
PMOS
Short-circuit current
IDD
V in0.5 1 1.5 2 2.5
0.5
11. 5
22.5
EEL7312 – INE5442
Digital Integrated Circuits
25Source: Weste & Harris
Static characteristics - 6
Vin Vout
VDD-
VGSp
+-
VDSp
+
IDp
IDn
Switching threshold - 1
EEL7312 – INE5442
Digital Integrated Circuits
26Source: Weste & Harris
Static characteristics - 7
1DSVλ <<
;1 1
M
Tn Tp DDDn Dp
r rV
r r
V V VI I
+= → = +
+ +
Vin Vout
VDD-
VGSp
+-
VDSp
+
IDp
IDn
Switching threshold - 2
Experimental determination of VM: short-circuit between input and output
Vin
Vout
VM
( ) ( ) ( )
( ) ( ) ( )
2 2
22
12 2
12 2
n nn DSn
n n
p p
p DSp DD
p p
Dn Tn M TnGSn
Dp Tp M TpGSp
k W k WV
L L
k kW WV
L L
I V V V V
I V V V V V
λ
λ
= + ≅
= + ≅ −
− −
− −
Usually
( )
( )
/
/
p p
n n
W Lkr
k W L=
Example: VDD=2.5 V, VTp=-0.4 V, VTn=0.43 V. What is VM for r= 0.5, 1.0, and 1.5? Answer: VM=0.98, 1.26, and 1.43 V, respectively.
EEL7312 – INE5442
Digital Integrated Circuits
27Source: Weste & Harris
Static characteristics - 8 Noise margins - 1
Vin Vout
VDD-
VGSp
+-
VDSp
+
IDp
IDn
EEL7312 – INE5442
Digital Integrated Circuits
28Source: Rabaey
Static characteristics - 9 Noise margins - 2
Vin Vout
VDD-
VGSp
+-
VDSp
+
IDp
IDn
Approximate calculation of VIL and VIH
VOH
VOL
Vin
Vout
VM
VIL VIH
For regeneration -g>1, g is the gain in
transition region
EEL7312 – INE5442
Digital Integrated Circuits
29Source: Rabaey
Static characteristics - 10 Scaling the supply voltage
Vin
Vout
VDD
-
VGSp
+-
VDSp
+
IDp
IDn
0 0.05 0.1 0.15 0.20
0.05
0.1
0.15
0.2
Vin (V)
Vo
ut (
V)
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5
Vin (V)
Vo
ut(
V)
Effects of supply voltage reduction:
• Energy dissipation decreases but gate delay increases
• dc characteristic becomes more sensitive to variations in device parameters
• Signal swing reduces making the design more sensitive to external noise
sources that do not scale
EEL7312 – INE5442
Digital Integrated Circuits
30
Impact of Process Variations
0 0.5 1 1.5 2 2.50
0.5
1
1.5
2
2.5
Vin (V)
Vou
t(V)
“Good” PMOS
“Bad” NMOS
Good NMOS
Bad PMOS
Nominal
Source: Rabaey
Static characteristics -11
Wk
Lβ ′=Notes:
1. k’n≈ 2 to 3 k’p2. For βn=βp and VTp=-VTn, VM=VDD/2
Source: Uyemura