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ECE 363 Design Project
Neil Choudhary, Eyad Lababidi, Kate Vance, Matt Bockneck
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Results
• Delay
• Area
• Power
• Metric
![Page 3: ECE 363 Design Project Neil Choudhary, Eyad Lababidi, Kate Vance, Matt Bockneck](https://reader036.vdocument.in/reader036/viewer/2022082821/5697bffb1a28abf838cc0ba5/html5/thumbnails/3.jpg)
Overview of ALU
![Page 4: ECE 363 Design Project Neil Choudhary, Eyad Lababidi, Kate Vance, Matt Bockneck](https://reader036.vdocument.in/reader036/viewer/2022082821/5697bffb1a28abf838cc0ba5/html5/thumbnails/4.jpg)
Inside ALU
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Design and Innovation
• 3:8 Decoder and t-gate vs muxing outputs– Saves power and area
• Separate logic for worst case path
• Manchester adder with inverted carry chain
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Sizing
• Sized to minimize WC delay, rest minimum
• Input registers sized up to drive inputs
• 3:8 Decoder sized up to drive all t-gates
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ADD/SUB
• Only used logic of ADDER + XOR<0:15>• Control - Xor and Carry in<0>• Manchester Carry Chain• Worst case is carrying through propagate
chain• A=<0…00><0..001>• B=<0…00><1…11>• Control=0
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ADD/SUB Optomization
• Place buffers every 4 in carry chain
• Use larger inverters as buffers
• Adapt carry chain to deal with inversion as needed
• Made T-gates larger for less resistance
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Arbitrary Function
• Analog to digital and digital to analog conversion
• All signals must be digitized
• Interesting and non-static implementation
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Comparator
• High gain Differential Amp
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Direct A/D
• Succesive Vrefs
• Large Array Nbits then 2^N Comparators
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Priority Encoder
• 16 bits to 4 bits
• Large but fast
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A/D Conversion
• Resistive ladder and summing amplifier
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A/D in Action
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A/D in Action