ECE 363 Design Project

Neil Choudhary, Eyad Lababidi, Kate Vance, Matt Bockneck

Results

• Delay

• Area

• Power

• Metric

Overview of ALU

Inside ALU

Design and Innovation

• 3:8 Decoder and t-gate vs muxing outputs– Saves power and area

• Separate logic for worst case path

• Manchester adder with inverted carry chain

Sizing

• Sized to minimize WC delay, rest minimum

• Input registers sized up to drive inputs

• 3:8 Decoder sized up to drive all t-gates

ADD/SUB

• Only used logic of ADDER + XOR<0:15>• Control - Xor and Carry in<0>• Manchester Carry Chain• Worst case is carrying through propagate

chain• A=<0…00><0..001>• B=<0…00><1…11>• Control=0

ADD/SUB Optomization

• Place buffers every 4 in carry chain

• Use larger inverters as buffers

• Adapt carry chain to deal with inversion as needed

• Made T-gates larger for less resistance

Arbitrary Function

• Analog to digital and digital to analog conversion

• All signals must be digitized

• Interesting and non-static implementation

Comparator

• High gain Differential Amp

Direct A/D

• Succesive Vrefs

• Large Array Nbits then 2^N Comparators

Priority Encoder

• 16 bits to 4 bits

• Large but fast

A/D Conversion

• Resistive ladder and summing amplifier

A/D in Action

A/D in Action