Download - Fpga creating counter with internal clock
FPGACounter Seven Segment
Created byAkhmad [email protected]
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Background
I try implement counter seven segmen in FPGA
Problem and solution
Problem:First I don't know how to combine counter and decoder in HDL top level. Usualy for my previous project , I do combining design with TOP level schematic.
Solution:I learn about portmap syntax for wiring component in HDL top level
My Design
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is Port ( clk_i : in STD_LOGIC; systick : out STD_LOGIC; counter_o : out STD_LOGIC_VECTOR (3 downto 0));end counter;
architecture Behavioral of counter issignal psc: std_logic_vector(23 downto 0) :=(others=>'0');signal clk_r: std_logic_vector(3 downto 0) :=(others=>'0');signal tick: std_logic :='0';beginprocess (clk_i)begin if rising_edge(clk_i) then if psc